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| author | Yao Qi <yao.qi@linaro.org> | 2016-08-19 14:49:31 +0100 |
|---|---|---|
| committer | Yao Qi <yao.qi@linaro.org> | 2016-08-19 14:51:39 +0100 |
| commit | ded7f5d81cab3eb02cca835f0c9bd9525f35f268 (patch) | |
| tree | a1660e2e35f34fd737ab6aa9c226491ba502dddd /gdb/arm-linux-nat.c | |
| parent | d71004b8fe2ab0f3e1fc6dede74821f7c287f521 (diff) | |
| download | gdb-ded7f5d81cab3eb02cca835f0c9bd9525f35f268.zip gdb-ded7f5d81cab3eb02cca835f0c9bd9525f35f268.tar.gz gdb-ded7f5d81cab3eb02cca835f0c9bd9525f35f268.tar.bz2 | |
[AArch64] Match instruction "STP with base register" in prologue
Nowadays, we only match pre-indexed STP in prologue. Due to the change
in gcc, https://gcc.gnu.org/ml/gcc-patches/2016-07/msg01933.html, it
may generate "STP with base register" in prologue, which GDB doesn't
handle. That is to say, previously GCC generates prologue like this,
sub sp, sp, #490
stp x29, x30, [sp, #-96]!
mov x29, sp
with the gcc patch above, GCC generates prologue like like this,
sub sp, sp, #4f0
stp x29, x30, [sp]
mov x29, sp
This patch is to teach GDB to recognize this instruction in prologue
analysis.
gdb:
2016-08-19 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_analyze_prologue): Handle register
based STP instruction.
Diffstat (limited to 'gdb/arm-linux-nat.c')
0 files changed, 0 insertions, 0 deletions