[ARM] Software single step cross kernel helpers

GDB step cross kernel helpers only works if the kernel helpers are tail
called, which is the case how it is used in glibc.  See __aeabi_read_tp
in sysdeps/unix/sysv/linux/arm/aeabi_read_tp.S.  In __aeabi_read_tp,
branch/jump to the kernel helper is the last instruction, and the next
instruction address is in LR, which is in caller function.  GDB can
handle this correctly.  For example, glibc function __GI___ctype_init
calls __aeabi_read_tp

   0xb6e19b30 <__GI___ctype_init+4>:	ldr	r3, [pc, #80]	;
   0xb6e19b34 <__GI___ctype_init+8>:	bl	0xb6e0a6e0 <__aeabi_read_tp>
   0xb6e19b38 <__GI___ctype_init+12>:	ldr	r3, [pc, r3]

and __aeabi_read_tp calls kernel helper,

(gdb) disassemble __aeabi_read_tp
   0xb6fef5d0 <+0>:	mvn	r0, #61440	; 0xf000
   0xb6fef5d4 <+4>:	sub	pc, r0, #31

once GDB or GDBserver single step instruction on 0xb6fef5d4, LR is
0xb6e19b38, which is right address of next instruction to set breakpoint
on.

However, if the kernel helpers are not tail-called, the LR is still the
address in the caller function of kernel helper's caller, which isn't
the right address of next instruction to set breakpoint on.  For example,
we use kernel helper in main,

(gdb) disassemble main
....
   0x00008624 <+32>:    mov     r3, #4064       ; 0xfe0^M
   0x00008628 <+36>:    movt    r3, #65535      ; 0xffff^M
   0x0000862c <+40>:    blx     r3
   0x00008630 <+44>:    ldr     r3, [r11, #-8]

kernel helper is called on 0x0000862c and the expected next instruction
address is 0x00008630, but the LR now is the return address of main.
The problem here is LR may not have the right address because when we
single step the instruction, it isn't executed yet, so the LR isn't
updated.  This patch fix this problem by decoding instruction, if the
instruction updates LR (BL and BLX), the next instruction address is
PC + INSN_SIZE, otherwise, get the address of next instruction from LR.

gdb:

2016-02-12  Yao Qi  <yao.qi@linaro.org>

	* arch/arm-linux.c (arm_linux_get_next_pcs_fixup): Calculate
	nextpc according to instruction.

gdb/testsuite:

2016-02-12  Yao Qi  <yao.qi@linaro.org>

	* gdb.arch/arm-single-step-kernel-helper.c: New.
	* gdb.arch/arm-single-step-kernel-helper.exp: New.

1 files changed, 66 insertions, 4 deletions

diff --git a/gdb/arch/arm-linux.c b/gdb/arch/arm-linux.c
index 457080c..7e240fe 100644
--- a/gdb/arch/arm-linux.c
+++ b/gdb/arch/arm-linux.c
@@ -68,10 +68,72 @@ arm_linux_get_next_pcs_fixup (struct arm_get_next_pcs *self,
   /* The Linux kernel offers some user-mode helpers in a high page.  We can
      not read this page (as of 2.6.23), and even if we could then we
      couldn't set breakpoints in it, and even if we could then the atomic
-     operations would fail when interrupted.  They are all called as
-     functions and return to the address in LR, so step to there
-     instead.  */
+     operations would fail when interrupted.  They are all (tail) called
+     as functions and return to the address in LR.  However, when GDB single
+     step this instruction, this instruction isn't executed yet, and LR
+     may not be updated yet.  In other words, GDB can get the target
+     address from LR if this instruction isn't BL or BLX.  */
   if (nextpc > 0xffff0000)
-    nextpc = regcache_raw_get_unsigned (self->regcache, ARM_LR_REGNUM);
+    {
+      int bl_blx_p = 0;
+      CORE_ADDR pc = regcache_read_pc (self->regcache);
+      int pc_incr = 0;
+
+      if (self->ops->is_thumb (self))
+	{
+	  unsigned short inst1
+	    = self->ops->read_mem_uint (pc, 2, self->byte_order_for_code);
+
+	  if (bits (inst1, 8, 15) == 0x47 && bit (inst1, 7))
+	    {
+	      /* BLX Rm */
+	      bl_blx_p = 1;
+	      pc_incr = 2;
+	    }
+	  else if (thumb_insn_size (inst1) == 4)
+	    {
+	      unsigned short inst2;
+
+	      inst2 = self->ops->read_mem_uint (pc + 2, 2,
+						self->byte_order_for_code);
+
+	      if ((inst1 & 0xf800) == 0xf000 && bits (inst2, 14, 15) == 0x3)
+		{
+		  /* BL <label> and BLX <label> */
+		  bl_blx_p = 1;
+		  pc_incr = 4;
+		}
+	    }
+
+	  pc_incr = MAKE_THUMB_ADDR (pc_incr);
+	}
+      else
+	{
+	  unsigned int insn
+	    = self->ops->read_mem_uint (pc, 4, self->byte_order_for_code);
+
+	  if (bits (insn, 28, 31) == INST_NV)
+	    {
+	      if (bits (insn, 25, 27) == 0x5) /* BLX <label> */
+		bl_blx_p = 1;
+	    }
+	  else
+	    {
+	      if (bits (insn, 24, 27) == 0xb  /* BL <label> */
+		  || bits (insn, 4, 27) == 0x12fff3 /* BLX Rm */)
+		bl_blx_p = 1;
+	    }
+
+	  pc_incr = 4;
+	}
+
+      /* If the instruction BL or BLX, the target address is the following
+	 instruction of BL or BLX, otherwise, the target address is in LR
+	 already.  */
+      if (bl_blx_p)
+	nextpc = pc + pc_incr;
+      else
+	nextpc = regcache_raw_get_unsigned (self->regcache, ARM_LR_REGNUM);
+    }
   return nextpc;
 }