gdb/riscv: Split ISA and ABI features

The goal of this commit is to allow RV64 binaries compiled for the 'F'
extension to run on a target that supports both the 'F' and 'D'
extensions.

The 'D' extension depends on the 'F' extension and chapter 9 of the
RISC-V ISA manual implies that running a program compiled for 'F' on
a 'D' target should be fine.

To support this the gdbarch now holds two feature sets, one represents
the features that are present on the target, and one represents the
features requested in the ELF flags.

The existing error checks are relaxed slightly to allow binaries
compiled for 32-bit 'F' extension to run on targets with the 64-bit
'D' extension.

A new set of functions called riscv_abi_{xlen,flen} are added to
compliment the existing riscv_isa_{xlen,flen}, and some callers to the
isa functions now call the abi functions when that is appropriate.

In riscv_call_arg_struct two asserts are removed, these asserts no
longer make sense.  The asserts were both like this:

    gdb_assert (TYPE_LENGTH (ainfo->type)
                <= (cinfo->flen + cinfo->xlen));

And were made in two cases, when passing structures like these:

   struct {
     integer field1;
     float   field2;
   };

or,

   struct {
     float   field1;
     integer field2;
   };

When running on an RV64 target which only has 32-bit float then the
integer field could be 64-bits, while if the float field is 32-bits
the overall size of the structure can be 128-bits (with 32-bits of
padding).  In this case the assertion would fail, however, the code
isn't incorrect, so its safe to just remove the assertion.

This was tested by running on an RV64IMFDC target using a compiler
configured for RV64IMFC, and comparing the results with those obtained
when using a compiler configured for RV64IMFDC.  The only regressions
I see (now) are in gdb.base/store.exp and are related too different
code generation choices GCC makes between the two targets.

Finally, this commit does not make any attempt to support running
binaries compiled for RV32 on an RV64 target, though nothing in here
should prevent that being supported in the future.

gdb/ChangeLog:

	* arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>:
	Delete.
	<operator==>: Update with for removed field.
	<hash>: Likewise.
	* riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to...
	<isa_features>: ...this.
	<abi_features>: New field.
	(riscv_isa_flen): Update comment.
	(riscv_abi_xlen): New declaration.
	(riscv_abi_flen): New declaration.
	* riscv-tdep.c (riscv_isa_xlen): Update to get answer from
	isa_features.
	(riscv_abi_xlen): New function.
	(riscv_isa_flen): Update to get answer from isa_features.
	(riscv_abi_flen): New function.
	(riscv_has_fp_abi): Update to get answer from abi_features.
	(riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa
	xlen and flen.
	(riscv_call_info) <xlen, flen>: Update comment.
	(riscv_call_arg_struct): Remove invalid assertions
	(riscv_features_from_gdbarch_info): Update now hw_float_abi field
	is removed.
	(riscv_gdbarch_init): Gather isa features and abi features
	separately, ensure both match on the gdbarch when reusing an old
	gdbarch.  Relax an error check to allow 32-bit abi float to run on
	a target with 64-bit float hardware.

1 files changed, 2 insertions, 13 deletions

diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
index 4a9a80d..05c1905 100644
--- a/gdb/arch/riscv.h
+++ b/gdb/arch/riscv.h
@@ -46,19 +46,10 @@ struct riscv_gdbarch_features
      that there are no f-registers.  No other value is valid.  */
   int flen = 0;
 
-  /* This indicates if hardware floating point abi is in use.  If the FLEN
-     field is 0 then this value _must_ be false.  If the FLEN field is
-     non-zero and this field is false then this indicates the target has
-     floating point registers, but is still using the soft-float abi.  If
-     this field is true then the hardware floating point abi is in use, and
-     values are passed in f-registers matching the size of FLEN.  */
-  bool hw_float_abi = false;
-
   /* Equality operator.  */
   bool operator== (const struct riscv_gdbarch_features &rhs) const
   {
-    return (xlen == rhs.xlen && flen == rhs.flen
-	    && hw_float_abi == rhs.hw_float_abi);
+    return (xlen == rhs.xlen && flen == rhs.flen);
   }
 
   /* Inequality operator.  */
@@ -70,9 +61,7 @@ struct riscv_gdbarch_features
   /* Used by std::unordered_map to hash feature sets.  */
   std::size_t hash () const noexcept
   {
-    std::size_t val = ((xlen & 0x1f) << 6
-                       | (flen & 0x1f) << 1
-                       | (hw_float_abi ? 1 : 0));
+    std::size_t val = ((xlen & 0x1f) << 5 | (flen & 0x1f) << 0);
     return val;
   }
 };