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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-08-11 03:12:52 +0000 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-08-11 13:27:52 +0000 |
| commit | 86dfe011797b3e442622d427e9abd1e0f70f3a62 (patch) | |
| tree | 584d80e095204241722bac9126b3d5081d9b1423 /gdb/arch/riscv.h | |
| parent | 1c450dc2e7626eb7643e5a370b4d5fe3b10f34ed (diff) | |
| download | gdb-86dfe011797b3e442622d427e9abd1e0f70f3a62.zip gdb-86dfe011797b3e442622d427e9abd1e0f70f3a62.tar.gz gdb-86dfe011797b3e442622d427e9abd1e0f70f3a62.tar.bz2 | |
RISC-V: Reflect actual range of vlen for hashing
Before actual vlen handling, fix the riscv_gdbarch_features hashing
function based on the actual valid range of vlen. In bytes, vlen is 0,
or 4 <= xlen <= 8192.
Diffstat (limited to 'gdb/arch/riscv.h')
| -rw-r--r-- | gdb/arch/riscv.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h index d5ea1a5..e1965da 100644 --- a/gdb/arch/riscv.h +++ b/gdb/arch/riscv.h @@ -90,7 +90,7 @@ struct riscv_gdbarch_features | (has_fcsr_reg ? 1 : 0) << 13 | (xlen & 0x1f) << 5 | (flen & 0x1f) << 0 - | (vlen & 0xfff) << 14); + | (vlen & 0x3fff) << 14); return val; } }; |