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authorTom de Vries <tdevries@suse.de>2019-10-18 02:48:08 +0200
committerTom de Vries <tdevries@suse.de>2019-10-18 02:48:08 +0200
commit85102364b2d1845fe9ae7d70096671a3ea4bccf3 (patch)
tree131dd3a2a2dcbec325716193b2fa0c496d6701b7 /gdb/arc-tdep.c
parent39849b0503152de7447b3da67ed9fa45fa9ba5fd (diff)
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[gdb] Fix more typos in comments
Fix typos in comments. NFC. Tested on x86_64-linux. gdb/ChangeLog: 2019-10-18 Tom de Vries <tdevries@suse.de> * aarch64-tdep.c: Fix typos in comments. * ada-lang.c: Same. * ada-tasks.c: Same. * alpha-tdep.c: Same. * alpha-tdep.h: Same. * amd64-nat.c: Same. * amd64-windows-tdep.c: Same. * arc-tdep.c: Same. * arc-tdep.h: Same. * arch-utils.c: Same. * arm-nbsd-tdep.c: Same. * arm-tdep.c: Same. * ax-gdb.c: Same. * blockframe.c: Same. * btrace.c: Same. * c-varobj.c: Same. * coff-pe-read.c: Same. * coffread.c: Same. * cris-tdep.c: Same. * darwin-nat.c: Same. * dbxread.c: Same. * dcache.c: Same. * disasm.c: Same. * dtrace-probe.c: Same. * dwarf-index-write.c: Same. * dwarf2-frame-tailcall.c: Same. * dwarf2-frame.c: Same. * dwarf2read.c: Same. * eval.c: Same. * exceptions.c: Same. * fbsd-tdep.c: Same. * findvar.c: Same. * frame.c: Same. * frv-tdep.c: Same. * gnu-v3-abi.c: Same. * go32-nat.c: Same. * h8300-tdep.c: Same. * hppa-tdep.c: Same. * i386-linux-tdep.c: Same. * i386-tdep.c: Same. * ia64-libunwind-tdep.c: Same. * ia64-tdep.c: Same. * infcmd.c: Same. * infrun.c: Same. * linespec.c: Same. * linux-nat.c: Same. * linux-thread-db.c: Same. * machoread.c: Same. * mdebugread.c: Same. * mep-tdep.c: Same. * mn10300-tdep.c: Same. * namespace.c: Same. * objfiles.c: Same. * opencl-lang.c: Same. * or1k-tdep.c: Same. * osabi.c: Same. * ppc-linux-nat.c: Same. * ppc-linux-tdep.c: Same. * ppc-sysv-tdep.c: Same. * printcmd.c: Same. * procfs.c: Same. * record-btrace.c: Same. * record-full.c: Same. * remote-fileio.c: Same. * remote.c: Same. * rs6000-tdep.c: Same. * s12z-tdep.c: Same. * score-tdep.c: Same. * ser-base.c: Same. * ser-go32.c: Same. * skip.c: Same. * sol-thread.c: Same. * solib-svr4.c: Same. * solib.c: Same. * source.c: Same. * sparc-nat.c: Same. * sparc-sol2-tdep.c: Same. * sparc-tdep.c: Same. * sparc64-tdep.c: Same. * stabsread.c: Same. * stack.c: Same. * symfile.c: Same. * symtab.c: Same. * target-descriptions.c: Same. * target-float.c: Same. * thread.c: Same. * utils.c: Same. * valops.c: Same. * valprint.c: Same. * value.c: Same. * varobj.c: Same. * windows-nat.c: Same. * xcoffread.c: Same. * xstormy16-tdep.c: Same. * xtensa-tdep.c: Same. Change-Id: I5175f1b107bfa4e1cdd4a3361ccb4739e53c75c4
Diffstat (limited to 'gdb/arc-tdep.c')
-rw-r--r--gdb/arc-tdep.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/gdb/arc-tdep.c b/gdb/arc-tdep.c
index 108b671..7f44702 100644
--- a/gdb/arc-tdep.c
+++ b/gdb/arc-tdep.c
@@ -1,4 +1,4 @@
-/* Target dependent code for ARC arhitecture, for GDB.
+/* Target dependent code for ARC architecture, for GDB.
Copyright 2005-2019 Free Software Foundation, Inc.
Contributed by Synopsys Inc.
@@ -1203,7 +1203,7 @@ arc_disassemble_info (struct gdbarch *gdbarch)
If CACHE is not NULL, then it will be filled with information about saved
registers.
- There are several variations of prologue which GDB may encouter. "Full"
+ There are several variations of prologue which GDB may encounter. "Full"
prologue looks like this:
sub sp,sp,<imm> ; Space for variadic arguments.
@@ -1224,7 +1224,7 @@ arc_disassemble_info (struct gdbarch *gdbarch)
store, that doesn't update SP. Like this:
- sub sp,sp,8 ; Create space for calee-saved registers.
+ sub sp,sp,8 ; Create space for callee-saved registers.
st r13,[sp,4] ; Store callee saved registers (up to R26/GP).
st r14,[sp,0]
@@ -1391,7 +1391,7 @@ arc_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
int
arc_delayed_print_insn (bfd_vma addr, struct disassemble_info *info)
{
- /* Standard BFD "machine number" field allows libocodes disassembler to
+ /* Standard BFD "machine number" field allows libopcodes disassembler to
distinguish ARC 600, 700 and v2 cores, however v2 encompasses both ARC EM
and HS, which have some difference between. There are two ways to specify
what is the target core: