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| author | Nelson Chu <nelson.chu@sifive.com> | 2021-08-23 15:46:53 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-10-28 08:50:29 +0800 |
| commit | d035495d996e8a79a3c29d5e6957ef5310fdc86d (patch) | |
| tree | 45e465eb701a492d04c9824c8d0fe9091c46f525 /gdb/annotate.h | |
| parent | 626c2b0d3688ffa02d347737f0878dce33245e1c (diff) | |
| download | gdb-d035495d996e8a79a3c29d5e6957ef5310fdc86d.zip gdb-d035495d996e8a79a3c29d5e6957ef5310fdc86d.tar.gz gdb-d035495d996e8a79a3c29d5e6957ef5310fdc86d.tar.bz2 | |
RISC-V/rvv: Update constraints for widening and narrowing instructions.
* Since fractional LMUL is supported, we cannot just assume LMUL is 1.
Otherwise, the old conflit checking rules may cause problems.
* Removed the overlap constraints for narrowing instructions.
gas/
* testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.d: Removed.
* testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.l: Likewise.
* testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.s: Likewise.
* testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.l: Updated.
* testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.s: Likewise.
opcodes/
* riscv-opc.c (match_vd_neq_vs1_neq_vm): Added for vw*.wv instructions.
(match_widen_vd_neq_vs1_neq_vs2_neq_vm): Replaced by match_vd_neq_vs1_neq_vs2_neq_vm.
(match_widen_vd_neq_vs1_neq_vm): Replaced by match_vd_neq_vs1_neq_vm.
(match_widen_vd_neq_vs2_neq_vm): Replaced by match_vd_neq_vs2_neq_vm.
(match_widen_vd_neq_vm): Replaced by match_vd_neq_vm.
(match_narrow_vd_neq_vs2_neq_vm): Same as match_widen_vd_neq_vs2_neq_vm.
Diffstat (limited to 'gdb/annotate.h')
0 files changed, 0 insertions, 0 deletions