RISC-V: Support svinval extensions.

https://github.com/riscv/riscv-isa-manual/pull/668/files

There are five new instructions for svinval extension.  According to
the above draft spec, two of them (HINVAL.VVMA and HINVAL.GVMA) need
to enable the hypervisor extension.  But there is no implementation
of hypervisor extension in mainline, so let's consider the related
issues later.

                31..25  24..20 19..15 14..12 11...7 6..2  1..0
sinval.vma      0001011 rs2    rs1    000    00000  11100 11
sfence.w.inval  0001100 00000  00000  000    00000  11100 11
sfence.inval.ir 0001100 00001  00000  000    00000  11100 11
hinval.vvma     0011011 rs2    rs1    000    00000  11100 11
hinval.gvma     0111011 rs2    rs1    000    00000  11100 11

bfd/
	* elfxx-riscv.c (riscv_supported_std_s_ext): Added svinval.
gas/
	* config/tc-riscv.c (riscv_extended_subset_supports):
	Handle INSN_CLASS_SVINVAL.
	* testsuite/gas/riscv/extended/extended.exp: Updated.
	* testsuite/gas/riscv/extended/svinval.d: Mew testcases.
	* testsuite/gas/riscv/extended/svinval.s: Likewise.
include/
	* opcode/riscv-opc-extended.h: Added encodings for svinval.
	* opcode/riscv.h (riscv_extended_insn_class): Added INSN_CLASS_SVINVAL.
opcodes/
	* riscv-opc.c (riscv_draft_opcodes): Added svinval instructions.

0 files changed, 0 insertions, 0 deletions