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| author | Lifang Xia <lifang_xia@c-sky.com> | 2021-09-07 17:20:26 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-10-28 08:50:29 +0800 |
| commit | 6099b2e4abcb8de39d7d013da0a7f1f2a57f9c80 (patch) | |
| tree | 4aa24ff979b86712ca42d7170523aad9e2b4a313 /gdb/annotate.h | |
| parent | 65ca6d1e099871462e07f0804b615be9976d2d61 (diff) | |
| download | gdb-6099b2e4abcb8de39d7d013da0a7f1f2a57f9c80.zip gdb-6099b2e4abcb8de39d7d013da0a7f1f2a57f9c80.tar.gz gdb-6099b2e4abcb8de39d7d013da0a7f1f2a57f9c80.tar.bz2 | |
RISC-V/t-head: Add CSRs and opcodes of the T-HEAD XUANTIE CPUs
Add CSRs and opcodes of the XUANTIE CPUs, extensions named "theadc",
"xtheade" and "xtheadse".
New ARG format for operands:
"Xgm@n": encode GPR with m bit at opcode[m+n-1:n].
"Xg5@0": encode GPR with 5 bit at opcode[4:0].
"Xg5@8": encode GPR with 5 bit at opcode[12:8].
"XIm@n": m bits unsigned immediate at opcode[m+n-1:n].
"XI5@0": 5 bits unsigned immediate at opcode[4:0].
"XI4@8": 4 bits unsigned immediate at opcode[11:8].
"XSm@n": m bits signed immediate at opcode[m+n-1:n].
"XS5@0": 5 bits signed immediate at opcode[4:0].
"XS4@8": 4 bits signed immediate at opcode[11:8].
"XFm@n": m bits FR at opcode[m+n-1:n].
"XF5@0": 5 bits FR at opcode[4:0].
"XF5@0": 5 bits FR at opcode[4:0].
bfd/
* cpu-riscv.h (enum riscv_spec_class)
<VENDOR_SPEC_CLASS_THEAD>: New.
* elfxx-riscv.c (riscv_supported_vendor_thead_ext): New.
(riscv_all_supported_ext): Updated.
(riscv_get_default_ext_version): Updated.
gas/
* config/tc-riscv.c (VENDOR_THEAD_EXT): New.
(enum riscv_extended_csr_class) <CSR_CLASS_VENDOR_THEAD>: New.
(riscv_extended_subset_supports): Check subset: INSN_CLASS_THEAD*
(op_vendor_thead_hash): New, the hash of T-HEAD Xuantie's opcodes.
(riscv_csr_address): Skip check version for T-HEAD Xuantie CPUs.
(validate_riscv_extended_insn): Parsing T-HEAD opargs.
(md_begin): Init op_vendor_thead_hash.
(riscv_find_extended_opcode_hash): Search op_vendor_thead_hash.
(riscv_parse_extended_operands): Parsing T-HEAD opargs.
* testsuite/gas/riscv/extended/thead*: New testcases.
include/
* opcode/riscv-opc-extended.h: Add CSRs and opcode of the T-HEAD
XUANTIE CPUs.
* opcode/riscv.h (riscv_extended_insn_class)
<INSN_CLASS_THEADC>: New.
<INSN_CLASS_THEADC_OR_THEADE>: New.
<INSN_CLASS_THEADC_OR_THEADE_OR_THEADSE>: New.
<INSN_CLASS_THEADE>: New.
<INSN_CLASS_THEADSE>: New.
(*VENDOR_THEAD_*): T-HEAD IMM encoding.
opcodes/
* riscv-dis.c (print_extended_insn_args): Parsing T-HEAD opargs.
* riscv-opc.c (match_thead_rd1_rd2_neq_rs1): New.
(riscv_vendor_thead_opcodes): New.
(riscv_extended_opcodes): Add riscv_vendor_thead_opcodes.
Diffstat (limited to 'gdb/annotate.h')
0 files changed, 0 insertions, 0 deletions