diff options
author | H.J. Lu <hjl.tools@gmail.com> | 2010-04-07 18:46:50 +0000 |
---|---|---|
committer | H.J. Lu <hjl.tools@gmail.com> | 2010-04-07 18:46:50 +0000 |
commit | a055a18785d694f50a4ebc8d36579ed20ffd3069 (patch) | |
tree | a10bec1357e03752dcbd479658e33b87ba98cd21 /gdb/amd64-tdep.h | |
parent | 31aeac7844e6e347a01fa69178fd1014e69578c0 (diff) | |
download | gdb-a055a18785d694f50a4ebc8d36579ed20ffd3069.zip gdb-a055a18785d694f50a4ebc8d36579ed20ffd3069.tar.gz gdb-a055a18785d694f50a4ebc8d36579ed20ffd3069.tar.bz2 |
Support amd64 AVX.
gdb/
2010-04-07 H.J. Lu <hongjiu.lu@intel.com>
* amd64-linux-nat.c: Include "regset.h", "elf/common.h",
<sys/uio.h> and "i386-xstate.h".
(PTRACE_GETREGSET): New.
(PTRACE_SETREGSET): Likewise.
(have_ptrace_getregset): Likewise.
(amd64_linux_gregset64_reg_offset): Include 16 upper YMM
registers.
(amd64_linux_gregset32_reg_offset): Include 8 upper YMM
registers.
(amd64_linux_fetch_inferior_registers): Support PTRACE_GETFPREGS.
(amd64_linux_store_inferior_registers): Likewise.
(amd64_linux_read_description): Check and enable AVX target
descriptions.
* amd64-linux-tdep.c: Include "regset.h", "i386-linux-tdep.h"
and "features/i386/amd64-avx-linux.c".
(amd64_linux_regset_sections): New.
(amd64_linux_core_read_description): Check and enable AVX
target description.
(amd64_linux_init_abi): Set xsave_xcr0_offset. Call
set_gdbarch_core_regset_sections.
(_initialize_amd64_linux_tdep): Call
initialize_tdesc_amd64_avx_linux.
* amd64-linux-tdep.h (AMD64_LINUX_ORIG_RAX_REGNUM): Replace
AMD64_MXCSR_REGNUM with AMD64_YMM15H_REGNUM.
(tdesc_amd64_avx_linux): New.
(amd64_linux_update_xstateregset): Likewise.
* amd64-tdep.c: Include "features/i386/amd64-avx.c".
(amd64_ymm_names): New.
(amd64_ymmh_names): Likewise.
(amd64_register_name): Likewise.
(amd64_supply_xstateregset): Likewise.
(amd64_collect_xstateregset): Likewise.
(amd64_supply_xsave): Likewise.
(amd64_collect_xsave): Likewise.
(AMD64_NUM_REGS): Removed.
(amd64_dwarf_reg_to_regnum): Return %ymmN register number for
%xmmN if AVX is available.
(amd64_pseudo_register_name): Support pseudo YMM registers.
(amd64_regset_from_core_section): Support .reg-xstate section.
(amd64_init_abi): Set ymmh_register_names, num_ymm_regs
and ymm0h_regnum. Call set_gdbarch_register_name.
(amd64_init_abi): Call initialize_tdesc_amd64_avx.
* amd64-tdep.h (amd64_regnum): Add AMD64_YMM0H_REGNUM and
AMD64_YMM15H_REGNUM.
(AMD64_NUM_REGS): New.
(amd64_supply_xsave): Likewise.
(amd64_collect_xsave): Likewise.
(amd64_register_name): Removed.
(amd64_register_type): Likewise.
gdb/testsuite/
2010-04-07 H.J. Lu <hongjiu.lu@intel.com>
* gdb.arch/i386-avx.c: New.
* gdb.arch/i386-avx.exp: Likewise.
* gdb.arch/i386-cpuid.h: Updated from gcc 4.4.
Diffstat (limited to 'gdb/amd64-tdep.h')
-rw-r--r-- | gdb/amd64-tdep.h | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/gdb/amd64-tdep.h b/gdb/amd64-tdep.h index 363479c..9f07dda 100644 --- a/gdb/amd64-tdep.h +++ b/gdb/amd64-tdep.h @@ -61,12 +61,16 @@ enum amd64_regnum AMD64_FSTAT_REGNUM = AMD64_ST0_REGNUM + 9, AMD64_XMM0_REGNUM = 40, /* %xmm0 */ AMD64_XMM1_REGNUM, /* %xmm1 */ - AMD64_MXCSR_REGNUM = AMD64_XMM0_REGNUM + 16 + AMD64_MXCSR_REGNUM = AMD64_XMM0_REGNUM + 16, + AMD64_YMM0H_REGNUM, /* %ymm0h */ + AMD64_YMM15H_REGNUM = AMD64_YMM0H_REGNUM + 15 }; /* Number of general purpose registers. */ #define AMD64_NUM_GREGS 24 +#define AMD64_NUM_REGS (AMD64_YMM15H_REGNUM + 1) + extern struct displaced_step_closure *amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs); @@ -77,12 +81,6 @@ extern void amd64_displaced_step_fixup (struct gdbarch *gdbarch, extern void amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch); -/* Functions from amd64-tdep.c which may be needed on architectures - with extra registers. */ - -extern const char *amd64_register_name (struct gdbarch *gdbarch, int regnum); -extern struct type *amd64_register_type (struct gdbarch *gdbarch, int regnum); - /* Fill register REGNUM in REGCACHE with the appropriate floating-point or SSE register value from *FXSAVE. If REGNUM is -1, do this for all registers. This function masks off any of the @@ -91,6 +89,10 @@ extern struct type *amd64_register_type (struct gdbarch *gdbarch, int regnum); extern void amd64_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave); +/* Similar to amd64_supply_fxsave, but use XSAVE extended state. */ +extern void amd64_supply_xsave (struct regcache *regcache, int regnum, + const void *xsave); + /* Fill register REGNUM (if it is a floating-point or SSE register) in *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for all registers. This function doesn't touch any of the reserved @@ -99,6 +101,10 @@ extern void amd64_supply_fxsave (struct regcache *regcache, int regnum, extern void amd64_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave); +/* Similar to amd64_collect_fxsave, but but use XSAVE extended state. */ +extern void amd64_collect_xsave (const struct regcache *regcache, + int regnum, void *xsave, int gcore); + void amd64_classify (struct type *type, enum amd64_reg_class class[2]); |