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| author | John Baldwin <jhb@FreeBSD.org> | 2019-03-12 13:39:02 -0700 |
|---|---|---|
| committer | John Baldwin <jhb@FreeBSD.org> | 2019-03-12 13:45:23 -0700 |
| commit | dd6876c91cd40cc105b1a91f418ca2c80683b314 (patch) | |
| tree | 394033e0658212a6461dd32784d158ff1d16f6e6 /gdb/amd64-fbsd-nat.c | |
| parent | 1163a4b7a38a79ebd153dc5ee76ce93877d21dbd (diff) | |
| download | gdb-dd6876c91cd40cc105b1a91f418ca2c80683b314.zip gdb-dd6876c91cd40cc105b1a91f418ca2c80683b314.tar.gz gdb-dd6876c91cd40cc105b1a91f418ca2c80683b314.tar.bz2 | |
Support fs_base and gs_base on FreeBSD/i386.
The i386 BSD native target uses the same ptrace operations
(PT_[GS]ET[FG]SBASE) as the amd64 BSD native target to fetch and store
the registers.
The amd64 BSD native now uses 'tdep->fsbase_regnum' instead of
hardcoding AMD64_FSBASE_REGNUM and AMD64_GSBASE_REGNUM to support
32-bit targets. In addition, the store operations explicitly zero the
new register value before fetching it from the register cache to
ensure 32-bit values are zero-extended.
gdb/ChangeLog:
* amd64-bsd-nat.c (amd64bsd_fetch_inferior_registers): Use
tdep->fsbase_regnum instead of constants for fs_base and gs_base.
(amd64bsd_store_inferior_registers): Likewise.
* amd64-fbsd-nat.c (amd64_fbsd_nat_target::read_description):
Enable segment base registers.
* i386-bsd-nat.c (i386bsd_fetch_inferior_registers): Use
PT_GETFSBASE and PT_GETGSBASE.
(i386bsd_store_inferior_registers): Use PT_SETFSBASE and
PT_SETGSBASE.
* i386-fbsd-nat.c (i386_fbsd_nat_target::read_description): Enable
segment base registers.
* i386-fbsd-tdep.c (i386fbsd_core_read_description): Likewise.
Diffstat (limited to 'gdb/amd64-fbsd-nat.c')
| -rw-r--r-- | gdb/amd64-fbsd-nat.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gdb/amd64-fbsd-nat.c b/gdb/amd64-fbsd-nat.c index 9fff763..cc676d3 100644 --- a/gdb/amd64-fbsd-nat.c +++ b/gdb/amd64-fbsd-nat.c @@ -190,13 +190,13 @@ amd64_fbsd_nat_target::read_description () if (is64) return amd64_target_description (xcr0, true); else - return i386_target_description (xcr0, false); + return i386_target_description (xcr0, true); } #endif if (is64) return amd64_target_description (X86_XSTATE_SSE_MASK, true); else - return i386_target_description (X86_XSTATE_SSE_MASK, false); + return i386_target_description (X86_XSTATE_SSE_MASK, true); } #if defined(HAVE_PT_GETDBREGS) && defined(USE_SIGTRAP_SIGINFO) |