AArch64: Allow additional sizes in prologue

When saving registers to the stack at the start of a function, not all state
needs to be saved. For example, only the first 64bits of float registers need
saving.  However, a program may choose to store extra state if it wishes,
there is nothing preventing it doing so.

The aarch64_analyze_prologue will error if it detects extra state being
stored.  Relex this restriction.

Tested via aarch64-prologue test.

gdb/ChangeLog:

	* aarch64-tdep.c (aarch64_analyze_prologue): Allow any valid
	register sizes.

gdb/testsuite/ChangeLog:

	* gdb.arch/aarch64-prologue.c: New test.
	* gdb.arch/aarch64-prologue.exp: New file.

1 files changed, 10 insertions, 22 deletions

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 9b6324f..5e9f7b8 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -387,17 +387,16 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
 	{
 	  unsigned rt = inst.operands[0].reg.regno;
 	  unsigned rn = inst.operands[1].addr.base_regno;
-	  int is64
-	    = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
+	  int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
 
 	  gdb_assert (aarch64_num_of_operands (inst.opcode) == 2);
 	  gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
 	  gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9);
 	  gdb_assert (!inst.operands[1].addr.offset.is_reg);
 
-	  stack.store (pv_add_constant (regs[rn],
-					inst.operands[1].addr.offset.imm),
-		       is64 ? 8 : 4, regs[rt]);
+	  stack.store
+	    (pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm),
+	     size, regs[rt]);
 	}
       else if ((inst.opcode->iclass == ldstpair_off
 		|| (inst.opcode->iclass == ldstpair_indexed
@@ -409,6 +408,7 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
 	  unsigned rt2;
 	  unsigned rn = inst.operands[2].addr.base_regno;
 	  int32_t imm = inst.operands[2].addr.offset.imm;
+	  int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
 
 	  gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
 		      || inst.operands[0].type == AARCH64_OPND_Ft);
@@ -430,17 +430,12 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
 	  rt2 = inst.operands[1].reg.regno;
 	  if (inst.operands[0].type == AARCH64_OPND_Ft)
 	    {
-	      /* Only bottom 64-bit of each V register (D register) need
-		 to be preserved.  */
-	      gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
 	      rt1 += AARCH64_X_REGISTER_COUNT;
 	      rt2 += AARCH64_X_REGISTER_COUNT;
 	    }
 
-	  stack.store (pv_add_constant (regs[rn], imm), 8,
-		       regs[rt1]);
-	  stack.store (pv_add_constant (regs[rn], imm + 8), 8,
-		       regs[rt2]);
+	  stack.store (pv_add_constant (regs[rn], imm), size, regs[rt1]);
+	  stack.store (pv_add_constant (regs[rn], imm + size), size, regs[rt2]);
 
 	  if (inst.operands[2].addr.writeback)
 	    regs[rn] = pv_add_constant (regs[rn], imm);
@@ -457,21 +452,14 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
 	  unsigned int rt = inst.operands[0].reg.regno;
 	  int32_t imm = inst.operands[1].addr.offset.imm;
 	  unsigned int rn = inst.operands[1].addr.base_regno;
-	  bool is64
-	    = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8);
+	  int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier);
 	  gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
 		      || inst.operands[0].type == AARCH64_OPND_Ft);
 
 	  if (inst.operands[0].type == AARCH64_OPND_Ft)
-	    {
-	      /* Only bottom 64-bit of each V register (D register) need
-		 to be preserved.  */
-	      gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
-	      rt += AARCH64_X_REGISTER_COUNT;
-	    }
+	    rt += AARCH64_X_REGISTER_COUNT;
 
-	  stack.store (pv_add_constant (regs[rn], imm),
-		       is64 ? 8 : 4, regs[rt]);
+	  stack.store (pv_add_constant (regs[rn], imm), size, regs[rt]);
 	  if (inst.operands[1].addr.writeback)
 	    regs[rn] = pv_add_constant (regs[rn], imm);
 	}