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authorSimon Marchi <simon.marchi@polymtl.ca>2017-05-02 13:30:07 -0400
committerSimon Marchi <simon.marchi@ericsson.com>2017-05-02 13:30:07 -0400
commita0ff9e1ad221c11f58a9d8d12a84c21579132d85 (patch)
treea3fc20fdc0445a738432cf73ac65d4d4616c4b65 /gdb/aarch64-tdep.c
parentea480a306d46efe3dd1839618137f0e73a80e9b3 (diff)
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Change return type of gdbarch_software_single_step to vector<CORE_ADDR>
This is a relatively straightforward patch that changes gdbarch_software_single_step so it returns an std::vector<CORE_ADDR> instead of a VEC (CORE_ADDR). gdb/ChangeLog: * gdbarch.sh (software_single_step): Change return type to std::vector<CORE_ADDR>. * gdbarch.c, gdbarch.h: Re-generate. * arch/arm-get-next-pcs.c (thumb_deal_with_atomic_sequence_raw): Adjust. (arm_deal_with_atomic_sequence_raw): Adjust. (thumb_get_next_pcs_raw): Adjust. (arm_get_next_pcs_raw): Adjust. (arm_get_next_pcs): Adjust. * arch/arm-get-next-pcs.h (arm_get_next_pcs): Adjust. * aarch64-tdep.c (aarch64_software_single_step): Adjust. * alpha-tdep.c (alpha_deal_with_atomic_sequence): Adjust. (alpha_software_single_step): Adjust. * alpha-tdep.h (alpha_software_single_step): Adjust. * arm-linux-tdep.c (arm_linux_software_single_step): Adjust. * arm-tdep.c (arm_software_single_step): Adjust. (arm_breakpoint_kind_from_current_state): Adjust. * arm-tdep.h (arm_software_single_step): Adjust. * breakpoint.c (insert_single_step_breakpoint): Adjust. * cris-tdep.c (cris_software_single_step): Adjust. * mips-tdep.c (mips_deal_with_atomic_sequence): Adjust. (micromips_deal_with_atomic_sequence): Adjust. (deal_with_atomic_sequence): Adjust. (mips_software_single_step): Adjust. * mips-tdep.h (mips_software_single_step): Adjust. * moxie-tdep.c (moxie_software_single_step): Adjust. * nios2-tdep.c (nios2_software_single_step): Adjust. * ppc-tdep.h (ppc_deal_with_atomic_sequence): Adjust. * rs6000-aix-tdep.c (rs6000_software_single_step): Adjust. * rs6000-tdep.c (ppc_deal_with_atomic_sequence): Adjust. * s390-linux-tdep.c (s390_software_single_step): Adjust. * sparc-tdep.c (sparc_software_single_step): Adjust. * spu-tdep.c (spu_software_single_step): Adjust. * tic6x-tdep.c (tic6x_software_single_step): Adjust. gdb/gdbserver/ChangeLog: * linux-arm-low.c (arm_gdbserver_get_next_pcs): Adjust to software_single_step change of return type to std::vector<CORE_ADDR>. * linux-low.c (install_software_single_step_breakpoints): Likewise. * linux-low.h (install_software_single_step_breakpoints): Likewise.
Diffstat (limited to 'gdb/aarch64-tdep.c')
-rw-r--r--gdb/aarch64-tdep.c17
1 files changed, 9 insertions, 8 deletions
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index d203ebe..000540a 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -2417,7 +2417,7 @@ value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
/* Implement the "software_single_step" gdbarch method, needed to
single step through atomic sequences on AArch64. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
aarch64_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
@@ -2435,14 +2435,13 @@ aarch64_software_single_step (struct regcache *regcache)
int bc_insn_count = 0; /* Conditional branch instruction count. */
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
aarch64_inst inst;
- VEC (CORE_ADDR) *next_pcs = NULL;
if (aarch64_decode_insn (insn, &inst, 1) != 0)
- return NULL;
+ return {};
/* Look for a Load Exclusive instruction which begins the sequence. */
if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
- return NULL;
+ return {};
for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
{
@@ -2451,14 +2450,14 @@ aarch64_software_single_step (struct regcache *regcache)
byte_order_for_code);
if (aarch64_decode_insn (insn, &inst, 1) != 0)
- return NULL;
+ return {};
/* Check if the instruction is a conditional branch. */
if (inst.opcode->iclass == condbranch)
{
gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
if (bc_insn_count >= 1)
- return NULL;
+ return {};
/* It is, so we'll try to set a breakpoint at the destination. */
breaks[1] = loc + inst.operands[0].imm.value;
@@ -2477,7 +2476,7 @@ aarch64_software_single_step (struct regcache *regcache)
/* We didn't find a closing Store Exclusive instruction, fall back. */
if (!closing_insn)
- return NULL;
+ return {};
/* Insert breakpoint after the end of the atomic sequence. */
breaks[0] = loc + insn_size;
@@ -2489,10 +2488,12 @@ aarch64_software_single_step (struct regcache *regcache)
|| (breaks[1] >= pc && breaks[1] <= closing_insn)))
last_breakpoint = 0;
+ std::vector<CORE_ADDR> next_pcs;
+
/* Insert the breakpoint at the end of the sequence, and one at the
destination of the conditional branch, if it exists. */
for (index = 0; index <= last_breakpoint; index++)
- VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
+ next_pcs.push_back (breaks[index]);
return next_pcs;
}