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| author | Yao Qi <yao.qi@linaro.org> | 2015-10-05 11:15:58 +0100 |
|---|---|---|
| committer | Yao Qi <yao.qi@linaro.org> | 2015-10-28 14:22:57 +0000 |
| commit | 43cdf5aeb8ae6ac2ec3bdbf636cbb2731ccbbb2a (patch) | |
| tree | 69ea73c3be6425045db21170af2694f58dc5cc49 /gdb/aarch64-tdep.c | |
| parent | 82188b295de579bee5f68de9f4d76ce4a3d41aa9 (diff) | |
| download | gdb-43cdf5aeb8ae6ac2ec3bdbf636cbb2731ccbbb2a.zip gdb-43cdf5aeb8ae6ac2ec3bdbf636cbb2731ccbbb2a.tar.gz gdb-43cdf5aeb8ae6ac2ec3bdbf636cbb2731ccbbb2a.tar.bz2 | |
Pass noaliases_p to aarch64_decode_insn
Nowadays aarch64_decode_insn is a public interface used by both
opcodes and gdb. However, its behaviour relies on a global variable
no_aliases, which isn't a good practise. On the other hand, In default,
no_aliases is zero, but in GDB, we do want no alias when decoding
instructions for prologue analysis (patches to be posted), so that we
can handle both instructions "add" and "mov" (an alias of "add") as
"add". The code in GDB can be simplified.
This patch adds a new argument in aarch64_decode_insn, and pass no_aliases
to it. In GDB side, always pass 1 to it.
include/opcode:
2015-10-28 Yao Qi <yao.qi@linaro.org>
* aarch64.h (aarch64_decode_insn): Update declaration.
opcodes:
2015-10-28 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c (aarch64_decode_insn): Add one argument
noaliases_p. Update comments. Pass noaliases_p rather than
no_aliases to aarch64_opcode_decode.
(print_insn_aarch64_word): Pass no_aliases to
aarch64_decode_insn.
gdb:
2015-10-28 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_software_single_step): Pass 1 to
aarch64_decode_insn.
Diffstat (limited to 'gdb/aarch64-tdep.c')
| -rw-r--r-- | gdb/aarch64-tdep.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 55c5fb8..d01a83f 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -2499,7 +2499,7 @@ aarch64_software_single_step (struct frame_info *frame) int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ aarch64_inst inst; - if (aarch64_decode_insn (insn, &inst) != 0) + if (aarch64_decode_insn (insn, &inst, 1) != 0) return 0; /* Look for a Load Exclusive instruction which begins the sequence. */ @@ -2512,7 +2512,7 @@ aarch64_software_single_step (struct frame_info *frame) insn = read_memory_unsigned_integer (loc, insn_size, byte_order_for_code); - if (aarch64_decode_insn (insn, &inst) != 0) + if (aarch64_decode_insn (insn, &inst, 1) != 0) return 0; /* Check if the instruction is a conditional branch. */ if (inst.opcode->iclass == condbranch) |