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| author | Luis Machado <luis.machado@linaro.org> | 2020-12-14 11:40:01 -0300 |
|---|---|---|
| committer | Luis Machado <luis.machado@linaro.org> | 2020-12-16 10:08:47 -0300 |
| commit | bfbe4b84606cb9b8ac6f51b473b1d351924080aa (patch) | |
| tree | e9b72f8b18021826665379be53fb25a1ebb67b7c /gdb/aarch64-tdep.c | |
| parent | 19007d955670a183fdf79408301d403b43eb7db1 (diff) | |
| download | gdb-bfbe4b84606cb9b8ac6f51b473b1d351924080aa.zip gdb-bfbe4b84606cb9b8ac6f51b473b1d351924080aa.tar.gz gdb-bfbe4b84606cb9b8ac6f51b473b1d351924080aa.tar.bz2 | |
Record FPSR for SIMD/FP data instructions
I noticed this failure in gdb.reverse/reverse-insn.exp:
FAIL: gdb.reverse/insn-reverse.exp: adv_simd_vect_shift: compare registers on insn 0:fcvtzs s0, s0, #1
Turns out we're not recording changes to the FPSR. The SIMD/FP data
instructions may set bits in the FPSR, so it needs to be recorded for
proper reverse operations.
gdb/ChangeLog:
2020-12-16 Luis Machado <luis.machado@linaro.org>
* aarch64-tdep.c (aarch64_record_data_proc_simd_fp): Record FPSR.
Diffstat (limited to 'gdb/aarch64-tdep.c')
| -rw-r--r-- | gdb/aarch64-tdep.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 40c73be..5858b64 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -4470,8 +4470,15 @@ aarch64_record_data_proc_simd_fp (insn_decode_record *aarch64_insn_r) if (record_debug) debug_printf ("\n"); + /* Record the V/X register. */ aarch64_insn_r->reg_rec_count++; - gdb_assert (aarch64_insn_r->reg_rec_count == 1); + + /* Some of these instructions may set bits in the FPSR, so record it + too. */ + record_buf[1] = AARCH64_FPSR_REGNUM; + aarch64_insn_r->reg_rec_count++; + + gdb_assert (aarch64_insn_r->reg_rec_count == 2); REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, record_buf); return AARCH64_RECORD_SUCCESS; |