AArch64: Implement memory tagging target methods for AArch64

The patch implements the memory tagging target hooks for AArch64, so we
can handle MTE.

gdb/ChangeLog:

2021-03-24  Luis Machado  <luis.machado@linaro.org>

	* Makefile.in (ALL_64_TARGET_OBS): Add arch/aarch64-mte-linux.o.
	(HFILES_NO_SRCDIR): Add arch/aarch64-mte-linux.h and
	nat/aarch64-mte-linux-ptrace.h.
	* aarch64-linux-nat.c: Include nat/aarch64-mte-linux-ptrace.h.
	(aarch64_linux_nat_target) <supports_memory_tagging>: New method
	override.
	<fetch_memtags>: New method override.
	<store_memtags>: New method override.
	(aarch64_linux_nat_target::supports_memory_tagging): New method.
	(aarch64_linux_nat_target::fetch_memtags): New method.
	(aarch64_linux_nat_target::store_memtags): New method.
	* arch/aarch64-mte-linux.c: New file.
	* arch/aarch64-mte-linux.h: Include gdbsupport/common-defs.h.
	(AARCH64_MTE_GRANULE_SIZE): Define.
	(aarch64_memtag_type): New enum.
	(aarch64_mte_get_tag_granules): New prototype.
	* configure.nat (NATDEPFILES): Add nat/aarch64-mte-linux-ptrace.o.
	* configure.tgt (aarch64*-*-linux*): Add arch/aarch64-mte-linux.o.
	* nat/aarch64-mte-linux-ptrace.c: New file.
	* nat/aarch64-mte-linux-ptrace.h: New file.

1 files changed, 50 insertions, 0 deletions

diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c
index fe3ba44..ae8db29 100644
--- a/gdb/aarch64-linux-nat.c
+++ b/gdb/aarch64-linux-nat.c
@@ -52,6 +52,8 @@
 
 #include "arch/aarch64-mte-linux.h"
 
+#include "nat/aarch64-mte-linux-ptrace.h"
+
 #ifndef TRAP_HWBKPT
 #define TRAP_HWBKPT 0x0004
 #endif
@@ -102,6 +104,16 @@ public:
     override;
 
   struct gdbarch *thread_architecture (ptid_t) override;
+
+  bool supports_memory_tagging () override;
+
+  /* Read memory allocation tags from memory via PTRACE.  */
+  bool fetch_memtags (CORE_ADDR address, size_t len,
+		      gdb::byte_vector &tags, int type) override;
+
+  /* Write allocation tags to memory via PTRACE.  */
+  bool store_memtags (CORE_ADDR address, size_t len,
+		      const gdb::byte_vector &tags, int type) override;
 };
 
 static aarch64_linux_nat_target the_aarch64_linux_nat_target;
@@ -1054,6 +1066,44 @@ aarch64_linux_nat_target::thread_architecture (ptid_t ptid)
   return gdbarch_find_by_info (info);
 }
 
+/* Implement the "supports_memory_tagging" target_ops method.  */
+
+bool
+aarch64_linux_nat_target::supports_memory_tagging ()
+{
+  return (linux_get_hwcap2 (this) & HWCAP2_MTE) != 0;
+}
+
+/* Implement the "fetch_memtags" target_ops method.  */
+
+bool
+aarch64_linux_nat_target::fetch_memtags (CORE_ADDR address, size_t len,
+					 gdb::byte_vector &tags, int type)
+{
+  int tid = get_ptrace_pid (inferior_ptid);
+
+  /* Allocation tags?  */
+  if (type == static_cast<int> (aarch64_memtag_type::mte_allocation))
+    return aarch64_mte_fetch_memtags (tid, address, len, tags);
+
+  return false;
+}
+
+/* Implement the "store_memtags" target_ops method.  */
+
+bool
+aarch64_linux_nat_target::store_memtags (CORE_ADDR address, size_t len,
+					 const gdb::byte_vector &tags, int type)
+{
+  int tid = get_ptrace_pid (inferior_ptid);
+
+  /* Allocation tags?  */
+  if (type == static_cast<int> (aarch64_memtag_type::mte_allocation))
+    return aarch64_mte_store_memtags (tid, address, len, tags);
+
+  return false;
+}
+
 /* Define AArch64 maintenance commands.  */
 
 static void