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author | John Baldwin <jhb@FreeBSD.org> | 2018-09-11 17:53:37 +0000 |
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committer | John Baldwin <jhb@FreeBSD.org> | 2018-09-12 16:10:42 -0700 |
commit | 88f22c34d0f39ee4aca87940bff2cbf47e64b9d7 (patch) | |
tree | a78e458780e1386582c4aefb4784d8407a417213 /gdb/aarch64-fbsd-tdep.h | |
parent | 4aa8e6c2387e796649279c2190cd499b579d028c (diff) | |
download | gdb-88f22c34d0f39ee4aca87940bff2cbf47e64b9d7.zip gdb-88f22c34d0f39ee4aca87940bff2cbf47e64b9d7.tar.gz gdb-88f22c34d0f39ee4aca87940bff2cbf47e64b9d7.tar.bz2 |
Fix a typo in a comment.
gdb/ChangeLog:
* aarch64-fbsd-tdep.h (AARCH64_FBSD_SIZEOF_GREGSET): Fix comment
typo.
Diffstat (limited to 'gdb/aarch64-fbsd-tdep.h')
-rw-r--r-- | gdb/aarch64-fbsd-tdep.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gdb/aarch64-fbsd-tdep.h b/gdb/aarch64-fbsd-tdep.h index 4515ea8..a086834 100644 --- a/gdb/aarch64-fbsd-tdep.h +++ b/gdb/aarch64-fbsd-tdep.h @@ -21,7 +21,7 @@ /* The general-purpose regset consists of 30 X registers, plus LR, SP, ELR, and SPSR registers. SPSR is 32 bits but the structure is - passed to 64 bit alignment. */ + padded to 64 bit alignment. */ #define AARCH64_FBSD_SIZEOF_GREGSET (34 * X_REGISTER_SIZE) /* The fp regset consists of 32 V registers, plus FPSR and FPCR which |