[ARM] Clear reserved bits in CPSR

Bits 20 ~ 23 of CPSR are reserved (RAZ, read as zero), but they are not
zero if the arm program runs on aarch64-linux.  AArch64 tracer gets PSTATE
from arm 32-bit tracee as CPSR, but bits 20 ~ 23 are used in PSTATE.  I
think kernel should clear these bits when it is read through ptrace, but
the fix in user space is still needed.

This patch fixes these two fails,

-FAIL: gdb.reverse/insn-reverse.exp: ext_reg_push_pop: compare registers on insn 0:vldr	d7, [r11, #-12]
-FAIL: gdb.reverse/insn-reverse.exp: ext_reg_push_pop: compare registers on insn 0:vldr	d7, [r7]

gdb:

2016-04-22  Yao Qi  <yao.qi@linaro.org>

	* aarch32-linux-nat.c (aarch32_gp_regcache_supply): Clear CPSR
	bits 20 to 23.

gdb/gdbserver:

2016-04-22  Yao Qi  <yao.qi@linaro.org>

	* linux-aarch32-low.c (arm_store_gregset): Clear CPSR bits 20
	to 23.

1 files changed, 5 insertions, 1 deletions

diff --git a/gdb/aarch32-linux-nat.c b/gdb/aarch32-linux-nat.c
index 568dfa6..72bf644 100644
--- a/gdb/aarch32-linux-nat.c
+++ b/gdb/aarch32-linux-nat.c
@@ -37,7 +37,11 @@ aarch32_gp_regcache_supply (struct regcache *regcache, uint32_t *regs,
     regcache_raw_supply (regcache, regno, &regs[regno]);
 
   if (arm_apcs_32)
-    regcache_raw_supply (regcache, ARM_PS_REGNUM, &regs[ARM_CPSR_GREGNUM]);
+    {
+      /* Clear reserved bits bit 20 to bit 23.  */
+      regs[ARM_CPSR_GREGNUM] &= 0xff0fffff;
+      regcache_raw_supply (regcache, ARM_PS_REGNUM, &regs[ARM_CPSR_GREGNUM]);
+    }
   else
     regcache_raw_supply (regcache, ARM_PS_REGNUM, &regs[ARM_PC_REGNUM]);