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| author | Thomas Preud'homme <thomas.preudhomme@arm.com> | 2018-01-15 14:11:02 +0000 |
|---|---|---|
| committer | Thomas Preud'homme <thomas.preudhomme@arm.com> | 2018-01-15 14:11:02 +0000 |
| commit | 2875ce2b55bdda40107ef3500edfeccfb29f14e6 (patch) | |
| tree | ae0b35dfd39a8605accf6b3d0bcf2e11e7aed654 /gas | |
| parent | df9909b8675c8c9b6fa88c5d13afd2efa66dcf68 (diff) | |
| download | gdb-2875ce2b55bdda40107ef3500edfeccfb29f14e6.zip gdb-2875ce2b55bdda40107ef3500edfeccfb29f14e6.tar.gz gdb-2875ce2b55bdda40107ef3500edfeccfb29f14e6.tar.bz2 | |
[ARM] Enable conditional Armv8-M instructions
Newly introduced instructions common to ARMv8-M Baseline and Mainline
are currently all marked as unconditional. However, all instructions but
sg (ie. blxns, bxns, tt, ttt, tta, ttat, vlldm and vlstm) do actually
support conditional execution. This patch fixes the definition of these
instructions accordingly.
2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm
and vlstm conditionally executable and reindent parameters.
* testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of
aforementionned instructions.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/config/tc-arm.c | 18 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/archv8m-cmse-main.s | 13 |
3 files changed, 27 insertions, 11 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 391912c..53a7e06 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,12 @@ 2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com> + * config/tc-arm.c (insns): Make blxns, bxns, tt, ttt, tta, ttat, vlldm + and vlstm conditionally executable and reindent parameters. + * testsuite/gas/arm/archv8m-cmse-main.s: Add conditional version of + aforementionned instructions. + +2018-01-15 Thomas Preud'homme <thomas.preudhomme@arm.com> + * config/tc-arm.c (it_fsm_post_encode): Do not warn if targeting M profile architecture or if in autodetection mode. Clarify that deprecation is for performance reason and concerns Armv8-A and Armv8-R. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index c07362a..925d994 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -21456,20 +21456,20 @@ static const struct asm_opcode insns[] = #define ARM_VARIANT NULL #undef THUMB_VARIANT #define THUMB_VARIANT & arm_ext_v8m - TUE("sg", 0, e97fe97f, 0, (), 0, noargs), - TUE("blxns", 0, 4784, 1, (RRnpc), 0, t_blx), - TUE("bxns", 0, 4704, 1, (RRnpc), 0, t_bx), - TUE("tt", 0, e840f000, 2, (RRnpc, RRnpc), 0, tt), - TUE("ttt", 0, e840f040, 2, (RRnpc, RRnpc), 0, tt), - TUE("tta", 0, e840f080, 2, (RRnpc, RRnpc), 0, tt), - TUE("ttat", 0, e840f0c0, 2, (RRnpc, RRnpc), 0, tt), + TUE("sg", 0, e97fe97f, 0, (), 0, noargs), + TCE("blxns", 0, 4784, 1, (RRnpc), 0, t_blx), + TCE("bxns", 0, 4704, 1, (RRnpc), 0, t_bx), + TCE("tt", 0, e840f000, 2, (RRnpc, RRnpc), 0, tt), + TCE("ttt", 0, e840f040, 2, (RRnpc, RRnpc), 0, tt), + TCE("tta", 0, e840f080, 2, (RRnpc, RRnpc), 0, tt), + TCE("ttat", 0, e840f0c0, 2, (RRnpc, RRnpc), 0, tt), /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the instructions behave as nop if no VFP is present. */ #undef THUMB_VARIANT #define THUMB_VARIANT & arm_ext_v8m_main - TUEc("vlldm", 0, ec300a00, 1, (RRnpc), rn), - TUEc("vlstm", 0, ec200a00, 1, (RRnpc), rn), + TCE("vlldm", 0, ec300a00, 1, (RRnpc), 0, rn), + TCE("vlstm", 0, ec200a00, 1, (RRnpc), 0, rn), }; #undef ARM_VARIANT #undef THUMB_VARIANT diff --git a/gas/testsuite/gas/arm/archv8m-cmse-main.s b/gas/testsuite/gas/arm/archv8m-cmse-main.s index 871414f..4f7ff5d 100644 --- a/gas/testsuite/gas/arm/archv8m-cmse-main.s +++ b/gas/testsuite/gas/arm/archv8m-cmse-main.s @@ -2,5 +2,14 @@ .syntax unified T: -vlldm r1 -vlstm r2 +vlldm r1 +vlstm r2 +it ne +blxnsne r4 +it ne +bxnsne r4 +itttt ne +ttane r0, r1 +ttane r8, r9 +ttatne r0, r1 +ttatne r8, r9 |