aarch64: [SME] SVE2 instructions added to support SME

This patch is adding new SVE2 instructions added to support SME extension.
The following SVE2 instructions are added by the SME architecture:
* PSEL,
* REVD, SCLAMP and UCLAMP.

gas/ChangeLog:

	* config/tc-aarch64.c (parse_sme_pred_reg_with_index):
	New parser.
	(parse_operands): New parser.
	* testsuite/gas/aarch64/sme-9-illegal.d: New test.
	* testsuite/gas/aarch64/sme-9-illegal.l: New test.
	* testsuite/gas/aarch64/sme-9-illegal.s: New test.
	* testsuite/gas/aarch64/sme-9.d: New test.
	* testsuite/gas/aarch64/sme-9.s: New test.

include/ChangeLog:

	* opcode/aarch64.h (enum aarch64_opnd): New operand
	AARCH64_OPND_SME_PnT_Wm_imm.

opcodes/ChangeLog:

	* aarch64-asm.c (aarch64_ins_sme_pred_reg_with_index):
	New inserter.
	* aarch64-dis.c (aarch64_ext_sme_pred_reg_with_index):
	New extractor.
	* aarch64-opc.c (aarch64_print_operand): Printout of
	OPND_SME_PnT_Wm_imm.
	* aarch64-opc.h (enum aarch64_field_kind): New bitfields
	FLD_SME_Rm, FLD_SME_i1, FLD_SME_tszh, FLD_SME_tszl.
	* aarch64-tbl.h (OP_SVE_NN_BHSD): New qualifier.
	(OP_SVE_QMQ): New qualifier.
	(struct aarch64_opcode): New instructions PSEL, REVD,
	SCLAMP and UCLAMP.
	aarch64-asm-2.c: Regenerate.
	aarch64-dis-2.c: Regenerate.
	aarch64-opc-2.c: Regenerate.

6 files changed, 348 insertions, 0 deletions

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 24cfabf..9fc61f7 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4655,6 +4655,65 @@ parse_sme_sm_za (char **str)
   return TOLOWER (p[0]);
 }
 
+/* Parse the name of the source scalable predicate register, the index base
+   register W12-W15 and the element index. Function performs element index
+   limit checks as well as qualifier type checks.
+
+   <Pn>.<T>[<Wv>, <imm>]
+   <Pn>.<T>[<Wv>, #<imm>]
+
+   On success function sets <Wv> to INDEX_BASE_REG, <T> to QUALIFIER and
+   <imm> to IMM.
+   Function returns <Pn>, or PARSE_FAIL.
+*/
+static int
+parse_sme_pred_reg_with_index(char **str,
+                              int *index_base_reg,
+                              int *imm,
+                              aarch64_opnd_qualifier_t *qualifier)
+{
+  int regno;
+  int64_t imm_limit;
+  int64_t imm_value;
+  const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_PN, qualifier);
+
+  if (reg == NULL)
+    return PARSE_FAIL;
+  regno = reg->number;
+
+  switch (*qualifier)
+    {
+    case AARCH64_OPND_QLF_S_B:
+      imm_limit = 15;
+      break;
+    case AARCH64_OPND_QLF_S_H:
+      imm_limit = 7;
+      break;
+    case AARCH64_OPND_QLF_S_S:
+      imm_limit = 3;
+      break;
+    case AARCH64_OPND_QLF_S_D:
+      imm_limit = 1;
+      break;
+    default:
+      set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d"));
+      return PARSE_FAIL;
+    }
+
+  if (! parse_sme_za_hv_tiles_operand_index (str, index_base_reg, &imm_value))
+    return PARSE_FAIL;
+
+  if (imm_value < 0 || imm_value > imm_limit)
+    {
+      set_syntax_error (_("element index out of range for given variant"));
+      return PARSE_FAIL;
+    }
+
+  *imm = imm_value;
+
+  return regno;
+}
+
 /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
    Returns the encoding for the option, or PARSE_FAIL.
 
@@ -7068,6 +7127,25 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	  info->reg.regno = val;
 	  break;
 
+	case AARCH64_OPND_SME_PnT_Wm_imm:
+	  /* <Pn>.<T>[<Wm>, #<imm>]  */
+	  {
+	    int index_base_reg;
+	    int imm;
+	    val = parse_sme_pred_reg_with_index (&str,
+	                                         &index_base_reg,
+	                                         &imm,
+	                                         &qualifier);
+	    if (val == PARSE_FAIL)
+	        goto failure;
+
+	    info->za_tile_vector.regno = val;
+	    info->za_tile_vector.index.regno = index_base_reg;
+	    info->za_tile_vector.index.imm = imm;
+	    info->qualifier = qualifier;
+	    break;
+	  }
+
 	case AARCH64_OPND_SVE_ADDR_RI_S4x16:
 	case AARCH64_OPND_SVE_ADDR_RI_S4x32:
 	case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.d b/gas/testsuite/gas/aarch64/sme-9-illegal.d
new file mode 100644
index 0000000..65ed0d3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-9-illegal.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sme-9-illegal.s
+#error_output: sme-9-illegal.l
diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.l b/gas/testsuite/gas/aarch64/sme-9-illegal.l
new file mode 100644
index 0000000..6bab29f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-9-illegal.l
@@ -0,0 +1,83 @@
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: wrong predicate register element size, allowed b, h, s and d at operand 3 -- `psel p1,p15,p3.q\[w15\]'
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p1,p15,p3.b\[w11\]'
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p8,p11,p15.h\[w16\]'
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p2,p7,p15.s\[w3\]'
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p13,p3,p1.d\[w17\]'
+[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p5,p12,p9.b\[w15,#16\]'
+[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p1,p8,p6.h\[w14,#8\]'
+[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p8,p4,p15.s\[w13,#4\]'
+[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p1,p1,p1.d\[w12,#2\]'
+[^:]*:[0-9]+: Error: operand mismatch -- `revd z0.q,p0/m,z0.b'
+[^:]*:[0-9]+: Info:    did you mean this\?
+[^:]*:[0-9]+: Info:    	revd z0.q, p0/m, z0.q
+[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z8.b,z1.b,z31.q'
+[^:]*:[0-9]+: Info:    did you mean this\?
+[^:]*:[0-9]+: Info:    	sclamp z8.b, z1.b, z31.b
+[^:]*:[0-9]+: Info:    other valid variant\(s\):
+[^:]*:[0-9]+: Info:    	sclamp z8.h, z1.h, z31.h
+[^:]*:[0-9]+: Info:    	sclamp z8.s, z1.s, z31.s
+[^:]*:[0-9]+: Info:    	sclamp z8.d, z1.d, z31.d
+[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z31.h,z0.h,z17.q'
+[^:]*:[0-9]+: Info:    did you mean this\?
+[^:]*:[0-9]+: Info:    	sclamp z31.h, z0.h, z17.h
+[^:]*:[0-9]+: Info:    other valid variant\(s\):
+[^:]*:[0-9]+: Info:    	sclamp z31.b, z0.b, z17.b
+[^:]*:[0-9]+: Info:    	sclamp z31.s, z0.s, z17.s
+[^:]*:[0-9]+: Info:    	sclamp z31.d, z0.d, z17.d
+[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z0.s,z31.s,z17.q'
+[^:]*:[0-9]+: Info:    did you mean this\?
+[^:]*:[0-9]+: Info:    	sclamp z0.s, z31.s, z17.s
+[^:]*:[0-9]+: Info:    other valid variant\(s\):
+[^:]*:[0-9]+: Info:    	sclamp z0.b, z31.b, z17.b
+[^:]*:[0-9]+: Info:    	sclamp z0.h, z31.h, z17.h
+[^:]*:[0-9]+: Info:    	sclamp z0.d, z31.d, z17.d
+[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z31.d,z0.d,z17.q'
+[^:]*:[0-9]+: Info:    did you mean this\?
+[^:]*:[0-9]+: Info:    	sclamp z31.d, z0.d, z17.d
+[^:]*:[0-9]+: Info:    other valid variant\(s\):
+[^:]*:[0-9]+: Info:    	sclamp z31.b, z0.b, z17.b
+[^:]*:[0-9]+: Info:    	sclamp z31.h, z0.h, z17.h
+[^:]*:[0-9]+: Info:    	sclamp z31.s, z0.s, z17.s
+[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z31.q,z0.d,z17.q'
+[^:]*:[0-9]+: Info:    did you mean this\?
+[^:]*:[0-9]+: Info:    	sclamp z31.d, z0.d, z17.d
+[^:]*:[0-9]+: Info:    other valid variant\(s\):
+[^:]*:[0-9]+: Info:    	sclamp z31.b, z0.b, z17.b
+[^:]*:[0-9]+: Info:    	sclamp z31.h, z0.h, z17.h
+[^:]*:[0-9]+: Info:    	sclamp z31.s, z0.s, z17.s
+[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z8.b,z1.b,z31.q'
+[^:]*:[0-9]+: Info:    did you mean this\?
+[^:]*:[0-9]+: Info:    	uclamp z8.b, z1.b, z31.b
+[^:]*:[0-9]+: Info:    other valid variant\(s\):
+[^:]*:[0-9]+: Info:    	uclamp z8.h, z1.h, z31.h
+[^:]*:[0-9]+: Info:    	uclamp z8.s, z1.s, z31.s
+[^:]*:[0-9]+: Info:    	uclamp z8.d, z1.d, z31.d
+[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z31.h,z0.h,z17.q'
+[^:]*:[0-9]+: Info:    did you mean this\?
+[^:]*:[0-9]+: Info:    	uclamp z31.h, z0.h, z17.h
+[^:]*:[0-9]+: Info:    other valid variant\(s\):
+[^:]*:[0-9]+: Info:    	uclamp z31.b, z0.b, z17.b
+[^:]*:[0-9]+: Info:    	uclamp z31.s, z0.s, z17.s
+[^:]*:[0-9]+: Info:    	uclamp z31.d, z0.d, z17.d
+[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z0.s,z31.s,z17.q'
+[^:]*:[0-9]+: Info:    did you mean this\?
+[^:]*:[0-9]+: Info:    	uclamp z0.s, z31.s, z17.s
+[^:]*:[0-9]+: Info:    other valid variant\(s\):
+[^:]*:[0-9]+: Info:    	uclamp z0.b, z31.b, z17.b
+[^:]*:[0-9]+: Info:    	uclamp z0.h, z31.h, z17.h
+[^:]*:[0-9]+: Info:    	uclamp z0.d, z31.d, z17.d
+[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z31.d,z0.d,z17.q'
+[^:]*:[0-9]+: Info:    did you mean this\?
+[^:]*:[0-9]+: Info:    	uclamp z31.d, z0.d, z17.d
+[^:]*:[0-9]+: Info:    other valid variant\(s\):
+[^:]*:[0-9]+: Info:    	uclamp z31.b, z0.b, z17.b
+[^:]*:[0-9]+: Info:    	uclamp z31.h, z0.h, z17.h
+[^:]*:[0-9]+: Info:    	uclamp z31.s, z0.s, z17.s
+[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z31.q,z0.d,z17.q'
+[^:]*:[0-9]+: Info:    did you mean this\?
+[^:]*:[0-9]+: Info:    	uclamp z31.d, z0.d, z17.d
+[^:]*:[0-9]+: Info:    other valid variant\(s\):
+[^:]*:[0-9]+: Info:    	uclamp z31.b, z0.b, z17.b
+[^:]*:[0-9]+: Info:    	uclamp z31.h, z0.h, z17.h
+[^:]*:[0-9]+: Info:    	uclamp z31.s, z0.s, z17.s
diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.s b/gas/testsuite/gas/aarch64/sme-9-illegal.s
new file mode 100644
index 0000000..308d52c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-9-illegal.s
@@ -0,0 +1,25 @@
+/* Scalable Matrix Extension (SME).  */
+
+psel p1, p15, p3.q[w15]
+psel p1, p15, p3.b[w11]
+psel p8, p11, p15.h[w16]
+psel p2, p7, p15.s[w3]
+psel p13, p3, p1.d[w17]
+psel p5, p12, p9.b[w15, #16]
+psel p1, p8, p6.h[w14, #8]
+psel p8, p4, p15.s[w13, #4]
+psel p1, p1, p1.d[w12, #2]
+
+revd z0.q, p0/m, z0.b
+
+sclamp z8.b, z1.b, z31.q
+sclamp z31.h, z0.h, z17.q
+sclamp z0.s, z31.s, z17.q
+sclamp z31.d, z0.d, z17.q
+sclamp z31.q, z0.d, z17.q
+
+uclamp z8.b, z1.b, z31.q
+uclamp z31.h, z0.h, z17.q
+uclamp z0.s, z31.s, z17.q
+uclamp z31.d, z0.d, z17.q
+uclamp z31.q, z0.d, z17.q
diff --git a/gas/testsuite/gas/aarch64/sme-9.d b/gas/testsuite/gas/aarch64/sme-9.d
new file mode 100644
index 0000000..ef314c6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-9.d
@@ -0,0 +1,73 @@
+#name: SVE2 instructions added to support SME
+#as: -march=armv8-a+sme
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+   0:	25277c61 	psel	p1, p15, p3.b\[w15, 0\]
+   4:	252778a2 	psel	p2, p14, p5.b\[w15, 0\]
+   8:	257f74e3 	psel	p3, p13, p7.b\[w15, 7\]
+   c:	25ff7125 	psel	p5, p12, p9.b\[w15, 15\]
+  10:	252a6de8 	psel	p8, p11, p15.h\[w14, 0\]
+  14:	252a682d 	psel	p13, p10, p1.h\[w14, 0\]
+  18:	257a640f 	psel	p15, p9, p0.h\[w14, 3\]
+  1c:	25fa60c1 	psel	p1, p8, p6.h\[w14, 7\]
+  20:	25315de2 	psel	p2, p7, p15.s\[w13, 0\]
+  24:	253159e3 	psel	p3, p6, p15.s\[w13, 0\]
+  28:	257155e5 	psel	p5, p5, p15.s\[w13, 1\]
+  2c:	25f151e8 	psel	p8, p4, p15.s\[w13, 3\]
+  30:	25604c2d 	psel	p13, p3, p1.d\[w12, 0\]
+  34:	2560482f 	psel	p15, p2, p1.d\[w12, 0\]
+  38:	25e04421 	psel	p1, p1, p1.d\[w12, 1\]
+  3c:	052e8000 	revd	z0.q, p0/m, z0.q
+  40:	052e9c00 	revd	z0.q, p7/m, z0.q
+  44:	052e83e0 	revd	z0.q, p0/m, z31.q
+  48:	052e9c1f 	revd	z31.q, p7/m, z0.q
+  4c:	4411c3e0 	sclamp	z0.b, z31.b, z17.b
+  50:	4411c01f 	sclamp	z31.b, z0.b, z17.b
+  54:	441fc028 	sclamp	z8.b, z1.b, z31.b
+  58:	4451c01f 	sclamp	z31.h, z0.h, z17.h
+  5c:	445fc028 	sclamp	z8.h, z1.h, z31.h
+  60:	4491c3e0 	sclamp	z0.s, z31.s, z17.s
+  64:	4491c01f 	sclamp	z31.s, z0.s, z17.s
+  68:	449fc028 	sclamp	z8.s, z1.s, z31.s
+  6c:	44d1c3e0 	sclamp	z0.d, z31.d, z17.d
+  70:	44d1c01f 	sclamp	z31.d, z0.d, z17.d
+  74:	44dfc028 	sclamp	z8.d, z1.d, z31.d
+  78:	4411c7e0 	uclamp	z0.b, z31.b, z17.b
+  7c:	4411c41f 	uclamp	z31.b, z0.b, z17.b
+  80:	441fc428 	uclamp	z8.b, z1.b, z31.b
+  84:	4451c7e0 	uclamp	z0.h, z31.h, z17.h
+  88:	4451c41f 	uclamp	z31.h, z0.h, z17.h
+  8c:	445fc428 	uclamp	z8.h, z1.h, z31.h
+  90:	4491c7e0 	uclamp	z0.s, z31.s, z17.s
+  94:	4491c41f 	uclamp	z31.s, z0.s, z17.s
+  98:	449fc428 	uclamp	z8.s, z1.s, z31.s
+  9c:	44d1c7e0 	uclamp	z0.d, z31.d, z17.d
+  a0:	44d1c41f 	uclamp	z31.d, z0.d, z17.d
+  a4:	44dfc428 	uclamp	z8.d, z1.d, z31.d
+  a8:	0420bca3 	movprfx	z3, z5
+  ac:	052e84a3 	revd	z3.q, p1/m, z5.q
+  b0:	0420bc81 	movprfx	z1, z4
+  b4:	052e84a1 	revd	z1.q, p1/m, z5.q
+  b8:	0420bc81 	movprfx	z1, z4
+  bc:	440bc141 	sclamp	z1.b, z10.b, z11.b
+  c0:	0420bc82 	movprfx	z2, z4
+  c4:	444bc142 	sclamp	z2.h, z10.h, z11.h
+  c8:	0420bc83 	movprfx	z3, z4
+  cc:	448bc143 	sclamp	z3.s, z10.s, z11.s
+  d0:	0420bca4 	movprfx	z4, z5
+  d4:	44cbc144 	sclamp	z4.d, z10.d, z11.d
+  d8:	0420bc81 	movprfx	z1, z4
+  dc:	440bc541 	uclamp	z1.b, z10.b, z11.b
+  e0:	0420bc82 	movprfx	z2, z4
+  e4:	444bc542 	uclamp	z2.h, z10.h, z11.h
+  e8:	0420bc83 	movprfx	z3, z4
+  ec:	448bc543 	uclamp	z3.s, z10.s, z11.s
+  f0:	0420bca4 	movprfx	z4, z5
+  f4:	44cbc544 	uclamp	z4.d, z10.d, z11.d
+  f8:	25277c61 	psel	p1, p15, p3.b\[w15, 0\]
+  fc:	252778a2 	psel	p2, p14, p5.b\[w15, 0\]
diff --git a/gas/testsuite/gas/aarch64/sme-9.s b/gas/testsuite/gas/aarch64/sme-9.s
new file mode 100644
index 0000000..be8511f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-9.s
@@ -0,0 +1,86 @@
+/* SVE2 instructions added to support SME.  */
+
+psel p1, p15, p3.b[w15, 0]
+psel p2, p14, p5.b[w15, 0]
+psel p3, p13, p7.b[w15, 7]
+psel p5, p12, p9.b[w15, 15]
+
+psel p8, p11, p15.h[w14, 0]
+psel p13, p10, p1.h[w14, 0]
+psel p15, p9, p0.h[w14, 3]
+psel p1, p8, p6.h[w14, 7]
+
+psel p2, p7, p15.s[w13, 0]
+psel p3, p6, p15.s[w13, 0]
+psel p5, p5, p15.s[w13, 1]
+psel p8, p4, p15.s[w13, 3]
+
+psel p13, p3, p1.d[w12, 0]
+psel p15, p2, p1.d[w12, 0]
+psel p1, p1, p1.d[w12, 1]
+
+revd z0.q, p0/m, z0.q
+revd z0.q, p7/m, z0.q
+revd z0.q, p0/m, z31.q
+revd z31.q, p7/m, z0.q
+
+sclamp z0.b, z31.b, z17.b
+sclamp z31.b, z0.b, z17.b
+sclamp z8.b, z1.b, z31.b
+sclamp z31.h, z0.h, z17.h
+sclamp z8.h, z1.h, z31.h
+sclamp z0.s, z31.s, z17.s
+sclamp z31.s, z0.s, z17.s
+sclamp z8.s, z1.s, z31.s
+sclamp z0.d, z31.d, z17.d
+sclamp z31.d, z0.d, z17.d
+sclamp z8.d, z1.d, z31.d
+
+uclamp z0.b, z31.b, z17.b
+uclamp z31.b, z0.b, z17.b
+uclamp z8.b, z1.b, z31.b
+uclamp z0.h, z31.h, z17.h
+uclamp z31.h, z0.h, z17.h
+uclamp z8.h, z1.h, z31.h
+uclamp z0.s, z31.s, z17.s
+uclamp z31.s, z0.s, z17.s
+uclamp z8.s, z1.s, z31.s
+uclamp z0.d, z31.d, z17.d
+uclamp z31.d, z0.d, z17.d
+uclamp z8.d, z1.d, z31.d
+
+/* The unpredicated MOVPRFX instruction.  */
+movprfx z3, z5
+revd z3.q, p1/m, z5.q
+
+movprfx z1, z4
+revd z1.q, p1/m, z5.q
+
+movprfx z1, z4
+sclamp z1.b, z10.b, z11.b
+
+movprfx z2, z4
+sclamp z2.h, z10.h, z11.h
+
+movprfx z3, z4
+sclamp z3.s, z10.s, z11.s
+
+movprfx z4, z5
+sclamp z4.d, z10.d, z11.d
+
+movprfx z1, z4
+uclamp z1.b, z10.b, z11.b
+
+movprfx z2, z4
+uclamp z2.h, z10.h, z11.h
+
+movprfx z3, z4
+uclamp z3.s, z10.s, z11.s
+
+movprfx z4, z5
+uclamp z4.d, z10.d, z11.d
+
+foo .req p1
+bar .req w15
+psel foo, p15, p3.b[w15, 0]
+psel p2, p14, p5.b[bar, 0]