aarch64: Add CSR PDEC instruction

This patch adds:
+ New feature +csre to -march command line.
+ New instruction CSR PDEC associated with CSRE feature.

Please note that CSRE system registers were already upstreamed. This patch
should finalize CSRE feature implementation.

CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of
a Call stack record) instruction. Although this instruction has operand
(PDEC) it's instruction's only operand. PDEC forces instruction field Rt
to be set to 0b1111. This results in fixed opcode of the instruction.

gas/ChangeLog:

2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* NEWS: Update docs.
	* config/tc-aarch64.c (parse_csr_operand): New operand parser.
	(parse_operands): Call to CSR operand parser.
	* testsuite/gas/aarch64/csre_csr-invalid.d: New test.
	* testsuite/gas/aarch64/csre_csr-invalid.l: New test.
	* testsuite/gas/aarch64/csre_csr-invalid.s: New test.
	* testsuite/gas/aarch64/csre_csr.d: New test.
	* testsuite/gas/aarch64/csre_csr.s: New test.

include/ChangeLog:

2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature.
	(enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR.

opcodes/ChangeLog:

2020-10-27  Przemyslaw Wirkus  <przemyslaw.wirkus@arm.com>

	* aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
	* aarch64-tbl.h (CSRE): New CSRE feature handler.
	(_CSRE_INSN): New CSRE instruction type.
	(struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

7 files changed, 57 insertions, 0 deletions

diff --git a/gas/NEWS b/gas/NEWS
index 88ad1d8..41cc668 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -24,6 +24,9 @@
 * Add support for DSB memory nXS barrier and WFET instruction for Armv8.7
   AArch64.
 
+* Add support for +csre feature for -march. Add CSR PDEC instruction for CSRE
+  feature.
+
 * Add support for Intel TDX instructions.
 
 * Add support for Intel Key Locker instructions.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 2ec1af4..a8ee74a 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4036,6 +4036,29 @@ parse_barrier_psb (char **str,
   return 0;
 }
 
+/* Parse an operand for CSR (CSRE instruction).  */
+
+static int
+parse_csr_operand (char **str)
+{
+  char *p, *q;
+
+  p = q = *str;
+  while (ISALPHA (*q))
+    q++;
+
+  /* Instruction has only one operand PDEC which encodes Rt field of the
+     operation to 0b11111.  */
+  if (strcasecmp(p, "pdec"))
+  {
+    set_syntax_error (_("CSR instruction accepts only PDEC"));
+    return PARSE_FAIL;
+  }
+
+  *str = q;
+  return 0;
+}
+
 /* Parse an operand for BTI.  Set *HINT_OPT to the hint-option record
    return 0 if successful.  Otherwise return PARSE_FAIL.  */
 
@@ -6749,6 +6772,12 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	    goto failure;
 	  break;
 
+	case AARCH64_OPND_CSRE_CSR:
+	  val = parse_csr_operand (&str);
+	  if (val == PARSE_FAIL)
+	    goto failure;
+	  break;
+
 	default:
 	  as_fatal (_("unhandled operand code %d"), operands[i]);
 	}
@@ -9171,6 +9200,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
   {"f64mm",		AARCH64_FEATURE (AARCH64_FEATURE_F64MM, 0),
 			AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
+  {"csre",		AARCH64_FEATURE (AARCH64_FEATURE_CSRE, 0),
+			AARCH64_ARCH_NONE},
   {NULL,		AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
 };
 
diff --git a/gas/testsuite/gas/aarch64/csre_csr-invalid.d b/gas/testsuite/gas/aarch64/csre_csr-invalid.d
new file mode 100644
index 0000000..bec71c8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/csre_csr-invalid.d
@@ -0,0 +1,3 @@
+#name: CSR PDEC instruction
+#source: csre_csr-invalid.s
+#error_output: csre_csr-invalid.l
diff --git a/gas/testsuite/gas/aarch64/csre_csr-invalid.l b/gas/testsuite/gas/aarch64/csre_csr-invalid.l
new file mode 100644
index 0000000..dec38ab
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/csre_csr-invalid.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: selected processor does not support `csr pdec'
diff --git a/gas/testsuite/gas/aarch64/csre_csr-invalid.s b/gas/testsuite/gas/aarch64/csre_csr-invalid.s
new file mode 100644
index 0000000..e8520ba
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/csre_csr-invalid.s
@@ -0,0 +1,4 @@
+/* CSR PDEC requires +csre for -march= command line option.   */
+.arch armv8-a
+
+    csr pdec
diff --git a/gas/testsuite/gas/aarch64/csre_csr.d b/gas/testsuite/gas/aarch64/csre_csr.d
new file mode 100644
index 0000000..c242f0a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/csre_csr.d
@@ -0,0 +1,10 @@
+#name: CSRE extension CSR PDEC instruction
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d50b721f 	csr	pdec
+.*:	d50b721f 	csr	pdec
diff --git a/gas/testsuite/gas/aarch64/csre_csr.s b/gas/testsuite/gas/aarch64/csre_csr.s
new file mode 100644
index 0000000..d0ac90f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/csre_csr.s
@@ -0,0 +1,4 @@
+.arch armv8-a+csre
+
+    csr pdec
+    CSR PDEC