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| author | Jin Ma <jinma@linux.alibaba.com> | 2023-12-25 16:49:21 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-12-29 08:55:30 +0800 |
| commit | 77d242a06e352eee88908326d7bbf3b77086d5db (patch) | |
| tree | f4b2b3738ae45273be8f53ee4ec815116842932e /gas | |
| parent | 0e2ec3dbce8a3948277e7b02ece0d926ac8a4253 (diff) | |
| download | gdb-77d242a06e352eee88908326d7bbf3b77086d5db.zip gdb-77d242a06e352eee88908326d7bbf3b77086d5db.tar.gz gdb-77d242a06e352eee88908326d7bbf3b77086d5db.tar.bz2 | |
RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extension
In order to make it easier to complete the compiler's support for
the XTheadVector extension and to be as compatible as possible
with the programming model of the 'V' extension ([1]), we consider
adding a few pseudo instructions ([2]).
th.vmmv.m vd,vs => th.vmand.mm vd,vs,vs
th.vneg.v vd,vs => th.vrsub.vx vd,vs,x0
th.vncvt.x.x.v vd,vs,vm => th.vnsrl.vx vd,vs,x0,vm
th.vfneg.v vd,vs => th.vfsgnjn.vv vd,vs,vs
th.vfabs.v vd,vs => th.vfsgnjx.vv vd,vs,vs
Ref:
[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641302.html
[2] https://github.com/T-head-Semi/thead-extension-spec/pull/40
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for new
pseudoinstructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
opcodes/ChangeLog:
* riscv-opc.c: Add new pseudoinstructions.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-vector.d | 9 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-vector.s | 15 |
2 files changed, 24 insertions, 0 deletions
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d index 014c2fd..441bd0e6 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -982,6 +982,8 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+e3057207[ ]+th.vlseg8eff.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+e3057207[ ]+th.vlseg8eff.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+e1057207[ ]+th.vlseg8eff.v[ ]+v4,\(a0\),v0.t +[ ]+[0-9a-f]+:[ ]+0e804257[ ]+th.vneg.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+0c804257[ ]+th.vneg.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+02860257[ ]+th.vadd.vv[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+0285c257[ ]+th.vadd.vx[ ]+v4,v8,a1 [ ]+[0-9a-f]+:[ ]+0287b257[ ]+th.vadd.vi[ ]+v4,v8,15 @@ -1098,6 +1100,8 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+a485c257[ ]+th.vsra.vx[ ]+v4,v8,a1,v0.t [ ]+[0-9a-f]+:[ ]+a480b257[ ]+th.vsra.vi[ ]+v4,v8,1,v0.t [ ]+[0-9a-f]+:[ ]+a48fb257[ ]+th.vsra.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+b2804257[ ]+th.vncvt.x.x.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+b0804257[ ]+th.vncvt.x.x.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+b2860257[ ]+th.vnsrl.vv[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+b285c257[ ]+th.vnsrl.vx[ ]+v4,v8,a1 [ ]+[0-9a-f]+:[ ]+b280b257[ ]+th.vnsrl.vi[ ]+v4,v8,1 @@ -1488,6 +1492,10 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+10865257[ ]+th.vfmin.vf[ ]+v4,v8,fa2,v0.t [ ]+[0-9a-f]+:[ ]+18861257[ ]+th.vfmax.vv[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+18865257[ ]+th.vfmax.vf[ ]+v4,v8,fa2,v0.t +[ ]+[0-9a-f]+:[ ]+26841257[ ]+th.vfneg.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+24841257[ ]+th.vfneg.v[ ]+v4,v8,v0.t +[ ]+[0-9a-f]+:[ ]+2a841257[ ]+th.vfabs.v[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+28841257[ ]+th.vfabs.v[ ]+v4,v8,v0.t [ ]+[0-9a-f]+:[ ]+22861257[ ]+th.vfsgnj.vv[ ]+v4,v8,v12 [ ]+[0-9a-f]+:[ ]+22865257[ ]+th.vfsgnj.vf[ ]+v4,v8,fa2 [ ]+[0-9a-f]+:[ ]+26861257[ ]+th.vfsgnjn.vv[ ]+v4,v8,v12 @@ -1593,6 +1601,7 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+cc861257[ ]+th.vfwredosum.vs[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+c4861257[ ]+th.vfwredsum.vs[ ]+v4,v8,v12,v0.t [ ]+[0-9a-f]+:[ ]+66842257[ ]+th.vmcpy.m[ ]+v4,v8 +[ ]+[0-9a-f]+:[ ]+66842257[ ]+th.vmcpy.m[ ]+v4,v8 [ ]+[0-9a-f]+:[ ]+6e422257[ ]+th.vmclr.m[ ]+v4 [ ]+[0-9a-f]+:[ ]+7e422257[ ]+th.vmset.m[ ]+v4 [ ]+[0-9a-f]+:[ ]+76842257[ ]+th.vmnot.m[ ]+v4,v8 diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index 3a4dea3..413f4a8 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -1006,6 +1006,10 @@ th.vlseg8eff.v v4, 0(a0) th.vlseg8eff.v v4, (a0), v0.t + # Aliases + th.vneg.v v4, v8 + th.vneg.v v4, v8, v0.t + th.vadd.vv v4, v8, v12 th.vadd.vx v4, v8, a1 th.vadd.vi v4, v8, 15 @@ -1131,6 +1135,10 @@ th.vsra.vi v4, v8, 1, v0.t th.vsra.vi v4, v8, 31, v0.t + # Aliases + th.vncvt.x.x.v v4, v8 + th.vncvt.x.x.v v4, v8, v0.t + th.vnsrl.vv v4, v8, v12 th.vnsrl.vx v4, v8, a1 th.vnsrl.vi v4, v8, 1 @@ -1539,6 +1547,12 @@ th.vfmax.vv v4, v8, v12, v0.t th.vfmax.vf v4, v8, fa2, v0.t + # Aliases + th.vfneg.v v4, v8 + th.vfneg.v v4, v8, v0.t + th.vfabs.v v4, v8 + th.vfabs.v v4, v8, v0.t + th.vfsgnj.vv v4, v8, v12 th.vfsgnj.vf v4, v8, fa2 th.vfsgnjn.vv v4, v8, v12 @@ -1658,6 +1672,7 @@ th.vfwredsum.vs v4, v8, v12, v0.t # Aliases + th.vmmv.m v4, v8 th.vmcpy.m v4, v8 th.vmclr.m v4 th.vmset.m v4 |