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| author | Palmer Dabbelt <palmer@dabbelt.com> | 2017-11-06 13:22:42 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2017-11-07 09:00:37 -0800 |
| commit | 1270b047fdc68d89f05668ed919d17f5fceeba2a (patch) | |
| tree | a8164ba6096eb6012fb6cc642f4aacd5a579049a /gas | |
| parent | a02b41a7e604471e584dc2151fbd36714842710e (diff) | |
| download | gdb-1270b047fdc68d89f05668ed919d17f5fceeba2a.zip gdb-1270b047fdc68d89f05668ed919d17f5fceeba2a.tar.gz gdb-1270b047fdc68d89f05668ed919d17f5fceeba2a.tar.bz2 | |
RISC-V: Add satp as an alias for sptbr
The RISC-V privileged ISA changed the name of sptbr (Supervisor Page
Table Base Register) to satp (Supervisor Address Translation and
Protection) to reflect the fact it could be used for more than just
paging. This patch adds an alias, as they're the same register.
include/ChangeLog
2017-11-06 Palmer Dabbelt <palmer@dabbelt.com>
* opcode/riscv-opc.h (sptbr): Rename to satp.
(CSR_SPTBR): Rename to CSR_SATP.
(sptbr): Alias to CSR_SATP.
gas/ChangeLog
2017-11-06 Palmer Dabbelt <palmer@dabbelt.com>
* testsuite/gas/riscv/satp.d: New test.
testsuite/gas/riscv/satp.s: Likewise.
testsuite/gas/riscv/riscv.exp: Likewise.
config/tc-riscv.c (md_begin): Handle CSR aliases.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/config/tc-riscv.c | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/riscv.exp | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/satp.d | 11 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/satp.s | 3 |
5 files changed, 23 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 6c84820..85f0664 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2017-11-07 Palmer Dabbelt <palmer@dabbelt.com> + + * testsuite/gas/riscv/satp.d: New test. + testsuite/gas/riscv/satp.s: Likewise. + testsuite/gas/riscv/riscv.exp: Likewise. + config/tc-riscv.c (md_begin): Handle CSR aliases. + 2017-11-07 Tamar Christina <tamar.christina@arm.com> * config/tc-arm.c (arm_cpus): diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index f4276c9..c8955a6 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -643,6 +643,7 @@ md_begin (void) hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR); #define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num); +#define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num); #include "opcode/riscv-opc.h" #undef DECLARE_CSR diff --git a/gas/testsuite/gas/riscv/riscv.exp b/gas/testsuite/gas/riscv/riscv.exp index b2eaec1..2ab885a 100644 --- a/gas/testsuite/gas/riscv/riscv.exp +++ b/gas/testsuite/gas/riscv/riscv.exp @@ -24,4 +24,5 @@ if [istarget riscv*-*-*] { run_dump_test "c-lui-fail" run_dump_test "c-addi4spn-fail" run_dump_test "c-addi16sp-fail" + run_dump_test "satp" } diff --git a/gas/testsuite/gas/riscv/satp.d b/gas/testsuite/gas/riscv/satp.d new file mode 100644 index 0000000..823601c --- /dev/null +++ b/gas/testsuite/gas/riscv/satp.d @@ -0,0 +1,11 @@ +#as: +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <target>: +[ ]+0:[ ]+180022f3[ ]+csrr[ ]+t0,satp +[ ]+4:[ ]+180022f3[ ]+csrr[ ]+t0,satp diff --git a/gas/testsuite/gas/riscv/satp.s b/gas/testsuite/gas/riscv/satp.s new file mode 100644 index 0000000..f8aa766 --- /dev/null +++ b/gas/testsuite/gas/riscv/satp.s @@ -0,0 +1,3 @@ +target: + csrr t0, satp + csrr t0, sptbr |