[AArch64][PATCH 3/3] Add floating-point FP16 instructions

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the ARMv8 FP support. This patch adds the new FP16 instructions,
making them available when the architecture extension +fp+fp16 is
specified.

The instructions added are:

- Comparisons and conditionals: FCMP, FCCMPE, FCMP, FCMPE and FCSEL.
- Arithmetic: FABS, FNEG, FSQRT, FMUL, FDIV, FADD, FSUB, FMADD, FMSUB,
  FNMADD and FNMSUB.
- Rounding: FRINTN, FRINTP, FRINTM, FRINTZ, FRINTA, FRINTX and FRINTI.
- Conversions: SCVTF (fixed-point), SCVTF (integer), UCVTF (fixed-point)
  UCVTF (integer), FCVTZS (fixed-point), FCVTZS (integer), FCVTZU
  (fixed-point), FCVTZU (integer), FCVTNS, FCVTNU, FCVTAS, FCVTAU,
  FCVTPS, FCVTPU, FCVTMS and  FCVTMU.
- Scalar FMOV: immediate, general and register

gas/testsuite/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/float-fp16.d: New.
	* gas/aarch64/float-fp16.s: New.

opcodes/
2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
	(QL_INT2FP_H, QL_FP2INT_H): New.
	(QL_FP2_H, QL_FP3_H, QL_FP4_H): New
	(QL_DST_H): New.
	(QL_FCCMP_H): New.
	(aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
	fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
	fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
	fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
	frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
	fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
	fcsel.

Change-Id: Ie6d40bd1b215a9bc024e12ba75e52afbe1675eb7

3 files changed, 328 insertions, 0 deletions

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 1f1b863..e73a977 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,10 @@
 2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
 
+	* gas/aarch64/float-fp16.d: New.
+	* gas/aarch64/float-fp16.s: New.
+
+2015-11-27  Matthew Wahab  <matthew.wahab@arm.com>
+
 	* gas/aarch64/alias-2.d: Add tests for REV.
 	* gas/aarch64/alias-2.s: Likewise.
 
diff --git a/gas/testsuite/gas/aarch64/float-fp16.d b/gas/testsuite/gas/aarch64/float-fp16.d
new file mode 100644
index 0000000..dc87981
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/float-fp16.d
@@ -0,0 +1,172 @@
+#as: -march=armv8.2-a+fp16
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+   [0-9a-f]+:	1e200400 	fccmp	s0, s0, #0x0, eq
+   [0-9a-f]+:	1ee00400 	fccmp	h0, h0, #0x0, eq
+   [0-9a-f]+:	1e22d420 	fccmp	s1, s2, #0x0, le
+   [0-9a-f]+:	1ee2d420 	fccmp	h1, h2, #0x0, le
+  [0-9a-f]+:	1e200410 	fccmpe	s0, s0, #0x0, eq
+  [0-9a-f]+:	1ee00410 	fccmpe	h0, h0, #0x0, eq
+  [0-9a-f]+:	1e22d430 	fccmpe	s1, s2, #0x0, le
+  [0-9a-f]+:	1ee2d430 	fccmpe	h1, h2, #0x0, le
+  [0-9a-f]+:	1e202000 	fcmp	s0, s0
+  [0-9a-f]+:	1ee02000 	fcmp	h0, h0
+  [0-9a-f]+:	1e222020 	fcmp	s1, s2
+  [0-9a-f]+:	1ee22020 	fcmp	h1, h2
+  [0-9a-f]+:	1e202010 	fcmpe	s0, s0
+  [0-9a-f]+:	1ee02010 	fcmpe	h0, h0
+  [0-9a-f]+:	1e222030 	fcmpe	s1, s2
+  [0-9a-f]+:	1ee22030 	fcmpe	h1, h2
+  [0-9a-f]+:	1e202008 	fcmp	s0, #0\.0
+  [0-9a-f]+:	1ee02008 	fcmp	h0, #0\.0
+  [0-9a-f]+:	1e202018 	fcmpe	s0, #0\.0
+  [0-9a-f]+:	1ee02018 	fcmpe	h0, #0\.0
+  [0-9a-f]+:	1e210c00 	fcsel	s0, s0, s1, eq
+  [0-9a-f]+:	1ee10c00 	fcsel	h0, h0, h1, eq
+  [0-9a-f]+:	9ee60000 	fmov	x0, h0
+  [0-9a-f]+:	1ee60000 	fmov	w0, h0
+  [0-9a-f]+:	9ee70001 	fmov	h1, x0
+  [0-9a-f]+:	1ee70001 	fmov	h1, w0
+  [0-9a-f]+:	1ee0c020 	fabs	h0, h1
+  [0-9a-f]+:	1e20c020 	fabs	s0, s1
+  [0-9a-f]+:	1e60c020 	fabs	d0, d1
+  [0-9a-f]+:	1ee14020 	fneg	h0, h1
+  [0-9a-f]+:	1e214020 	fneg	s0, s1
+  [0-9a-f]+:	1e614020 	fneg	d0, d1
+  [0-9a-f]+:	1ee1c020 	fsqrt	h0, h1
+  [0-9a-f]+:	1e21c020 	fsqrt	s0, s1
+  [0-9a-f]+:	1e61c020 	fsqrt	d0, d1
+  [0-9a-f]+:	1ee44020 	frintn	h0, h1
+  [0-9a-f]+:	1e244020 	frintn	s0, s1
+  [0-9a-f]+:	1e644020 	frintn	d0, d1
+  [0-9a-f]+:	1ee4c020 	frintp	h0, h1
+  [0-9a-f]+:	1e24c020 	frintp	s0, s1
+  [0-9a-f]+:	1e64c020 	frintp	d0, d1
+  [0-9a-f]+:	1ee54020 	frintm	h0, h1
+  [0-9a-f]+:	1e254020 	frintm	s0, s1
+  [0-9a-f]+:	1e654020 	frintm	d0, d1
+  [0-9a-f]+:	1ee5c020 	frintz	h0, h1
+  [0-9a-f]+:	1e25c020 	frintz	s0, s1
+  [0-9a-f]+:	1e65c020 	frintz	d0, d1
+  [0-9a-f]+:	1ee64020 	frinta	h0, h1
+  [0-9a-f]+:	1e264020 	frinta	s0, s1
+  [0-9a-f]+:	1e664020 	frinta	d0, d1
+  [0-9a-f]+:	1ee74020 	frintx	h0, h1
+  [0-9a-f]+:	1e274020 	frintx	s0, s1
+  [0-9a-f]+:	1e674020 	frintx	d0, d1
+  [0-9a-f]+:	1ee7c020 	frinti	h0, h1
+  [0-9a-f]+:	1e27c020 	frinti	s0, s1
+  [0-9a-f]+:	1e67c020 	frinti	d0, d1
+  [0-9a-f]+:	1ee20820 	fmul	h0, h1, h2
+  [0-9a-f]+:	1e220820 	fmul	s0, s1, s2
+  [0-9a-f]+:	1e620820 	fmul	d0, d1, d2
+  [0-9a-f]+:	1ee21820 	fdiv	h0, h1, h2
+  [0-9a-f]+:	1e221820 	fdiv	s0, s1, s2
+  [0-9a-f]+:	1e621820 	fdiv	d0, d1, d2
+  [0-9a-f]+:	1ee22820 	fadd	h0, h1, h2
+  [0-9a-f]+:	1e222820 	fadd	s0, s1, s2
+ [0-9a-f]+:	1e622820 	fadd	d0, d1, d2
+ [0-9a-f]+:	1ee23820 	fsub	h0, h1, h2
+ [0-9a-f]+:	1e223820 	fsub	s0, s1, s2
+ [0-9a-f]+:	1e623820 	fsub	d0, d1, d2
+ [0-9a-f]+:	1ee24820 	fmax	h0, h1, h2
+ [0-9a-f]+:	1e224820 	fmax	s0, s1, s2
+ [0-9a-f]+:	1e624820 	fmax	d0, d1, d2
+ [0-9a-f]+:	1ee25820 	fmin	h0, h1, h2
+ [0-9a-f]+:	1e225820 	fmin	s0, s1, s2
+ [0-9a-f]+:	1e625820 	fmin	d0, d1, d2
+ [0-9a-f]+:	1ee26820 	fmaxnm	h0, h1, h2
+ [0-9a-f]+:	1e226820 	fmaxnm	s0, s1, s2
+ [0-9a-f]+:	1e626820 	fmaxnm	d0, d1, d2
+ [0-9a-f]+:	1ee27820 	fminnm	h0, h1, h2
+ [0-9a-f]+:	1e227820 	fminnm	s0, s1, s2
+ [0-9a-f]+:	1e627820 	fminnm	d0, d1, d2
+ [0-9a-f]+:	1ee28820 	fnmul	h0, h1, h2
+ [0-9a-f]+:	1e228820 	fnmul	s0, s1, s2
+ [0-9a-f]+:	1e628820 	fnmul	d0, d1, d2
+ [0-9a-f]+:	1fc20c20 	fmadd	h0, h1, h2, h3
+ [0-9a-f]+:	1f020c20 	fmadd	s0, s1, s2, s3
+ [0-9a-f]+:	1f420c20 	fmadd	d0, d1, d2, d3
+ [0-9a-f]+:	1fc28c20 	fmsub	h0, h1, h2, h3
+ [0-9a-f]+:	1f028c20 	fmsub	s0, s1, s2, s3
+ [0-9a-f]+:	1f428c20 	fmsub	d0, d1, d2, d3
+ [0-9a-f]+:	1fe20c20 	fnmadd	h0, h1, h2, h3
+ [0-9a-f]+:	1f220c20 	fnmadd	s0, s1, s2, s3
+ [0-9a-f]+:	1f620c20 	fnmadd	d0, d1, d2, d3
+ [0-9a-f]+:	1fe28c20 	fnmsub	h0, h1, h2, h3
+ [0-9a-f]+:	1f228c20 	fnmsub	s0, s1, s2, s3
+ [0-9a-f]+:	1f628c20 	fnmsub	d0, d1, d2, d3
+ [0-9a-f]+:	1e2e1000 	fmov	s0, #1\.000000000000000000e\+00
+ [0-9a-f]+:	1eee1000 	fmov	h0, #1\.000000000000000000e\+00
+ [0-9a-f]+:	1e02f820 	scvtf	s0, w1, #2
+ [0-9a-f]+:	9e02f420 	scvtf	s0, x1, #3
+ [0-9a-f]+:	1ec2f820 	scvtf	h0, w1, #2
+ [0-9a-f]+:	9ec2f420 	scvtf	h0, x1, #3
+ [0-9a-f]+:	1e03f820 	ucvtf	s0, w1, #2
+ [0-9a-f]+:	9e03f420 	ucvtf	s0, x1, #3
+ [0-9a-f]+:	1ec3f820 	ucvtf	h0, w1, #2
+ [0-9a-f]+:	9ec3f420 	ucvtf	h0, x1, #3
+ [0-9a-f]+:	1e58f801 	fcvtzs	w1, d0, #2
+ [0-9a-f]+:	9e58f401 	fcvtzs	x1, d0, #3
+ [0-9a-f]+:	1ed8f801 	fcvtzs	w1, h0, #2
+ [0-9a-f]+:	9ed8f401 	fcvtzs	x1, h0, #3
+ [0-9a-f]+:	1e59f801 	fcvtzu	w1, d0, #2
+ [0-9a-f]+:	9e59f401 	fcvtzu	x1, d0, #3
+ [0-9a-f]+:	1ed9f801 	fcvtzu	w1, h0, #2
+ [0-9a-f]+:	9ed9f401 	fcvtzu	x1, h0, #3
+ [0-9a-f]+:	1e200001 	fcvtns	w1, s0
+ [0-9a-f]+:	9e600001 	fcvtns	x1, d0
+ [0-9a-f]+:	1ee00001 	fcvtns	w1, h0
+ [0-9a-f]+:	9ee00001 	fcvtns	x1, h0
+ [0-9a-f]+:	1e210001 	fcvtnu	w1, s0
+ [0-9a-f]+:	9e610001 	fcvtnu	x1, d0
+ [0-9a-f]+:	1ee10001 	fcvtnu	w1, h0
+ [0-9a-f]+:	9ee10001 	fcvtnu	x1, h0
+ [0-9a-f]+:	1e250001 	fcvtau	w1, s0
+ [0-9a-f]+:	9e650001 	fcvtau	x1, d0
+ [0-9a-f]+:	1ee50001 	fcvtau	w1, h0
+ [0-9a-f]+:	9ee50001 	fcvtau	x1, h0
+ [0-9a-f]+:	1e240001 	fcvtas	w1, s0
+ [0-9a-f]+:	9e640001 	fcvtas	x1, d0
+ [0-9a-f]+:	1ee40001 	fcvtas	w1, h0
+ [0-9a-f]+:	9ee40001 	fcvtas	x1, h0
+ [0-9a-f]+:	1e280001 	fcvtps	w1, s0
+ [0-9a-f]+:	9e680001 	fcvtps	x1, d0
+ [0-9a-f]+:	1ee80001 	fcvtps	w1, h0
+ [0-9a-f]+:	9ee80001 	fcvtps	x1, h0
+ [0-9a-f]+:	1e290001 	fcvtpu	w1, s0
+ [0-9a-f]+:	9e690001 	fcvtpu	x1, d0
+ [0-9a-f]+:	1ee90001 	fcvtpu	w1, h0
+ [0-9a-f]+:	9ee90001 	fcvtpu	x1, h0
+ [0-9a-f]+:	1e300001 	fcvtms	w1, s0
+ [0-9a-f]+:	9e700001 	fcvtms	x1, d0
+ [0-9a-f]+:	1ef00001 	fcvtms	w1, h0
+ [0-9a-f]+:	9ef00001 	fcvtms	x1, h0
+ [0-9a-f]+:	1e310001 	fcvtmu	w1, s0
+ [0-9a-f]+:	9e710001 	fcvtmu	x1, d0
+ [0-9a-f]+:	1ef10001 	fcvtmu	w1, h0
+ [0-9a-f]+:	9ef10001 	fcvtmu	x1, h0
+ [0-9a-f]+:	1e220020 	scvtf	s0, w1
+ [0-9a-f]+:	9e620020 	scvtf	d0, x1
+ [0-9a-f]+:	1ee20020 	scvtf	h0, w1
+ [0-9a-f]+:	9ee20020 	scvtf	h0, x1
+ [0-9a-f]+:	1e230020 	ucvtf	s0, w1
+ [0-9a-f]+:	9e630020 	ucvtf	d0, x1
+ [0-9a-f]+:	1ee30020 	ucvtf	h0, w1
+ [0-9a-f]+:	9ee30020 	ucvtf	h0, x1
+ [0-9a-f]+:	1e604020 	fmov	d0, d1
+ [0-9a-f]+:	1e204020 	fmov	s0, s1
+ [0-9a-f]+:	1ee04020 	fmov	h0, h1
+ [0-9a-f]+:	9ee60020 	fmov	x0, h1
+ [0-9a-f]+:	1ee60020 	fmov	w0, h1
+ [0-9a-f]+:	9ee70001 	fmov	h1, x0
+ [0-9a-f]+:	1ee70001 	fmov	h1, w0
+ [0-9a-f]+:	1e260020 	fmov	w0, s1
+ [0-9a-f]+:	9e660020 	fmov	x0, d1
+ [0-9a-f]+:	1e270001 	fmov	s1, w0
+ [0-9a-f]+:	9e670001 	fmov	d1, x0
diff --git a/gas/testsuite/gas/aarch64/float-fp16.s b/gas/testsuite/gas/aarch64/float-fp16.s
new file mode 100644
index 0000000..0c30038
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/float-fp16.s
@@ -0,0 +1,151 @@
+/* Test file for AArch64 half-precision floating-point instructions.  */
+
+	.text
+	fccmp s0, s0, #0, eq
+	fccmp h0, h0, #0, eq
+	fccmp s1, s2, #0, le
+	fccmp h1, h2, #0, le
+
+	fccmpe s0, s0, #0, eq
+	fccmpe h0, h0, #0, eq
+	fccmpe s1, s2, #0, le
+	fccmpe h1, h2, #0, le
+
+	fcmp s0, s0
+	fcmp h0, h0
+	fcmp s1, s2
+	fcmp h1, h2
+
+	fcmpe s0, s0
+	fcmpe h0, h0
+	fcmpe s1, s2
+	fcmpe h1, h2
+
+	fcmp s0, #0.0
+	fcmp h0, #0.0
+
+	fcmpe s0, #0.0
+	fcmpe h0, #0.0
+
+	fcsel s0, s0, s1, eq
+	fcsel h0, h0, h1, eq
+
+	fmov x0, h0
+	fmov w0, h0
+	fmov h1, x0
+	fmov h1, w0
+
+	/* Scalar data-processing with one source.  */
+	.macro sdp1src op
+	\op     h0, h1
+	\op     s0, s1
+	\op     d0, d1
+	.endm
+
+	.text
+	.irp op, fabs, fneg, fsqrt, frintn, frintp, frintm, frintz
+	sdp1src \op
+	.endr
+
+	.irp op, frinta, frintx, frinti
+	sdp1src \op
+	.endr
+
+	/* Scalar data-processing with two sources.  */
+	.macro sdp2src op
+	\op     h0, h1, h2
+	\op     s0, s1, s2
+	\op     d0, d1, d2
+	.endm
+
+	.text
+	.irp op, fmul, fdiv, fadd, fsub, fmax, fmin, fmaxnm, fminnm, fnmul
+	sdp2src \op
+	.endr
+
+	/* Scalar data-processing with three sources.  */
+	.macro sdp3src op
+	\op     h0, h1, h2, h3
+	\op     s0, s1, s2, s3
+	\op     d0, d1, d2, d3
+	.endm
+
+	.text
+	.irp op, fmadd, fmsub, fnmadd, fnmsub
+	sdp3src \op
+	.endr
+
+	/* Scalar conversion.  */
+
+	.macro scvt_fix2fp op
+	\op     s0, w1, #2
+	\op     s0, x1, #3
+	\op     h0, w1, #2
+	\op     h0, x1, #3
+	.endm
+
+	.macro scvt_fp2fix op
+	\op     w1, d0, #2
+	\op     x1, d0, #3
+	\op     w1, h0, #2
+	\op     x1, h0, #3
+	.endm
+
+	.text
+
+	fmov s0, #1.0
+	fmov h0, #1.0
+
+	.irp op, scvtf, ucvtf
+	scvt_fix2fp \op
+	.endr
+
+	.irp op, fcvtzs, fcvtzu
+	scvt_fp2fix \op
+	.endr
+
+	.macro scvt_fp2int op
+	\op w1, s0
+	\op x1, d0
+	\op w1, h0
+	\op x1, h0
+	.endm
+
+	.macro scvt_int2fp op
+	\op s0, w1
+	\op d0, x1
+	\op h0, w1
+	\op h0, x1
+	.endm
+
+	.text
+	.irp op, fcvtns, fcvtnu, fcvtau, fcvtas
+	scvt_fp2int \op
+	.endr
+
+	.text
+	.irp op, fcvtps, fcvtpu, fcvtms, fcvtmu
+	scvt_fp2int \op
+	.endr
+
+	.irp op, scvtf, ucvtf
+	scvt_int2fp \op
+	.endr
+
+	/* FMOV.  */
+
+	fmov d0, d1
+	fmov s0, s1
+	fmov h0, h1
+
+	fmov x0, h1
+	fmov w0, h1
+
+	fmov h1, x0
+	fmov h1, w0
+
+	fmov w0, s1
+	fmov x0, d1
+
+	fmov s1, w0
+	fmov d1, x0