Support Intel PREFETCHI

gas/ChangeLog:

	* NEWS: Add support for Intel PREFETCHI instruction.
	* config/tc-i386.c (load_insn_p): Use prefetch* to fold all prefetches.
	(md_assemble): Add warning for illegal input of PREFETCHI.
	* doc/c-i386.texi: Document .prefetchi.
	* testsuite/gas/i386/i386.exp: Run PREFETCHI tests.
	* testsuite/gas/i386/x86-64-lfence-load.d: Add PREFETCHI.
	* testsuite/gas/i386/x86-64-lfence-load.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetch.d: New test.
	* testsuite/gas/i386/x86-64-prefetchi-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise..
	* testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-warn.l: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-warn.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi.d: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi.s: Likewise.

opcodes/ChangeLog:

	* i386-dis.c (reg_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7
	(x86_64_table): Add X86_64_0F18_REG_6_MOD_0 and X86_64_0F18_REG_7_MOD_0.
	(mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7.
	(prefix_table): Add PREFIX_0F18_REG_6_MOD_0_X86_64 and
	PREFIX_0F18_REG_7_MOD_0_X86_64.
	(PREFETCHI_Fixup): New.
	* i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS.
	(cpu_flags): Add CpuPREFETCHI.
	* i386-opc.h (CpuPREFETCHI): New.
	(i386_cpu_flags): Add cpuprefetchi.
	* i386-opc.tbl: Add Intel PREFETCHI instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

13 files changed, 103 insertions, 3 deletions

diff --git a/gas/NEWS b/gas/NEWS
index b676b67..dd8f857 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for Intel PREFETCHI instructions.
+
 * Add support for Intel AMX-FP16 instructions.
 
 * gas now supports --compress-debug-sections=zstd to compress
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index df83d4b..fb1ce75 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1095,6 +1095,7 @@ static const arch_entry cpu_arch[] =
   SUBARCH (uintr, UINTR, ANY_UINTR, false),
   SUBARCH (hreset, HRESET, ANY_HRESET, false),
   SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false),
+  SUBARCH (prefetchi, PREFETCHI, PREFETCHI, false),
 };
 
 #undef SUBARCH
@@ -4496,9 +4497,8 @@ load_insn_p (void)
 
   if (!any_vex_p)
     {
-      /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
-	 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
-	 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote.  */
+      /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
+	 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote.  */
       if (i.tm.opcode_modifier.anysize)
 	return 0;
 
@@ -5033,6 +5033,11 @@ md_assemble (char *line)
   if (!process_suffix ())
     return;
 
+  /* Check if IP-relative addressing requirements can be satisfied.  */
+  if (i.tm.cpu_flags.bitfield.cpuprefetchi
+      && !(i.base_reg && i.base_reg->reg_num == RegIP))
+    as_warn (_("only support RIP-relative address"), i.tm.name);
+
   /* Update operand types and check extended states.  */
   for (j = 0; j < i.operands; j++)
     {
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 9d2ccdd..55a587b 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -194,6 +194,7 @@ accept various extension mnemonics.  For example,
 @code{avx512_bf16},
 @code{avx_vnni},
 @code{avx512_fp16},
+@code{prefetchi},
 @code{amx_int8},
 @code{amx_bf16},
 @code{amx_fp16},
@@ -1487,6 +1488,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
 @item @samp{.tdx} @tab @samp{.avx_vnni}  @tab @samp{.avx512_fp16}
 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
+@item @samp{.prefetchi}
 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 185229d..1b0bacb 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -1177,6 +1177,10 @@ if [gas_64_check] then {
     run_dump_test "x86-64-tdx"
     run_dump_test "x86-64-tsxldtrk"
     run_dump_test "x86-64-hreset"
+    run_dump_test "x86-64-prefetchi"
+    run_dump_test "x86-64-prefetchi-intel"
+    run_dump_test "x86-64-prefetchi-inval-register"
+    run_list_test "x86-64-prefetchi-warn"
     run_dump_test "x86-64-vp2intersect"
     run_dump_test "x86-64-vp2intersect-intel"
     run_list_test "x86-64-vp2intersect-inval-bcast"
diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.d b/gas/testsuite/gas/i386/x86-64-lfence-load.d
index 2af86fc..17c3b9f 100644
--- a/gas/testsuite/gas/i386/x86-64-lfence-load.d
+++ b/gas/testsuite/gas/i386/x86-64-lfence-load.d
@@ -33,6 +33,8 @@ Disassembly of section .text:
  +[a-f0-9]+:	0f 18 55 00          	prefetcht1 0x0\(%rbp\)
  +[a-f0-9]+:	0f 18 5d 00          	prefetcht2 0x0\(%rbp\)
  +[a-f0-9]+:	0f 0d 4d 00          	prefetchw 0x0\(%rbp\)
+ +[a-f0-9]+:	0f 18 3d 78 56 34 12 	prefetchit0 0x12345678\(%rip\)        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+ +[a-f0-9]+:	0f 18 35 78 56 34 12 	prefetchit1 0x12345678\(%rip\)        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
  +[a-f0-9]+:	0f a1                	pop    %fs
  +[a-f0-9]+:	0f ae e8             	lfence
  +[a-f0-9]+:	9d                   	popf
diff --git a/gas/testsuite/gas/i386/x86-64-lfence-load.s b/gas/testsuite/gas/i386/x86-64-lfence-load.s
index 2a3ac6b..c478082 100644
--- a/gas/testsuite/gas/i386/x86-64-lfence-load.s
+++ b/gas/testsuite/gas/i386/x86-64-lfence-load.s
@@ -20,6 +20,8 @@ _start:
 	prefetcht1 (%rbp)
 	prefetcht2 (%rbp)
 	prefetchw (%rbp)
+	prefetchit0 0x12345678(%rip)
+	prefetchit1 0x12345678(%rip)
 	pop %fs
 	popf
 	xlatb (%rbx)
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d b/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
new file mode 100644
index 0000000..7f72f0a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
@@ -0,0 +1,16 @@
+#as:
+#objdump: -dwMintel
+#name: x86-64 PREFETCHI insns (Intel disassembly)
+#source: x86-64-prefetchi.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	0f 18 3d 78 56 34 12 	prefetchit0 BYTE PTR \[rip\+0x12345678\]        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ 	]*[a-f0-9]+:	0f 18 35 78 56 34 12 	prefetchit1 BYTE PTR \[rip\+0x12345678\]        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ 	]*[a-f0-9]+:	0f 18 3d 78 56 34 12 	prefetchit0 BYTE PTR \[rip\+0x12345678\]        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ 	]*[a-f0-9]+:	0f 18 35 78 56 34 12 	prefetchit1 BYTE PTR \[rip\+0x12345678\]        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
new file mode 100644
index 0000000..b29b1ae
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
@@ -0,0 +1,13 @@
+#as:
+#objdump: -dw
+#name: x86-64 PREFETCHI INVAL REGISTER insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <\.text>:
+[ 	]*[a-f0-9]+:[ 	]0f 18 39[ 	]*nopl   \(%rcx\)
+[ 	]*[a-f0-9]+:[ 	]0f 18 31[ 	]*nopl   \(%rcx\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
new file mode 100644
index 0000000..550449a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
@@ -0,0 +1,9 @@
+.text
+        #prefetchit0 (%rcx) PREFETCHIT0/1 apply without RIP-relative addressing, should stay NOPs.
+        .byte 0x0f
+        .byte 0x18
+        .byte 0x39
+        #prefetchit1 (%rcx) PREFETCHIT1/1 apply without RIP-relative addressing, should stay NOPs.
+        .byte 0x0f
+        .byte 0x18
+        .byte 0x31
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-warn.l b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.l
new file mode 100644
index 0000000..4e15389
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*:[0-9]*: Warning: only support RIP-relative address
+.*:[0-9]*: Warning: only support RIP-relative address
+.*:[0-9]*: Warning: only support RIP-relative address
+.*:[0-9]*: Warning: only support RIP-relative address
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi-warn.s b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.s
new file mode 100644
index 0000000..330ff31
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi-warn.s
@@ -0,0 +1,11 @@
+# Check error for ICACHE-PREFETCH 64-bit instruction
+
+	.allow_index_reg
+	.text
+_start:
+	prefetchit0     0x12345678(%rax)
+	prefetchit1     0x12345678(%rax)
+
+	.intel_syntax noprefix
+	prefetchit0     BYTE PTR [rax+0x12345678]
+	prefetchit1     BYTE PTR [rax+0x12345678]
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi.d b/gas/testsuite/gas/i386/x86-64-prefetchi.d
new file mode 100644
index 0000000..c8ab92d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi.d
@@ -0,0 +1,15 @@
+#as:
+#objdump: -dw
+#name: x86-64 PREFETCHI insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	0f 18 3d 78 56 34 12 	prefetchit0 0x12345678\(%rip\)        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ 	]*[a-f0-9]+:	0f 18 35 78 56 34 12 	prefetchit1 0x12345678\(%rip\)        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ 	]*[a-f0-9]+:	0f 18 3d 78 56 34 12 	prefetchit0 0x12345678\(%rip\)        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ 	]*[a-f0-9]+:	0f 18 35 78 56 34 12 	prefetchit1 0x12345678\(%rip\)        # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-prefetchi.s b/gas/testsuite/gas/i386/x86-64-prefetchi.s
new file mode 100644
index 0000000..cc7c61e
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetchi.s
@@ -0,0 +1,14 @@
+# Check 64bit PREFETCHI instructions
+
+	.allow_index_reg
+	.text
+_start:
+
+        prefetchit0     0x12345678(%rip)
+        prefetchit1     0x12345678(%rip)
+
+        .intel_syntax noprefix
+
+        prefetchit0     BYTE PTR [rip+0x12345678]
+        prefetchit1     BYTE PTR [rip+0x12345678]
+