aarch64: Add support for Check Feature Status Extension.

This patch adds support for Check Feature Status Extension (CHK) which
is mandatory from Armv8.0-A. Also this patch supports "chkfeat" instruction
(hint #40).

9 files changed, 67 insertions, 10 deletions

diff --git a/gas/NEWS b/gas/NEWS
index ca03cad..2b593c1 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for AArch64 Check Feature Status Extension (CHK).
+
 * Add support for 'armv8.9-a' and 'armv9.4-a' for -march in AArch64 GAS.
 
 * Add support for Intel USER_MSR instructions.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 7d7e549..f5b7b42 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6570,6 +6570,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	case AARCH64_OPND_Rm:
 	case AARCH64_OPND_Rt:
 	case AARCH64_OPND_Rt2:
+	case AARCH64_OPND_X16:
 	case AARCH64_OPND_Rs:
 	case AARCH64_OPND_Ra:
 	case AARCH64_OPND_Rt_LS64:
@@ -6581,17 +6582,26 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	  /* In LS64 load/store instructions Rt register number must be even
 	     and <=22.  */
 	  if (operands[i] == AARCH64_OPND_Rt_LS64)
-	  {
-	    /* We've already checked if this is valid register.
-	       This will check if register number (Rt) is not undefined for LS64
-	       instructions:
-	       if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED.  */
-	    if ((info->reg.regno & 0x18) == 0x18 || (info->reg.regno & 0x01) == 0x01)
 	    {
-	      set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
-	      goto failure;
+	      /* We've already checked if this is valid register.
+		This will check if register number (Rt) is not undefined for
+		LS64 instructions:
+		if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED.  */
+	      if ((info->reg.regno & 0x18) == 0x18
+		  || (info->reg.regno & 0x01) == 0x01)
+		{
+		  set_syntax_error
+		    (_("invalid Rt register number in 64-byte load/store"));
+		  goto failure;
+		}
+	    }
+	  else if (operands[i] == AARCH64_OPND_X16)
+	    {
+	      if (info->reg.regno != 16)
+		{
+		  goto failure;
+		}
 	    }
-	  }
 	  break;
 
 	case AARCH64_OPND_Rd_SP:
@@ -10314,6 +10324,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"mops",		AARCH64_FEATURE (MOPS), AARCH64_NO_FEATURES},
   {"hbc",		AARCH64_FEATURE (HBC), AARCH64_NO_FEATURES},
   {"cssc",		AARCH64_FEATURE (CSSC), AARCH64_NO_FEATURES},
+  {"chk",		AARCH64_FEATURE (CHK), AARCH64_NO_FEATURES},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 9b73fbf..0cabf72e 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -259,6 +259,8 @@ automatically cause those extensions to be disabled.
  @tab Enable SVE2 SM4 Extension.  This implies @code{sm4} and @code{sve2}.
 @item @code{tme} @tab ARMv8-A @tab No
  @tab Enable Transactional Memory Extensions.
+@item @code{chk} @tab ARMv8-A @tab ARMv8-A
+ @tab Enable Check Feature Status Extension.
 @end multitable
 
 @node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/chk-bad-1.d b/gas/testsuite/gas/aarch64/chk-bad-1.d
new file mode 100644
index 0000000..6389d05
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/chk-bad-1.d
@@ -0,0 +1,4 @@
+#name: Test of chkfeat extension operand
+#source: chk-bad-1.s
+#as: -march=armv8-a
+#error_output: chk-bad-1.l
diff --git a/gas/testsuite/gas/aarch64/chk-bad-1.l b/gas/testsuite/gas/aarch64/chk-bad-1.l
new file mode 100644
index 0000000..b7403c2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/chk-bad-1.l
@@ -0,0 +1,13 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `chkfeat'
+[^ :]+:[0-9]+: Error: operand 1 must be X16 -- `chkfeat x0'
+[^ :]+:[0-9]+: Error: operand 1 must be X16 -- `chkfeat x10'
+[^ :]+:[0-9]+: Error: operand 1 must be X16 -- `chkfeat x17'
+[^ :]+:[0-9]+: Error: operand 1 must be X16 -- `chkfeat x30'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `chkfeat x31'
+[^ :]+:[0-9]+: Error: operand mismatch -- `chkfeat w16'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	chkfeat x16
+[^ :]+:[0-9]+: Error: operand 1 must be X16 -- `chkfeat xzr'
+[^ :]+:[0-9]+: Error: operand 1 must be X16 -- `chkfeat wzr'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `chkfeat sp'
diff --git a/gas/testsuite/gas/aarch64/chk-bad-1.s b/gas/testsuite/gas/aarch64/chk-bad-1.s
new file mode 100644
index 0000000..5e75d58
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/chk-bad-1.s
@@ -0,0 +1,12 @@
+	.text
+	chkfeat
+	chkfeat x0
+	chkfeat x10
+	chkfeat x17
+	chkfeat x30
+	chkfeat x31
+	chkfeat x16
+	chkfeat w16
+	chkfeat xzr
+	chkfeat wzr
+	chkfeat sp
diff --git a/gas/testsuite/gas/aarch64/chk.d b/gas/testsuite/gas/aarch64/chk.d
new file mode 100644
index 0000000..6222eca
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/chk.d
@@ -0,0 +1,11 @@
+#name: Test of Check Feature Status Instruction.
+#as: -march=armv8-a
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*:	d503251f 	chkfeat	x16
diff --git a/gas/testsuite/gas/aarch64/chk.s b/gas/testsuite/gas/aarch64/chk.s
new file mode 100644
index 0000000..3d6dc53
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/chk.s
@@ -0,0 +1,2 @@
+	.text
+	chkfeat x16
diff --git a/gas/testsuite/gas/aarch64/system.d b/gas/testsuite/gas/aarch64/system.d
index 6de9aeb..8ad2746 100644
--- a/gas/testsuite/gas/aarch64/system.d
+++ b/gas/testsuite/gas/aarch64/system.d
@@ -55,7 +55,7 @@ Disassembly of section \.text:
 .*:	d50324bf 	hint	#0x25
 .*:	d50324df 	(hint	#0x26|bti	jc)
 .*:	d50324ff 	hint	#0x27
-.*:	d503251f 	hint	#0x28
+.*:	d503251f 	(hint	#0x28|chkfeat	x16)
 .*:	d503253f 	hint	#0x29
 .*:	d503255f 	hint	#0x2a
 .*:	d503257f 	hint	#0x2b