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| author | Neal Frager <neal.frager@amd.com> | 2023-10-19 12:37:40 +0100 |
|---|---|---|
| committer | Michael J. Eager <eager@eagercon.com> | 2023-10-19 17:59:06 -0700 |
| commit | 2d1777b530d7832db5d8d7017378354c28816554 (patch) | |
| tree | afb934c520d01495eef0b82641f0c7d47d089ed9 /gas | |
| parent | 4781e165dc9e8b8f3c0ba40825c620e88e6ae103 (diff) | |
| download | gdb-2d1777b530d7832db5d8d7017378354c28816554.zip gdb-2d1777b530d7832db5d8d7017378354c28816554.tar.gz gdb-2d1777b530d7832db5d8d7017378354c28816554.tar.bz2 | |
opcodes: microblaze: Fix bit masking bug
There is currently a bug in the bit masking for the barrel shift
instructions because the bit mask is not including all of the
register bits which must be zero. With this patch, the disassembler
can be sure that the 32-bit value is indeed a barrel shift instruction
and not a data value in memory.
This fix can be verified by assembling and disassembling the following:
.text
.long 0x65005f5f
With this patch, the bug is fixed, and the objdump will know that
0x65005f5f is not a barrel shift instruction.
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michael J. Eager <eager@eagercon.com>
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/testsuite/gas/microblaze/allinsn.d | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gas/testsuite/gas/microblaze/allinsn.d b/gas/testsuite/gas/microblaze/allinsn.d index 312e3fb..83175f1 100644 --- a/gas/testsuite/gas/microblaze/allinsn.d +++ b/gas/testsuite/gas/microblaze/allinsn.d @@ -49,7 +49,7 @@ Disassembly of section .text: 40: 900001e2 swaph r0, r0 00000044 <bsefi>: - 44: 64004041 bsrli r0, r0, 1 + 44: 64004041 bsefi r0, r0, 1, 1 00000048 <bsifi>: - 48: 64008041 bsrli r0, r0, 1 + 48: 64008041 bsifi r0, r0, 1, 1 |