diff options
author | Sebastian Pop <sebastian.pop@amd.com> | 2009-11-05 23:40:05 +0000 |
---|---|---|
committer | Sebastian Pop <sebastian.pop@amd.com> | 2009-11-05 23:40:05 +0000 |
commit | f88c9eb030684877952d1316567fdc461d69772a (patch) | |
tree | e7da5818868361faa92bcf0b99d702d2b0b967dd /gas | |
parent | d85a05f07f9f01c6b7e0e84491ca7972a621b85b (diff) | |
download | gdb-f88c9eb030684877952d1316567fdc461d69772a.zip gdb-f88c9eb030684877952d1316567fdc461d69772a.tar.gz gdb-f88c9eb030684877952d1316567fdc461d69772a.tar.bz2 |
2009-11-05 Sebastian Pop <sebastian.pop@amd.com>
Quentin Neill <quentin.neill@amd.com>
* gas/config/tc-i386.c (cpu_arch): Add CPU_LWP_FLAGS.
(build_vex_prefix): Handle xop09 and xop0a.
(build_modrm_byte): Handle vexlwp.
(md_show_usage): Add lwp.
* gas/doc/c-i386.texi (i386-LWP): New section.
* gas/testsuite/gas/i386/i386.exp: Run x86-64-lwp in 64-bit mode,
run lwp in 32-bit mode.
* gas/testsuite/gas/i386/x86-64-lwp.d: New.
* gas/testsuite/gas/i386/x86-64-lwp.s: New.
* gas/testsuite/gas/i386/lwp.d: New.
* gas/testsuite/gas/i386/lwp.s: New.
* opcodes/i386-dis.c (OP_LWPCB_E): New.
(OP_LWP_E): New.
(OP_LWP_I): New.
(USE_XOP_8F_TABLE): New.
(XOP_8F_TABLE): New.
(REG_XOP_LWPCB): New.
(REG_XOP_LWP): New.
(XOP_09): New.
(XOP_0A): New.
(reg_table): Redirect REG_8F to XOP_8F_TABLE.
Add entries for REG_XOP_LWPCB and REG_XOP_LWP.
(xop_table): New.
(get_valid_dis386): Handle USE_XOP_8F_TABLE.
Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values
to access to the vex_table.
(OP_LWPCB_E): New.
(OP_LWP_E): New.
(OP_LWP_I): New.
* opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP.
(cpu_flags): Add CpuLWP.
(opcode_modifiers): Add VexLWP, XOP09, and XOP0A.
* opcodes/i386-opc.h (CpuLWP): New.
(i386_cpu_flags): Add bit cpulwp.
(VexLWP): New.
(XOP09): New.
(XOP0A): New.
(i386_opcode_modifier): Add vexlwp, xop09, and xop0a.
* opcodes/i386-opc.tbl (llwpcb): Added.
(lwpval): Added.
(lwpins): Added.
Diffstat (limited to 'gas')
-rw-r--r-- | gas/ChangeLog | 9 | ||||
-rw-r--r-- | gas/config/tc-i386.c | 37 | ||||
-rw-r--r-- | gas/doc/c-i386.texi | 23 | ||||
-rw-r--r-- | gas/testsuite/ChangeLog | 10 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/i386.exp | 2 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/lwp.d | 137 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/lwp.s | 141 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-lwp.d | 201 | ||||
-rw-r--r-- | gas/testsuite/gas/i386/x86-64-lwp.s | 205 |
9 files changed, 758 insertions, 7 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 0efc8f2..02cfc37 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,12 @@ +2009-11-05 Sebastian Pop <sebastian.pop@amd.com> + Quentin Neill <quentin.neill@amd.com> + + * config/tc-i386.c (cpu_arch): Add CPU_LWP_FLAGS. + (build_vex_prefix): Handle xop09 and xop0a. + (build_modrm_byte): Handle vexlwp. + (md_show_usage): Add lwp. + * doc/c-i386.texi (i386-LWP): New section. + 2009-11-04 DJ Delorie <dj@redhat.com> * config/rx-parse.y (MVTIPL): Update bit pattern. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index ff6129c..2996751 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -641,6 +641,8 @@ static const arch_entry cpu_arch[] = CPU_FMA_FLAGS }, { ".fma4", PROCESSOR_UNKNOWN, CPU_FMA4_FLAGS }, + { ".lwp", PROCESSOR_UNKNOWN, + CPU_LWP_FLAGS }, { ".movbe", PROCESSOR_UNKNOWN, CPU_MOVBE_FLAGS }, { ".ept", PROCESSOR_UNKNOWN, @@ -2720,18 +2722,28 @@ build_vex_prefix (const insn_template *t) /* 3-byte VEX prefix. */ unsigned int m, w; + i.vex.length = 3; + i.vex.bytes[0] = 0xc4; + if (i.tm.opcode_modifier.vex0f) m = 0x1; else if (i.tm.opcode_modifier.vex0f38) m = 0x2; else if (i.tm.opcode_modifier.vex0f3a) m = 0x3; + else if (i.tm.opcode_modifier.xop09) + { + m = 0x9; + i.vex.bytes[0] = 0x8f; + } + else if (i.tm.opcode_modifier.xop0a) + { + m = 0xa; + i.vex.bytes[0] = 0x8f; + } else abort (); - i.vex.length = 3; - i.vex.bytes[0] = 0xc4; - /* The high 3 bits of the second VEX byte are 1's compliment of RXB bits from REX. */ i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; @@ -4936,7 +4948,8 @@ build_modrm_byte (void) a instruction with VEX prefix and 3 sources. */ if (i.mem_operands == 0 && ((i.reg_operands == 2 - && !i.tm.opcode_modifier.vexndd) + && !i.tm.opcode_modifier.vexndd + && !i.tm.opcode_modifier.vexlwp) || (i.reg_operands == 3 && i.tm.opcode_modifier.vexnds) || (i.reg_operands == 4 && vex_3_sources))) @@ -5252,11 +5265,22 @@ build_modrm_byte (void) else mem = ~0; + if (i.tm.opcode_modifier.vexlwp) + { + i.vex.register_specifier = i.op[2].regs; + if (!i.mem_operands) + { + i.rm.mode = 3; + i.rm.regmem = i.op[1].regs->reg_num; + if ((i.op[1].regs->reg_flags & RegRex) != 0) + i.rex |= REX_B; + } + } /* Fill in i.rm.reg or i.rm.regmem field with register operand (if any) based on i.tm.extension_opcode. Again, we must be careful to make sure that segment/control/debug/test/MMX registers are coded into the i.rm.reg field. */ - if (i.reg_operands) + else if (i.reg_operands) { unsigned int op; unsigned int vex_reg = ~0; @@ -5316,6 +5340,7 @@ build_modrm_byte (void) && !operand_type_equal (&i.tm.operand_types[vex_reg], ®ymm)) abort (); + i.vex.register_specifier = i.op[vex_reg].regs; } @@ -8019,7 +8044,7 @@ md_show_usage (stream) ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\ vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\ clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\ - svme, abm, padlock, fma4\n")); + svme, abm, padlock, fma4, lwp\n")); fprintf (stream, _("\ -mtune=CPU optimize for CPU, CPU is one of:\n\ i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\ diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 4110679..9dacf4c 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -32,6 +32,7 @@ extending the Intel architecture to 64-bits. * i386-Jumps:: Handling of Jump Instructions * i386-Float:: Floating Point * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations +* i386-LWP:: AMD's Lightweight Profiling Instructions * i386-16bit:: Writing 16-bit Code * i386-Arch:: Specifying an x86 CPU architecture * i386-Bugs:: AT&T Syntax bugs @@ -140,6 +141,7 @@ accept various extension mnemonics. For example, @code{movbe}, @code{ept}, @code{clflush}, +@code{lwp}, @code{syscall}, @code{rdtscp}, @code{3dnow}, @@ -799,6 +801,25 @@ as the floating point stack. See Intel and AMD documentation, keeping in mind that the operand order in instructions is reversed from the Intel syntax. +@node i386-LWP +@section AMD's Lightweight Profiling Instructions + +@cindex LWP, i386 +@cindex LWP, x86-64 + +@code{@value{AS}} supports AMD's Lightweight Profiling (LWP) +instruction set, available on AMD's Family 15h (Orochi) processors. + +LWP enables applications to collect and manage performance data, and +react to performance events. The collection of performance data +requires no context switches. LWP runs in the context of a thread and +so several counters can be used independently across multiple threads. +LWP can be used in both 64-bit and legacy 32-bit modes. + +For detailed information on the LWP instruction set, see the +@cite{AMD Lightweight Profiling Specification} available at +@uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}. + @node i386-16bit @section Writing 16-bit Code @@ -898,7 +919,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave} @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.movbe} -@item @samp{.ept} @tab @samp{.clflush} +@item @samp{.ept} @tab @samp{.clflush} @tab @samp{.lwp} @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} @item @samp{.padlock} diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 28045f9..4d398a4 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,13 @@ +2009-11-05 Sebastian Pop <sebastian.pop@amd.com> + Quentin Neill <quentin.neill@amd.com> + + * gas/i386/i386.exp: Run x86-64-lwp in 64-bit mode, + run lwp in 32-bit mode. + * gas/i386/x86-64-lwp.d: New. + * gas/i386/x86-64-lwp.s: New. + * gas/i386/lwp.d: New. + * gas/i386/lwp.s: New. + 2009-11-05 Nick Clifton <nickc@redhat.com> * gas/i386/i386.exp (space1): Move test inside check for x86 diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 15459c4..52b57b6 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -156,6 +156,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "fma" run_dump_test "fma-intel" run_dump_test "fma4" + run_dump_test "lwp" # These tests require support for 8 and 16 bit relocs, # so we only run them for ELF and COFF targets. @@ -324,6 +325,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t run_dump_test "x86-64-fma" run_dump_test "x86-64-fma-intel" run_dump_test "x86-64-fma4" + run_dump_test "x86-64-lwp" if { ![istarget "*-*-aix*"] && ![istarget "*-*-beos*"] diff --git a/gas/testsuite/gas/i386/lwp.d b/gas/testsuite/gas/i386/lwp.d new file mode 100644 index 0000000..417f626 --- /dev/null +++ b/gas/testsuite/gas/i386/lwp.d @@ -0,0 +1,137 @@ +#objdump: -dw +#name: x86-64 LWP + +.*: +file format .* + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: 8f e9 78 12 c0[ ]+llwpcb %ax +[ ]*[a-f0-9]+: 8f e9 78 12 c1[ ]+llwpcb %cx +[ ]*[a-f0-9]+: 8f e9 78 12 c2[ ]+llwpcb %dx +[ ]*[a-f0-9]+: 8f e9 78 12 c3[ ]+llwpcb %bx +[ ]*[a-f0-9]+: 8f e9 78 12 c4[ ]+llwpcb %sp +[ ]*[a-f0-9]+: 8f e9 78 12 c5[ ]+llwpcb %bp +[ ]*[a-f0-9]+: 8f e9 78 12 c6[ ]+llwpcb %si +[ ]*[a-f0-9]+: 8f e9 78 12 c7[ ]+llwpcb %di +[ ]*[a-f0-9]+: 8f e9 7c 12 c0[ ]+llwpcb %eax +[ ]*[a-f0-9]+: 8f e9 7c 12 c1[ ]+llwpcb %ecx +[ ]*[a-f0-9]+: 8f e9 7c 12 c2[ ]+llwpcb %edx +[ ]*[a-f0-9]+: 8f e9 7c 12 c3[ ]+llwpcb %ebx +[ ]*[a-f0-9]+: 8f e9 7c 12 c4[ ]+llwpcb %esp +[ ]*[a-f0-9]+: 8f e9 7c 12 c5[ ]+llwpcb %ebp +[ ]*[a-f0-9]+: 8f e9 7c 12 c6[ ]+llwpcb %esi +[ ]*[a-f0-9]+: 8f e9 7c 12 c7[ ]+llwpcb %edi +[ ]*[a-f0-9]+: 8f e9 7c 12 cf[ ]+slwpcb %edi +[ ]*[a-f0-9]+: 8f e9 7c 12 ce[ ]+slwpcb %esi +[ ]*[a-f0-9]+: 8f e9 7c 12 cd[ ]+slwpcb %ebp +[ ]*[a-f0-9]+: 8f e9 7c 12 cc[ ]+slwpcb %esp +[ ]*[a-f0-9]+: 8f e9 7c 12 cb[ ]+slwpcb %ebx +[ ]*[a-f0-9]+: 8f e9 7c 12 ca[ ]+slwpcb %edx +[ ]*[a-f0-9]+: 8f e9 7c 12 c9[ ]+slwpcb %ecx +[ ]*[a-f0-9]+: 8f e9 7c 12 c8[ ]+slwpcb %eax +[ ]*[a-f0-9]+: 8f e9 78 12 cf[ ]+slwpcb %di +[ ]*[a-f0-9]+: 8f e9 78 12 ce[ ]+slwpcb %si +[ ]*[a-f0-9]+: 8f e9 78 12 cd[ ]+slwpcb %bp +[ ]*[a-f0-9]+: 8f e9 78 12 cc[ ]+slwpcb %sp +[ ]*[a-f0-9]+: 8f e9 78 12 cb[ ]+slwpcb %bx +[ ]*[a-f0-9]+: 8f e9 78 12 ca[ ]+slwpcb %dx +[ ]*[a-f0-9]+: 8f e9 78 12 c9[ ]+slwpcb %cx +[ ]*[a-f0-9]+: 8f e9 78 12 c8[ ]+slwpcb %ax +[ ]*[a-f0-9]+: 8f ea 78 12 c0 34 12[ ]+lwpins \$0x1234,%eax,%ax +[ ]*[a-f0-9]+: 8f ea 70 12 c1 34 12[ ]+lwpins \$0x1234,%ecx,%cx +[ ]*[a-f0-9]+: 8f ea 68 12 c2 34 12[ ]+lwpins \$0x1234,%edx,%dx +[ ]*[a-f0-9]+: 8f ea 60 12 c3 34 12[ ]+lwpins \$0x1234,%ebx,%bx +[ ]*[a-f0-9]+: 8f ea 58 12 c4 34 12[ ]+lwpins \$0x1234,%esp,%sp +[ ]*[a-f0-9]+: 8f ea 50 12 c5 34 12[ ]+lwpins \$0x1234,%ebp,%bp +[ ]*[a-f0-9]+: 8f ea 48 12 c6 34 12[ ]+lwpins \$0x1234,%esi,%si +[ ]*[a-f0-9]+: 8f ea 40 12 c7 34 12[ ]+lwpins \$0x1234,%edi,%di +[ ]*[a-f0-9]+: 8f ea 7c 12 c7 78 56 34 12[ ]+lwpins \$0x12345678,%edi,%eax +[ ]*[a-f0-9]+: 8f ea 74 12 c6 78 56 34 12[ ]+lwpins \$0x12345678,%esi,%ecx +[ ]*[a-f0-9]+: 8f ea 6c 12 c5 78 56 34 12[ ]+lwpins \$0x12345678,%ebp,%edx +[ ]*[a-f0-9]+: 8f ea 64 12 c4 78 56 34 12[ ]+lwpins \$0x12345678,%esp,%ebx +[ ]*[a-f0-9]+: 8f ea 5c 12 c3 78 56 34 12[ ]+lwpins \$0x12345678,%ebx,%esp +[ ]*[a-f0-9]+: 8f ea 54 12 c2 78 56 34 12[ ]+lwpins \$0x12345678,%edx,%ebp +[ ]*[a-f0-9]+: 8f ea 4c 12 c1 78 56 34 12[ ]+lwpins \$0x12345678,%ecx,%esi +[ ]*[a-f0-9]+: 8f ea 44 12 c0 78 56 34 12[ ]+lwpins \$0x12345678,%eax,%edi +[ ]*[a-f0-9]+: 8f ea 78 12 c8 34 12[ ]+lwpval \$0x1234,%eax,%ax +[ ]*[a-f0-9]+: 8f ea 70 12 c9 34 12[ ]+lwpval \$0x1234,%ecx,%cx +[ ]*[a-f0-9]+: 8f ea 68 12 ca 34 12[ ]+lwpval \$0x1234,%edx,%dx +[ ]*[a-f0-9]+: 8f ea 60 12 cb 34 12[ ]+lwpval \$0x1234,%ebx,%bx +[ ]*[a-f0-9]+: 8f ea 58 12 cc 34 12[ ]+lwpval \$0x1234,%esp,%sp +[ ]*[a-f0-9]+: 8f ea 50 12 cd 34 12[ ]+lwpval \$0x1234,%ebp,%bp +[ ]*[a-f0-9]+: 8f ea 48 12 ce 34 12[ ]+lwpval \$0x1234,%esi,%si +[ ]*[a-f0-9]+: 8f ea 40 12 cf 34 12[ ]+lwpval \$0x1234,%edi,%di +[ ]*[a-f0-9]+: 8f ea 7c 12 cf 78 56 34 12[ ]+lwpval \$0x12345678,%edi,%eax +[ ]*[a-f0-9]+: 8f ea 74 12 ce 78 56 34 12[ ]+lwpval \$0x12345678,%esi,%ecx +[ ]*[a-f0-9]+: 8f ea 6c 12 cd 78 56 34 12[ ]+lwpval \$0x12345678,%ebp,%edx +[ ]*[a-f0-9]+: 8f ea 64 12 cc 78 56 34 12[ ]+lwpval \$0x12345678,%esp,%ebx +[ ]*[a-f0-9]+: 8f ea 5c 12 cb 78 56 34 12[ ]+lwpval \$0x12345678,%ebx,%esp +[ ]*[a-f0-9]+: 8f ea 54 12 ca 78 56 34 12[ ]+lwpval \$0x12345678,%edx,%ebp +[ ]*[a-f0-9]+: 8f ea 4c 12 c9 78 56 34 12[ ]+lwpval \$0x12345678,%ecx,%esi +[ ]*[a-f0-9]+: 8f ea 44 12 c8 78 56 34 12[ ]+lwpval \$0x12345678,%eax,%edi +[ ]*[a-f0-9]+: 8f ea 78 12 00 34 12[ ]+lwpins \$0x1234,\(%eax\),%ax +[ ]*[a-f0-9]+: 8f ea 70 12 01 34 12[ ]+lwpins \$0x1234,\(%ecx\),%cx +[ ]*[a-f0-9]+: 8f ea 68 12 02 34 12[ ]+lwpins \$0x1234,\(%edx\),%dx +[ ]*[a-f0-9]+: 8f ea 60 12 03 34 12[ ]+lwpins \$0x1234,\(%ebx\),%bx +[ ]*[a-f0-9]+: 8f ea 58 12 04 24 34 12[ ]+lwpins \$0x1234,\(%esp\),%sp +[ ]*[a-f0-9]+: 8f ea 50 12 45 00 34 12[ ]+lwpins \$0x1234,0x0\(%ebp\),%bp +[ ]*[a-f0-9]+: 8f ea 48 12 06 34 12[ ]+lwpins \$0x1234,\(%esi\),%si +[ ]*[a-f0-9]+: 8f ea 40 12 07 34 12[ ]+lwpins \$0x1234,\(%edi\),%di +[ ]*[a-f0-9]+: 8f ea 7c 12 07 78 56 34 12[ ]+lwpins \$0x12345678,\(%edi\),%eax +[ ]*[a-f0-9]+: 8f ea 74 12 06 78 56 34 12[ ]+lwpins \$0x12345678,\(%esi\),%ecx +[ ]*[a-f0-9]+: 8f ea 6c 12 45 00 78 56 34 12[ ]+lwpins \$0x12345678,0x0\(%ebp\),%edx +[ ]*[a-f0-9]+: 8f ea 64 12 04 24 78 56 34 12[ ]+lwpins \$0x12345678,\(%esp\),%ebx +[ ]*[a-f0-9]+: 8f ea 5c 12 03 78 56 34 12[ ]+lwpins \$0x12345678,\(%ebx\),%esp +[ ]*[a-f0-9]+: 8f ea 54 12 02 78 56 34 12[ ]+lwpins \$0x12345678,\(%edx\),%ebp +[ ]*[a-f0-9]+: 8f ea 4c 12 01 78 56 34 12[ ]+lwpins \$0x12345678,\(%ecx\),%esi +[ ]*[a-f0-9]+: 8f ea 44 12 00 78 56 34 12[ ]+lwpins \$0x12345678,\(%eax\),%edi +[ ]*[a-f0-9]+: 8f ea 78 12 08 34 12[ ]+lwpval \$0x1234,\(%eax\),%ax +[ ]*[a-f0-9]+: 8f ea 70 12 09 34 12[ ]+lwpval \$0x1234,\(%ecx\),%cx +[ ]*[a-f0-9]+: 8f ea 68 12 0a 34 12[ ]+lwpval \$0x1234,\(%edx\),%dx +[ ]*[a-f0-9]+: 8f ea 60 12 0b 34 12[ ]+lwpval \$0x1234,\(%ebx\),%bx +[ ]*[a-f0-9]+: 8f ea 58 12 0c 24 34 12[ ]+lwpval \$0x1234,\(%esp\),%sp +[ ]*[a-f0-9]+: 8f ea 50 12 4d 00 34 12[ ]+lwpval \$0x1234,0x0\(%ebp\),%bp +[ ]*[a-f0-9]+: 8f ea 48 12 0e 34 12[ ]+lwpval \$0x1234,\(%esi\),%si +[ ]*[a-f0-9]+: 8f ea 40 12 0f 34 12[ ]+lwpval \$0x1234,\(%edi\),%di +[ ]*[a-f0-9]+: 8f ea 7c 12 0f 78 56 34 12[ ]+lwpval \$0x12345678,\(%edi\),%eax +[ ]*[a-f0-9]+: 8f ea 74 12 0e 78 56 34 12[ ]+lwpval \$0x12345678,\(%esi\),%ecx +[ ]*[a-f0-9]+: 8f ea 6c 12 4d 00 78 56 34 12[ ]+lwpval \$0x12345678,0x0\(%ebp\),%edx +[ ]*[a-f0-9]+: 8f ea 64 12 0c 24 78 56 34 12[ ]+lwpval \$0x12345678,\(%esp\),%ebx +[ ]*[a-f0-9]+: 8f ea 5c 12 0b 78 56 34 12[ ]+lwpval \$0x12345678,\(%ebx\),%esp +[ ]*[a-f0-9]+: 8f ea 54 12 0a 78 56 34 12[ ]+lwpval \$0x12345678,\(%edx\),%ebp +[ ]*[a-f0-9]+: 8f ea 4c 12 09 78 56 34 12[ ]+lwpval \$0x12345678,\(%ecx\),%esi +[ ]*[a-f0-9]+: 8f ea 44 12 08 78 56 34 12[ ]+lwpval \$0x12345678,\(%eax\),%edi +[ ]*[a-f0-9]+: 8f ea 78 12 80 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%eax\),%ax +[ ]*[a-f0-9]+: 8f ea 70 12 81 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%ecx\),%cx +[ ]*[a-f0-9]+: 8f ea 68 12 82 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%edx\),%dx +[ ]*[a-f0-9]+: 8f ea 60 12 83 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%ebx\),%bx +[ ]*[a-f0-9]+: 8f ea 58 12 84 24 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%esp\),%sp +[ ]*[a-f0-9]+: 8f ea 50 12 85 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%ebp\),%bp +[ ]*[a-f0-9]+: 8f ea 48 12 86 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%esi\),%si +[ ]*[a-f0-9]+: 8f ea 40 12 87 fe ca 00 00 34 12[ ]+lwpins \$0x1234,0xcafe\(%edi\),%di +[ ]*[a-f0-9]+: 8f ea 7c 12 87 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%edi\),%eax +[ ]*[a-f0-9]+: 8f ea 74 12 86 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%esi\),%ecx +[ ]*[a-f0-9]+: 8f ea 6c 12 85 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%ebp\),%edx +[ ]*[a-f0-9]+: 8f ea 64 12 84 24 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%esp\),%ebx +[ ]*[a-f0-9]+: 8f ea 5c 12 83 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%ebx\),%esp +[ ]*[a-f0-9]+: 8f ea 54 12 82 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%edx\),%ebp +[ ]*[a-f0-9]+: 8f ea 4c 12 81 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%ecx\),%esi +[ ]*[a-f0-9]+: 8f ea 44 12 80 fe ca 00 00 78 56 34 12[ ]+lwpins \$0x12345678,0xcafe\(%eax\),%edi +[ ]*[a-f0-9]+: 8f ea 78 12 88 fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%eax\),%ax +[ ]*[a-f0-9]+: 8f ea 70 12 89 fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%ecx\),%cx +[ ]*[a-f0-9]+: 8f ea 68 12 8a fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%edx\),%dx +[ ]*[a-f0-9]+: 8f ea 60 12 8b fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%ebx\),%bx +[ ]*[a-f0-9]+: 8f ea 58 12 8c 24 fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%esp\),%sp +[ ]*[a-f0-9]+: 8f ea 50 12 8d fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%ebp\),%bp +[ ]*[a-f0-9]+: 8f ea 48 12 8e fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%esi\),%si +[ ]*[a-f0-9]+: 8f ea 40 12 8f fe ca 00 00 34 12[ ]+lwpval \$0x1234,0xcafe\(%edi\),%di +[ ]*[a-f0-9]+: 8f ea 7c 12 8f fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%edi\),%eax +[ ]*[a-f0-9]+: 8f ea 74 12 8e fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%esi\),%ecx +[ ]*[a-f0-9]+: 8f ea 6c 12 8d fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%ebp\),%edx +[ ]*[a-f0-9]+: 8f ea 64 12 8c 24 fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%esp\),%ebx +[ ]*[a-f0-9]+: 8f ea 5c 12 8b fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%ebx\),%esp +[ ]*[a-f0-9]+: 8f ea 54 12 8a fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%edx\),%ebp +[ ]*[a-f0-9]+: 8f ea 4c 12 89 fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%ecx\),%esi +[ ]*[a-f0-9]+: 8f ea 44 12 88 fe ca 00 00 78 56 34 12[ ]+lwpval \$0x12345678,0xcafe\(%eax\),%edi +#pass diff --git a/gas/testsuite/gas/i386/lwp.s b/gas/testsuite/gas/i386/lwp.s new file mode 100644 index 0000000..0f1598e --- /dev/null +++ b/gas/testsuite/gas/i386/lwp.s @@ -0,0 +1,141 @@ +# Check 64bit LWP instructions + + .allow_index_reg + .text +_start: + + llwpcb %ax + llwpcb %cx + llwpcb %dx + llwpcb %bx + llwpcb %sp + llwpcb %bp + llwpcb %si + llwpcb %di + llwpcb %eax + llwpcb %ecx + llwpcb %edx + llwpcb %ebx + llwpcb %esp + llwpcb %ebp + llwpcb %esi + llwpcb %edi + + slwpcb %edi + slwpcb %esi + slwpcb %ebp + slwpcb %esp + slwpcb %ebx + slwpcb %edx + slwpcb %ecx + slwpcb %eax + slwpcb %di + slwpcb %si + slwpcb %bp + slwpcb %sp + slwpcb %bx + slwpcb %dx + slwpcb %cx + slwpcb %ax + + lwpins $0x1234, %eax, %ax + lwpins $0x1234, %ecx, %cx + lwpins $0x1234, %edx, %dx + lwpins $0x1234, %ebx, %bx + lwpins $0x1234, %esp, %sp + lwpins $0x1234, %ebp, %bp + lwpins $0x1234, %esi, %si + lwpins $0x1234, %edi, %di + lwpins $0x12345678, %edi, %eax + lwpins $0x12345678, %esi, %ecx + lwpins $0x12345678, %ebp, %edx + lwpins $0x12345678, %esp, %ebx + lwpins $0x12345678, %ebx, %esp + lwpins $0x12345678, %edx, %ebp + lwpins $0x12345678, %ecx, %esi + lwpins $0x12345678, %eax, %edi + + lwpval $0x1234, %eax, %ax + lwpval $0x1234, %ecx, %cx + lwpval $0x1234, %edx, %dx + lwpval $0x1234, %ebx, %bx + lwpval $0x1234, %esp, %sp + lwpval $0x1234, %ebp, %bp + lwpval $0x1234, %esi, %si + lwpval $0x1234, %edi, %di + lwpval $0x12345678, %edi, %eax + lwpval $0x12345678, %esi, %ecx + lwpval $0x12345678, %ebp, %edx + lwpval $0x12345678, %esp, %ebx + lwpval $0x12345678, %ebx, %esp + lwpval $0x12345678, %edx, %ebp + lwpval $0x12345678, %ecx, %esi + lwpval $0x12345678, %eax, %edi + + lwpins $0x1234, (%eax), %ax + lwpins $0x1234, (%ecx), %cx + lwpins $0x1234, (%edx), %dx + lwpins $0x1234, (%ebx), %bx + lwpins $0x1234, (%esp), %sp + lwpins $0x1234, (%ebp), %bp + lwpins $0x1234, (%esi), %si + lwpins $0x1234, (%edi), %di + lwpins $0x12345678, (%edi), %eax + lwpins $0x12345678, (%esi), %ecx + lwpins $0x12345678, (%ebp), %edx + lwpins $0x12345678, (%esp), %ebx + lwpins $0x12345678, (%ebx), %esp + lwpins $0x12345678, (%edx), %ebp + lwpins $0x12345678, (%ecx), %esi + lwpins $0x12345678, (%eax), %edi + + lwpval $0x1234, (%eax), %ax + lwpval $0x1234, (%ecx), %cx + lwpval $0x1234, (%edx), %dx + lwpval $0x1234, (%ebx), %bx + lwpval $0x1234, (%esp), %sp + lwpval $0x1234, (%ebp), %bp + lwpval $0x1234, (%esi), %si + lwpval $0x1234, (%edi), %di + lwpval $0x12345678, (%edi), %eax + lwpval $0x12345678, (%esi), %ecx + lwpval $0x12345678, (%ebp), %edx + lwpval $0x12345678, (%esp), %ebx + lwpval $0x12345678, (%ebx), %esp + lwpval $0x12345678, (%edx), %ebp + lwpval $0x12345678, (%ecx), %esi + lwpval $0x12345678, (%eax), %edi + + lwpins $0x1234, 0xcafe(%eax), %ax + lwpins $0x1234, 0xcafe(%ecx), %cx + lwpins $0x1234, 0xcafe(%edx), %dx + lwpins $0x1234, 0xcafe(%ebx), %bx + lwpins $0x1234, 0xcafe(%esp), %sp + lwpins $0x1234, 0xcafe(%ebp), %bp + lwpins $0x1234, 0xcafe(%esi), %si + lwpins $0x1234, 0xcafe(%edi), %di + lwpins $0x12345678, 0xcafe(%edi), %eax + lwpins $0x12345678, 0xcafe(%esi), %ecx + lwpins $0x12345678, 0xcafe(%ebp), %edx + lwpins $0x12345678, 0xcafe(%esp), %ebx + lwpins $0x12345678, 0xcafe(%ebx), %esp + lwpins $0x12345678, 0xcafe(%edx), %ebp + lwpins $0x12345678, 0xcafe(%ecx), %esi + lwpins $0x12345678, 0xcafe(%eax), %edi + + lwpval $0x1234, 0xcafe(%eax), %ax + lwpval $0x1234, 0xcafe(%ecx), %cx + lwpval $0x1234, 0xcafe(%edx), %dx + lwpval $0x1234, 0xcafe(%ebx), %bx + lwpval $0x1234, 0xcafe(%esp), %sp + lwpval $0x1234, 0xcafe(%ebp), %bp + lwpval $0x1234, 0xcafe(%esi), %si + lwpval $0x1234, 0xcafe(%edi), %di + lwpval $0x12345678, 0xcafe(%edi), %eax + lwpval $0x12345678, 0xcafe(%esi), %ecx + lwpval $0x12345678, 0xcafe(%ebp), %edx + lwpval $0x12345678, 0xcafe(%esp), %ebx + lwpval $0x12345678, 0xcafe(%ebx), %esp + lwpval $0x12345678, 0xcafe(%edx), %ebp + lwpval $0x12345678, 0xcafe(%ecx), %esi + lwpval $0x12345678, 0xcafe(%eax), %edi diff --git a/gas/testsuite/gas/i386/x86-64-lwp.d b/gas/testsuite/gas/i386/x86-64-lwp.d new file mode 100644 index 0000000..3f70446 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-lwp.d @@ -0,0 +1,201 @@ +#objdump: -dw +#name: x86-64 LWP + +.*: +file format .* + +Disassembly of section .text: + +0+ <_start>: +[ ]*[a-f0-9]+: 8f e9 78 12 c0[ ]+llwpcb %ax +[ ]*[a-f0-9]+: 8f e9 78 12 c1[ ]+llwpcb %cx +[ ]*[a-f0-9]+: 8f e9 78 12 c2[ ]+llwpcb %dx +[ ]*[a-f0-9]+: 8f e9 78 12 c3[ ]+llwpcb %bx +[ ]*[a-f0-9]+: 8f e9 78 12 c4[ ]+llwpcb %sp +[ ]*[a-f0-9]+: 8f e9 78 12 c5[ ]+llwpcb %bp +[ ]*[a-f0-9]+: 8f e9 78 12 c6[ ]+llwpcb %si +[ ]*[a-f0-9]+: 8f e9 78 12 c7[ ]+llwpcb %di +[ ]*[a-f0-9]+: 8f e9 7c 12 c0[ ]+llwpcb %eax +[ ]*[a-f0-9]+: 8f e9 7c 12 c1[ ]+llwpcb %ecx +[ ]*[a-f0-9]+: 8f e9 7c 12 c2[ ]+llwpcb %edx +[ ]*[a-f0-9]+: 8f e9 7c 12 c3[ ]+llwpcb %ebx +[ ]*[a-f0-9]+: 8f e9 7c 12 c4[ ]+llwpcb %esp +[ ]*[a-f0-9]+: 8f e9 7c 12 c5[ ]+llwpcb %ebp +[ ]*[a-f0-9]+: 8f e9 7c 12 c6[ ]+llwpcb %esi +[ ]*[a-f0-9]+: 8f e9 7c 12 c7[ ]+llwpcb %edi +[ ]*[a-f0-9]+: 8f e9 f8 12 c0[ ]+llwpcb %rax +[ ]*[a-f0-9]+: 8f e9 f8 12 c1[ ]+llwpcb %rcx +[ ]*[a-f0-9]+: 8f e9 f8 12 c2[ ]+llwpcb %rdx +[ ]*[a-f0-9]+: 8f e9 f8 12 c3[ ]+llwpcb %rbx +[ ]*[a-f0-9]+: 8f e9 f8 12 c4[ ]+llwpcb %rsp +[ ]*[a-f0-9]+: 8f e9 f8 12 c5[ ]+llwpcb %rbp +[ ]*[a-f0-9]+: 8f e9 f8 12 c6[ ]+llwpcb %rsi +[ ]*[a-f0-9]+: 8f e9 f8 12 c7[ ]+llwpcb %rdi +[ ]*[a-f0-9]+: 8f e9 f8 12 cf[ ]+slwpcb %rdi +[ ]*[a-f0-9]+: 8f e9 f8 12 ce[ ]+slwpcb %rsi +[ ]*[a-f0-9]+: 8f e9 f8 12 cd[ ]+slwpcb %rbp +[ ]*[a-f0-9]+: 8f e9 f8 12 cc[ ]+slwpcb %rsp +[ ]*[a-f0-9]+: 8f e9 f8 12 cb[ ]+slwpcb %rbx +[ ]*[a-f0-9]+: 8f e9 f8 12 ca[ ]+slwpcb %rdx +[ ]*[a-f0-9]+: 8f e9 f8 12 c9[ ]+slwpcb %rcx +[ ]*[a-f0-9]+: 8f e9 f8 12 c8[ ]+slwpcb %rax +[ ]*[a-f0-9]+: 8f e9 7c 12 cf[ ]+slwpcb %edi +[ ]*[a-f0-9]+: 8f e9 7c 12 ce[ ]+slwpcb %esi +[ ]*[a-f0-9]+: 8f e9 7c 12 cd[ ]+slwpcb %ebp +[ ]*[a-f0-9]+: 8f e9 7c 12 cc[ ]+slwpcb %esp +[ ]*[a-f0-9]+: 8f e9 7c 12 cb[ ]+slwpcb %ebx +[ ]*[a-f0-9]+: 8f e9 7c 12 ca[ ]+slwpcb %edx +[ ]*[a-f0-9]+: 8f e9 7c 12 c9[ ]+slwpcb %ecx +[ ]*[a-f0-9]+: 8f e9 7c 12 c8[ ]+slwpcb %eax +[ ]*[a-f0-9]+: 8f e9 78 12 cf[ ]+slwpcb %di +[ ]*[a-f0-9]+: 8f e9 78 12 ce[ ]+slwpcb %si +[ ]*[a-f0-9]+: 8f e9 78 12 cd[ ]+slwpcb %bp +[ ]*[a-f0-9]+: 8f e9 78 12 cc[ ]+slwpcb %sp +[ ]*[a-f0-9]+: 8f e9 78 12 cb[ ]+slwpcb %bx +[ ]*[a-f0-9]+: 8f e9 78 12 ca[ ]+slwpcb %dx +[ ]*[a-f0-9]+: 8f e9 78 12 c9[ ]+slwpcb %cx +[ ]*[a-f0-9]+: 8f e9 78 12 c8[ ]+slwpcb %ax +[ ]*[a-f0-9]+: 8f ea 78 12 c0 34 12[ ]+lwpins \$0x1234,%eax,%ax +[ ]*[a-f0-9]+: 8f ea 70 12 c1 34 12[ ]+lwpins \$0x1234,%ecx,%cx +[ ]*[a-f0-9]+: 8f ea 68 12 c2 34 12[ ]+lwpins \$0x1234,%edx,%dx +[ ]*[a-f0-9]+: 8f ea 60 12 c3 34 12[ ]+lwpins \$0x1234,%ebx,%bx +[ ]*[a-f0-9]+: 8f ea 58 12 c4 34 12[ ]+lwpins \$0x1234,%esp,%sp +[ ]*[a-f0-9]+: 8f ea 50 12 c5 34 12[ ]+lwpins \$0x1234,%ebp,%bp +[ ]*[a-f0-9]+: 8f ea 48 12 c6 34 12[ ]+lwpins \$0x1234,%esi,%si +[ ]*[a-f0-9]+: 8f ea 40 12 c7 34 12[ ]+lwpins \$0x1234,%edi,%di +[ ]*[a-f0-9]+: 8f ea 7c 12 c7 78 56 34 12[ ]+lwpins \$0x12345678,%edi,%eax +[ ]*[a-f0-9]+: 8f ea 74 12 c6 78 56 34 12[ ]+lwpins \$0x12345678,%esi,%ecx +[ ]*[a-f0-9]+: 8f ea 6c 12 c5 78 56 34 12[ ]+lwpins \$0x12345678,%ebp,%edx +[ ]*[a-f0-9]+: 8f ea 64 12 c4 78 56 34 12[ ]+lwpins \$0x12345678,%esp,%ebx +[ ]*[a-f0-9]+: 8f ea 5c 12 c3 78 56 34 12[ ]+lwpins \$0x12345678,%ebx,%esp +[ ]*[a-f0-9]+: 8f ea 54 12 c2 78 56 34 12[ ]+lwpins \$0x12345678,%edx,%ebp +[ ]*[a-f0-9]+: 8f ea 4c 12 c1 78 56 34 12[ ]+lwpins \$0x12345678,%ecx,%esi +[ ]*[a-f0-9]+: 8f ea 44 12 c0 78 56 34 12[ ]+lwpins \$0x12345678,%eax,%edi +[ ]*[a-f0-9]+: 8f ea f8 12 c0 78 56 34 12[ ]+lwpins \$0x12345678,%eax,%rax +[ ]*[a-f0-9]+: 8f ea f0 12 c1 78 56 34 12[ ]+lwpins \$0x12345678,%ecx,%rcx +[ ]*[a-f0-9]+: 8f ea e8 12 c2 78 56 34 12[ ]+lwpins \$0x12345678,%edx,%rdx +[ ]*[a-f0-9]+: 8f ea e0 12 c3 78 56 34 12[ ]+lwpins \$0x12345678,%ebx,%rbx +[ ]*[a-f0-9]+: 8f ea d8 12 c4 78 56 34 12[ ]+lwpins \$0x12345678,%esp,%rsp +[ ]*[a-f0-9]+: 8f ea d0 12 c5 78 56 34 12[ ]+lwpins \$0x12345678,%ebp,%rbp +[ ]*[a-f0-9]+: 8f ea c8 12 c6 78 56 34 12[ ]+lwpins \$0x12345678,%esi,%rsi +[ ]*[a-f0-9]+: 8f ea c0 12 c7 78 56 34 12[ ]+lwpins \$0x12345678,%edi,%rdi +[ ]*[a-f0-9]+: 8f ea 78 12 c8 34 12[ ]+lwpval \$0x1234,%eax,%ax +[ ]*[a-f0-9]+: 8f ea 70 12 c9 34 12[ ]+lwpval \$0x1234,%ecx,%cx +[ ]*[a-f0-9]+: 8f ea 68 12 ca 34 12[ ]+lwpval \$0x1234,%edx,%dx +[ ]*[a-f0-9]+: 8f ea 60 12 cb 34 12[ ]+lwpval \$0x1234,%ebx,%bx +[ ]*[a-f0-9]+: 8f ea 58 12 cc 34 12[ ]+lwpval \$0x1234,%esp,%sp +[ ]*[a-f0-9]+: 8f ea 50 12 cd 34 12[ ]+lwpval \$0x1234,%ebp,%bp +[ ]*[a-f0-9]+: 8f ea 48 12 ce 34 12[ ]+lwpval \$0x1234,%esi,%si +[ ]*[a-f0-9]+: 8f ea 40 12 cf 34 12[ ]+lwpval \$0x1234,%edi,%di +[ ]*[a-f0-9]+: 8f ea 7c 12 cf 78 56 34 12[ ]+lwpval \$0x12345678,%edi,%eax +[ ]*[a-f0-9]+: 8f ea 74 12 ce 78 56 34 12[ ]+lwpval \$0x12345678,%esi,%ecx +[ ]*[a-f0-9]+: 8f ea 6c 12 cd 78 56 34 12[ ]+lwpval \$0x12345678,%ebp,%edx +[ ]*[a-f0-9]+: 8f ea 64 12 cc 78 56 34 12[ ]+lwpval \$0x12345678,%esp,%ebx +[ ]*[a-f0-9]+: 8f ea 5c 12 cb 78 56 34 12[ ]+lwpval \$0x12345678,%ebx,%esp +[ ]*[a-f0-9]+: 8f ea 54 12 ca 78 56 34 12[ ]+lwpval \$0x12345678,%edx,%ebp +[ ]*[a-f0-9]+: 8f ea 4c 12 c9 78 56 34 12[ ]+lwpval \$0x12345678,%ecx,%esi +[ ]*[a-f0-9]+: 8f ea 44 12 c8 78 56 34 12[ ]+lwpval \$0x12345678,%eax,%edi +[ ]*[a-f0-9]+: 8f ea f8 12 c8 78 56 34 12[ ]+lwpval \$0x12345678,%eax,%rax +[ ]*[a-f0-9]+: 8f ea f0 12 c9 78 56 34 12[ ]+lwpval \$0x12345678,%ecx,%rcx +[ ]*[a-f0-9]+: 8f ea e8 12 ca 78 56 34 12[ ]+lwpval \$0x12345678,%edx,%rdx +[ ]*[a-f0-9]+: 8f ea e0 12 cb 78 56 34 12[ ]+lwpval \$0x12345678,%ebx,%rbx +[ ]*[a-f0-9]+: 8f ea d8 12 cc 78 56 34 12[ ]+lwpval \$0x12345678,%esp,%rsp +[ ]*[a-f0-9]+: 8f ea d0 12 cd 78 56 34 12[ ]+lwpval \$0x12345678,%ebp,%rbp +[ ]*[a-f0-9]+: 8f ea c8 12 ce 78 56 34 12[ ]+lwpval \$0x12345678,%esi,%rsi +[ ]*[a-f0-9]+: 8f ea c0 12 cf 78 56 34 12[ ]+lwpval \$0x12345678,%edi,%rdi +[ ]*[a-f0-9]+: 67 8f ea 78 12 00 34 12[ ]+addr32 lwpins \$0x1234,\(%eax\),%ax +[ ]*[a-f0-9]+: 67 8f ea 70 12 01 34 12[ ]+addr32 lwpins \$0x1234,\(%ecx\),%cx +[ ]*[a-f0-9]+: 67 8f ea 68 12 02 34 12[ ]+addr32 lwpins \$0x1234,\(%edx\),%dx +[ ]*[a-f0-9]+: 67 8f ea 60 12 03 34 12[ ]+addr32 lwpins \$0x1234,\(%ebx\),%bx +[ ]*[a-f0-9]+: 67 8f ea 58 12 04 24 34 12[ ]+addr32 lwpins \$0x1234,\(%esp\),%sp +[ ]*[a-f0-9]+: 67 8f ea 50 12 45 00 34 12[ ]+addr32 lwpins \$0x1234,0x0\(%ebp\),%bp +[ ]*[a-f0-9]+: 67 8f ea 48 12 06 34 12[ ]+addr32 lwpins \$0x1234,\(%esi\),%si +[ ]*[a-f0-9]+: 67 8f ea 40 12 07 34 12[ ]+addr32 lwpins \$0x1234,\(%edi\),%di +[ ]*[a-f0-9]+: 67 8f ea 7c 12 07 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%edi\),%eax +[ ]*[a-f0-9]+: 67 8f ea 74 12 06 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%esi\),%ecx +[ ]*[a-f0-9]+: 67 8f ea 6c 12 45 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0x0\(%ebp\),%edx +[ ]*[a-f0-9]+: 67 8f ea 64 12 04 24 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%esp\),%ebx +[ ]*[a-f0-9]+: 67 8f ea 5c 12 03 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%ebx\),%esp +[ ]*[a-f0-9]+: 67 8f ea 54 12 02 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%edx\),%ebp +[ ]*[a-f0-9]+: 67 8f ea 4c 12 01 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%ecx\),%esi +[ ]*[a-f0-9]+: 67 8f ea 44 12 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%eax\),%edi +[ ]*[a-f0-9]+: 67 8f ea f8 12 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%eax\),%rax +[ ]*[a-f0-9]+: 67 8f ea f0 12 01 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%ecx\),%rcx +[ ]*[a-f0-9]+: 67 8f ea e8 12 02 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%edx\),%rdx +[ ]*[a-f0-9]+: 67 8f ea e0 12 03 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%ebx\),%rbx +[ ]*[a-f0-9]+: 67 8f ea d8 12 04 24 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%esp\),%rsp +[ ]*[a-f0-9]+: 67 8f ea d0 12 45 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0x0\(%ebp\),%rbp +[ ]*[a-f0-9]+: 67 8f ea c8 12 06 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%esi\),%rsi +[ ]*[a-f0-9]+: 67 8f ea c0 12 07 78 56 34 12[ ]+addr32 lwpins \$0x12345678,\(%edi\),%rdi +[ ]*[a-f0-9]+: 67 8f ea 78 12 08 34 12[ ]+addr32 lwpval \$0x1234,\(%eax\),%ax +[ ]*[a-f0-9]+: 67 8f ea 70 12 09 34 12[ ]+addr32 lwpval \$0x1234,\(%ecx\),%cx +[ ]*[a-f0-9]+: 67 8f ea 68 12 0a 34 12[ ]+addr32 lwpval \$0x1234,\(%edx\),%dx +[ ]*[a-f0-9]+: 67 8f ea 60 12 0b 34 12[ ]+addr32 lwpval \$0x1234,\(%ebx\),%bx +[ ]*[a-f0-9]+: 67 8f ea 58 12 0c 24 34 12[ ]+addr32 lwpval \$0x1234,\(%esp\),%sp +[ ]*[a-f0-9]+: 67 8f ea 50 12 4d 00 34 12[ ]+addr32 lwpval \$0x1234,0x0\(%ebp\),%bp +[ ]*[a-f0-9]+: 67 8f ea 48 12 0e 34 12[ ]+addr32 lwpval \$0x1234,\(%esi\),%si +[ ]*[a-f0-9]+: 67 8f ea 40 12 0f 34 12[ ]+addr32 lwpval \$0x1234,\(%edi\),%di +[ ]*[a-f0-9]+: 67 8f ea 7c 12 0f 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%edi\),%eax +[ ]*[a-f0-9]+: 67 8f ea 74 12 0e 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%esi\),%ecx +[ ]*[a-f0-9]+: 67 8f ea 6c 12 4d 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0x0\(%ebp\),%edx +[ ]*[a-f0-9]+: 67 8f ea 64 12 0c 24 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%esp\),%ebx +[ ]*[a-f0-9]+: 67 8f ea 5c 12 0b 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%ebx\),%esp +[ ]*[a-f0-9]+: 67 8f ea 54 12 0a 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%edx\),%ebp +[ ]*[a-f0-9]+: 67 8f ea 4c 12 09 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%ecx\),%esi +[ ]*[a-f0-9]+: 67 8f ea 44 12 08 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%eax\),%edi +[ ]*[a-f0-9]+: 67 8f ea f8 12 08 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%eax\),%rax +[ ]*[a-f0-9]+: 67 8f ea f0 12 09 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%ecx\),%rcx +[ ]*[a-f0-9]+: 67 8f ea e8 12 0a 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%edx\),%rdx +[ ]*[a-f0-9]+: 67 8f ea e0 12 0b 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%ebx\),%rbx +[ ]*[a-f0-9]+: 67 8f ea d8 12 0c 24 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%esp\),%rsp +[ ]*[a-f0-9]+: 67 8f ea d0 12 4d 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0x0\(%ebp\),%rbp +[ ]*[a-f0-9]+: 67 8f ea c8 12 0e 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%esi\),%rsi +[ ]*[a-f0-9]+: 67 8f ea c0 12 0f 78 56 34 12[ ]+addr32 lwpval \$0x12345678,\(%edi\),%rdi +[ ]*[a-f0-9]+: 67 8f ea 78 12 80 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%eax\),%ax +[ ]*[a-f0-9]+: 67 8f ea 70 12 81 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%ecx\),%cx +[ ]*[a-f0-9]+: 67 8f ea 68 12 82 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%edx\),%dx +[ ]*[a-f0-9]+: 67 8f ea 60 12 83 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%ebx\),%bx +[ ]*[a-f0-9]+: 67 8f ea 58 12 84 24 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%esp\),%sp +[ ]*[a-f0-9]+: 67 8f ea 50 12 85 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%ebp\),%bp +[ ]*[a-f0-9]+: 67 8f ea 48 12 86 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%esi\),%si +[ ]*[a-f0-9]+: 67 8f ea 40 12 87 fe ca 00 00 34 12[ ]+addr32 lwpins \$0x1234,0xcafe\(%edi\),%di +[ ]*[a-f0-9]+: 67 8f ea 7c 12 87 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%edi\),%eax +[ ]*[a-f0-9]+: 67 8f ea 74 12 86 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%esi\),%ecx +[ ]*[a-f0-9]+: 67 8f ea 6c 12 85 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%ebp\),%edx +[ ]*[a-f0-9]+: 67 8f ea 64 12 84 24 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%esp\),%ebx +[ ]*[a-f0-9]+: 67 8f ea 5c 12 83 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%ebx\),%esp +[ ]*[a-f0-9]+: 67 8f ea 54 12 82 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%edx\),%ebp +[ ]*[a-f0-9]+: 67 8f ea 4c 12 81 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%ecx\),%esi +[ ]*[a-f0-9]+: 67 8f ea 44 12 80 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%eax\),%edi +[ ]*[a-f0-9]+: 67 8f ea f8 12 80 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%eax\),%rax +[ ]*[a-f0-9]+: 67 8f ea f0 12 81 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%ecx\),%rcx +[ ]*[a-f0-9]+: 67 8f ea e8 12 82 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%edx\),%rdx +[ ]*[a-f0-9]+: 67 8f ea e0 12 83 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%ebx\),%rbx +[ ]*[a-f0-9]+: 67 8f ea d8 12 84 24 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%esp\),%rsp +[ ]*[a-f0-9]+: 67 8f ea d0 12 85 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%ebp\),%rbp +[ ]*[a-f0-9]+: 67 8f ea c8 12 86 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%esi\),%rsi +[ ]*[a-f0-9]+: 67 8f ea c0 12 87 fe ca 00 00 78 56 34 12[ ]+addr32 lwpins \$0x12345678,0xcafe\(%edi\),%rdi +[ ]*[a-f0-9]+: 67 8f ea 78 12 88 fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%eax\),%ax +[ ]*[a-f0-9]+: 67 8f ea 70 12 89 fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%ecx\),%cx +[ ]*[a-f0-9]+: 67 8f ea 68 12 8a fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%edx\),%dx +[ ]*[a-f0-9]+: 67 8f ea 60 12 8b fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%ebx\),%bx +[ ]*[a-f0-9]+: 67 8f ea 58 12 8c 24 fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%esp\),%sp +[ ]*[a-f0-9]+: 67 8f ea 50 12 8d fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%ebp\),%bp +[ ]*[a-f0-9]+: 67 8f ea 48 12 8e fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%esi\),%si +[ ]*[a-f0-9]+: 67 8f ea 40 12 8f fe ca 00 00 34 12[ ]+addr32 lwpval \$0x1234,0xcafe\(%edi\),%di +[ ]*[a-f0-9]+: 67 8f ea 7c 12 8f fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%edi\),%eax +[ ]*[a-f0-9]+: 67 8f ea 74 12 8e fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%esi\),%ecx +[ ]*[a-f0-9]+: 67 8f ea 6c 12 8d fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%ebp\),%edx +[ ]*[a-f0-9]+: 67 8f ea 64 12 8c 24 fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%esp\),%ebx +[ ]*[a-f0-9]+: 67 8f ea 5c 12 8b fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%ebx\),%esp +[ ]*[a-f0-9]+: 67 8f ea 54 12 8a fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%edx\),%ebp +[ ]*[a-f0-9]+: 67 8f ea 4c 12 89 fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%ecx\),%esi +[ ]*[a-f0-9]+: 67 8f ea 44 12 88 fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%eax\),%edi +[ ]*[a-f0-9]+: 67 8f ea f8 12 88 fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%eax\),%rax +[ ]*[a-f0-9]+: 67 8f ea f0 12 89 fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%ecx\),%rcx +[ ]*[a-f0-9]+: 67 8f ea e8 12 8a fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%edx\),%rdx +[ ]*[a-f0-9]+: 67 8f ea e0 12 8b fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%ebx\),%rbx +[ ]*[a-f0-9]+: 67 8f ea d8 12 8c 24 fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%esp\),%rsp +[ ]*[a-f0-9]+: 67 8f ea d0 12 8d fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%ebp\),%rbp +[ ]*[a-f0-9]+: 67 8f ea c8 12 8e fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%esi\),%rsi +[ ]*[a-f0-9]+: 67 8f ea c0 12 8f fe ca 00 00 78 56 34 12[ ]+addr32 lwpval \$0x12345678,0xcafe\(%edi\),%rdi +#pass diff --git a/gas/testsuite/gas/i386/x86-64-lwp.s b/gas/testsuite/gas/i386/x86-64-lwp.s new file mode 100644 index 0000000..df6963b --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-lwp.s @@ -0,0 +1,205 @@ +# Check 64bit LWP instructions + + .allow_index_reg + .text +_start: + + llwpcb %ax + llwpcb %cx + llwpcb %dx + llwpcb %bx + llwpcb %sp + llwpcb %bp + llwpcb %si + llwpcb %di + llwpcb %eax + llwpcb %ecx + llwpcb %edx + llwpcb %ebx + llwpcb %esp + llwpcb %ebp + llwpcb %esi + llwpcb %edi + llwpcb %rax + llwpcb %rcx + llwpcb %rdx + llwpcb %rbx + llwpcb %rsp + llwpcb %rbp + llwpcb %rsi + llwpcb %rdi + + slwpcb %rdi + slwpcb %rsi + slwpcb %rbp + slwpcb %rsp + slwpcb %rbx + slwpcb %rdx + slwpcb %rcx + slwpcb %rax + slwpcb %edi + slwpcb %esi + slwpcb %ebp + slwpcb %esp + slwpcb %ebx + slwpcb %edx + slwpcb %ecx + slwpcb %eax + slwpcb %di + slwpcb %si + slwpcb %bp + slwpcb %sp + slwpcb %bx + slwpcb %dx + slwpcb %cx + slwpcb %ax + + lwpins $0x1234, %eax, %ax + lwpins $0x1234, %ecx, %cx + lwpins $0x1234, %edx, %dx + lwpins $0x1234, %ebx, %bx + lwpins $0x1234, %esp, %sp + lwpins $0x1234, %ebp, %bp + lwpins $0x1234, %esi, %si + lwpins $0x1234, %edi, %di + lwpins $0x12345678, %edi, %eax + lwpins $0x12345678, %esi, %ecx + lwpins $0x12345678, %ebp, %edx + lwpins $0x12345678, %esp, %ebx + lwpins $0x12345678, %ebx, %esp + lwpins $0x12345678, %edx, %ebp + lwpins $0x12345678, %ecx, %esi + lwpins $0x12345678, %eax, %edi + lwpins $0x12345678, %eax, %rax + lwpins $0x12345678, %ecx, %rcx + lwpins $0x12345678, %edx, %rdx + lwpins $0x12345678, %ebx, %rbx + lwpins $0x12345678, %esp, %rsp + lwpins $0x12345678, %ebp, %rbp + lwpins $0x12345678, %esi, %rsi + lwpins $0x12345678, %edi, %rdi + + lwpval $0x1234, %eax, %ax + lwpval $0x1234, %ecx, %cx + lwpval $0x1234, %edx, %dx + lwpval $0x1234, %ebx, %bx + lwpval $0x1234, %esp, %sp + lwpval $0x1234, %ebp, %bp + lwpval $0x1234, %esi, %si + lwpval $0x1234, %edi, %di + lwpval $0x12345678, %edi, %eax + lwpval $0x12345678, %esi, %ecx + lwpval $0x12345678, %ebp, %edx + lwpval $0x12345678, %esp, %ebx + lwpval $0x12345678, %ebx, %esp + lwpval $0x12345678, %edx, %ebp + lwpval $0x12345678, %ecx, %esi + lwpval $0x12345678, %eax, %edi + lwpval $0x12345678, %eax, %rax + lwpval $0x12345678, %ecx, %rcx + lwpval $0x12345678, %edx, %rdx + lwpval $0x12345678, %ebx, %rbx + lwpval $0x12345678, %esp, %rsp + lwpval $0x12345678, %ebp, %rbp + lwpval $0x12345678, %esi, %rsi + lwpval $0x12345678, %edi, %rdi + + lwpins $0x1234, (%eax), %ax + lwpins $0x1234, (%ecx), %cx + lwpins $0x1234, (%edx), %dx + lwpins $0x1234, (%ebx), %bx + lwpins $0x1234, (%esp), %sp + lwpins $0x1234, (%ebp), %bp + lwpins $0x1234, (%esi), %si + lwpins $0x1234, (%edi), %di + lwpins $0x12345678, (%edi), %eax + lwpins $0x12345678, (%esi), %ecx + lwpins $0x12345678, (%ebp), %edx + lwpins $0x12345678, (%esp), %ebx + lwpins $0x12345678, (%ebx), %esp + lwpins $0x12345678, (%edx), %ebp + lwpins $0x12345678, (%ecx), %esi + lwpins $0x12345678, (%eax), %edi + lwpins $0x12345678, (%eax), %rax + lwpins $0x12345678, (%ecx), %rcx + lwpins $0x12345678, (%edx), %rdx + lwpins $0x12345678, (%ebx), %rbx + lwpins $0x12345678, (%esp), %rsp + lwpins $0x12345678, (%ebp), %rbp + lwpins $0x12345678, (%esi), %rsi + lwpins $0x12345678, (%edi), %rdi + + lwpval $0x1234, (%eax), %ax + lwpval $0x1234, (%ecx), %cx + lwpval $0x1234, (%edx), %dx + lwpval $0x1234, (%ebx), %bx + lwpval $0x1234, (%esp), %sp + lwpval $0x1234, (%ebp), %bp + lwpval $0x1234, (%esi), %si + lwpval $0x1234, (%edi), %di + lwpval $0x12345678, (%edi), %eax + lwpval $0x12345678, (%esi), %ecx + lwpval $0x12345678, (%ebp), %edx + lwpval $0x12345678, (%esp), %ebx + lwpval $0x12345678, (%ebx), %esp + lwpval $0x12345678, (%edx), %ebp + lwpval $0x12345678, (%ecx), %esi + lwpval $0x12345678, (%eax), %edi + lwpval $0x12345678, (%eax), %rax + lwpval $0x12345678, (%ecx), %rcx + lwpval $0x12345678, (%edx), %rdx + lwpval $0x12345678, (%ebx), %rbx + lwpval $0x12345678, (%esp), %rsp + lwpval $0x12345678, (%ebp), %rbp + lwpval $0x12345678, (%esi), %rsi + lwpval $0x12345678, (%edi), %rdi + + lwpins $0x1234, 0xcafe(%eax), %ax + lwpins $0x1234, 0xcafe(%ecx), %cx + lwpins $0x1234, 0xcafe(%edx), %dx + lwpins $0x1234, 0xcafe(%ebx), %bx + lwpins $0x1234, 0xcafe(%esp), %sp + lwpins $0x1234, 0xcafe(%ebp), %bp + lwpins $0x1234, 0xcafe(%esi), %si + lwpins $0x1234, 0xcafe(%edi), %di + lwpins $0x12345678, 0xcafe(%edi), %eax + lwpins $0x12345678, 0xcafe(%esi), %ecx + lwpins $0x12345678, 0xcafe(%ebp), %edx + lwpins $0x12345678, 0xcafe(%esp), %ebx + lwpins $0x12345678, 0xcafe(%ebx), %esp + lwpins $0x12345678, 0xcafe(%edx), %ebp + lwpins $0x12345678, 0xcafe(%ecx), %esi + lwpins $0x12345678, 0xcafe(%eax), %edi + lwpins $0x12345678, 0xcafe(%eax), %rax + lwpins $0x12345678, 0xcafe(%ecx), %rcx + lwpins $0x12345678, 0xcafe(%edx), %rdx + lwpins $0x12345678, 0xcafe(%ebx), %rbx + lwpins $0x12345678, 0xcafe(%esp), %rsp + lwpins $0x12345678, 0xcafe(%ebp), %rbp + lwpins $0x12345678, 0xcafe(%esi), %rsi + lwpins $0x12345678, 0xcafe(%edi), %rdi + + lwpval $0x1234, 0xcafe(%eax), %ax + lwpval $0x1234, 0xcafe(%ecx), %cx + lwpval $0x1234, 0xcafe(%edx), %dx + lwpval $0x1234, 0xcafe(%ebx), %bx + lwpval $0x1234, 0xcafe(%esp), %sp + lwpval $0x1234, 0xcafe(%ebp), %bp + lwpval $0x1234, 0xcafe(%esi), %si + lwpval $0x1234, 0xcafe(%edi), %di + lwpval $0x12345678, 0xcafe(%edi), %eax + lwpval $0x12345678, 0xcafe(%esi), %ecx + lwpval $0x12345678, 0xcafe(%ebp), %edx + lwpval $0x12345678, 0xcafe(%esp), %ebx + lwpval $0x12345678, 0xcafe(%ebx), %esp + lwpval $0x12345678, 0xcafe(%edx), %ebp + lwpval $0x12345678, 0xcafe(%ecx), %esi + lwpval $0x12345678, 0xcafe(%eax), %edi + lwpval $0x12345678, 0xcafe(%eax), %rax + lwpval $0x12345678, 0xcafe(%ecx), %rcx + lwpval $0x12345678, 0xcafe(%edx), %rdx + lwpval $0x12345678, 0xcafe(%ebx), %rbx + lwpval $0x12345678, 0xcafe(%esp), %rsp + lwpval $0x12345678, 0xcafe(%ebp), %rbp + lwpval $0x12345678, 0xcafe(%esi), %rsi + lwpval $0x12345678, 0xcafe(%edi), %rdi |