Enhance the AARCH64 assembler to support LDFF1xx instructions which use REG+REG addressing with an assumed offset register.

	PR 22988
opcode	* opcode/aarch64.h (enum aarch64_opnd): Add
	AARCH64_OPND_SVE_ADDR_R.

opcodes	* aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
	instructions with only a base address register.
	* aarch64-opc.c (operand_general_constraint_met_p): Add code to
	handle AARHC64_OPND_SVE_ADDR_R.
	(aarch64_print_operand): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64_dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

gas	* config/tc-aarch64.c (parse_operands): Add code to handle
	AARCH64_OPN_SVE_ADDR_R.
	* testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions
	with an assumed XZR offset address register.
	* testsuite/gas/aarch64/sve.d: Update expected disassembly.

4 files changed, 67 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index e1488d3..0df61ed 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2018-03-28  Nick Clifton  <nickc@redhat.com>
+
+	PR 22988
+	* config/tc-aarch64.c (parse_operands): Add code to handle
+	AARCH64_OPN_SVE_ADDR_R.
+	* testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions
+	with an assumed XZR offset address register.
+	* testsuite/gas/aarch64/sve.d: Update expected disassembly.
+
 2018-03-22  Jan Beulich  <jbeulich@suse.com>
 
 	* config/tc-i386.c (check_VecOperands): Latch
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 3a0cde9..e857f29 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -3695,6 +3695,7 @@ parse_address_main (char **str, aarch64_opnd_info *operand,
 	  set_syntax_error (_("missing offset in the pre-indexed address"));
 	  return FALSE;
 	}
+
       operand->addr.preind = 1;
       inst.reloc.exp.X_op = O_constant;
       inst.reloc.exp.X_add_number = 0;
@@ -6233,6 +6234,25 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	  info->addr.offset.imm = inst.reloc.exp.X_add_number;
 	  break;
 
+	case AARCH64_OPND_SVE_ADDR_R:
+	  /* [<Xn|SP>{, <R><m>}]
+	     but recognizing SVE registers.  */
+	  po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
+					      &offset_qualifier));
+	  if (offset_qualifier == AARCH64_OPND_QLF_NIL)
+	    {
+	      offset_qualifier = AARCH64_OPND_QLF_X;
+	      info->addr.offset.is_reg = 1;
+	      info->addr.offset.regno = 31;
+	    }
+	  else if (base_qualifier != AARCH64_OPND_QLF_X
+	      || offset_qualifier != AARCH64_OPND_QLF_X)
+	    {
+	      set_syntax_error (_("invalid addressing mode"));
+	      goto failure;
+	    }
+	  goto regoff_addr;
+	  
 	case AARCH64_OPND_SVE_ADDR_RR:
 	case AARCH64_OPND_SVE_ADDR_RR_LSL1:
 	case AARCH64_OPND_SVE_ADDR_RR_LSL2:
diff --git a/gas/testsuite/gas/aarch64/sve.d b/gas/testsuite/gas/aarch64/sve.d
index 5c7c519..4592891 100644
--- a/gas/testsuite/gas/aarch64/sve.d
+++ b/gas/testsuite/gas/aarch64/sve.d
@@ -40562,3 +40562,18 @@ Disassembly of section .*:
 .*:	0e431441 	fadd	v1\.4h, v2\.4h, v3\.4h
 .*:	4e401400 	fadd	v0\.8h, v0\.8h, v0\.8h
 .*:	4e431441 	fadd	v1\.8h, v2\.8h, v3\.8h
+
+.*:	a41f6400 	ldff1b	\{z0\.b\}, p1/z, \[x0, xzr\]
+.*:	a43f6420 	ldff1b	\{z0\.h\}, p1/z, \[x1, xzr\]
+.*:	a45f6440 	ldff1b	\{z0\.s\}, p1/z, \[x2, xzr\]
+.*:	a47f6460 	ldff1b	\{z0\.d\}, p1/z, \[x3, xzr\]
+.*:	a5ff6000 	ldff1d	\{z0\.d\}, p0/z, \[x0, xzr, lsl #3\]
+.*:	a4bf6520 	ldff1h	\{z0\.h\}, p1/z, \[x9, xzr, lsl #1\]
+.*:	a4df6540 	ldff1h	\{z0\.s\}, p1/z, \[x10, xzr, lsl #1\]
+.*:	a4ff6560 	ldff1h	\{z0\.d\}, p1/z, \[x11, xzr, lsl #1\]
+.*:	a5bf65c0 	ldff1sb	\{z0\.s\}, p1/z, \[x14, xzr\]
+.*:	a59f65e0 	ldff1sb	\{z0\.d\}, p1/z, \[x15, xzr\]
+.*:	a53f6640 	ldff1sh	\{z0\.s\}, p1/z, \[x18, xzr, lsl #1\]
+.*:	a51f6660 	ldff1sh	\{z0\.d\}, p1/z, \[x19, xzr, lsl #1\]
+.*:	a49f66e0 	ldff1sw	\{z0\.d\}, p1/z, \[x23, xzr, lsl #2\]
+.*:	a57f6760 	ldff1w	\{z0\.d\}, p1/z, \[x27, xzr, lsl #2\]
diff --git a/gas/testsuite/gas/aarch64/sve.s b/gas/testsuite/gas/aarch64/sve.s
index 2130b0d..3dbf486 100644
--- a/gas/testsuite/gas/aarch64/sve.s
+++ b/gas/testsuite/gas/aarch64/sve.s
@@ -40540,3 +40540,26 @@
 	ORN       Z0.D, Z0.D, #0X1
 
 	.include  "advsimd-compnum.s"
+
+	#  PR 22988 - check that [Rn] is equivalent to [Rn,xzr]
+	ldff1b   z0.b, p1/z, [x0]
+	ldff1b   z0.h, p1/z, [x1]
+	ldff1b   z0.s, p1/z, [x2]
+	ldff1b   z0.d, p1/z, [x3]
+
+	ldff1d   z0.d, p0/z, [x0]
+
+	ldff1h   z0.h, p1/z, [x9]
+	ldff1h   z0.s, p1/z, [x10]
+	ldff1h   z0.d, p1/z, [x11]
+
+	ldff1sb  z0.s, p1/z, [x14]
+	ldff1sb  z0.d, p1/z, [x15]
+
+	ldff1sh  z0.s, p1/z, [x18]
+	ldff1sh  z0.d, p1/z, [x19]
+
+	ldff1sw  z0.d, p1/z, [x23]
+
+	ldff1w   z0.d, p1/z, [x27]
+