[ARC] Local symbols relocation cleanup

bfd/
2016-02-29  Cupertino Miranda  <cmiranda@synopsys.com>

	* elf32-arc.c (elf_arc_relocate_section): Added rules to fix the
	relocation addend when sections get merged.

gas/
2016-02-29  Cupertino Miranda  <cmiranda@synopsys.com>
	    Claudiu Zissulescu  <Claudiu.Zissulescu@synopsys.com>

        * config/tc-arc.c (arc_extra_reloc): Change size to 0.
        (tc_arc_fix_adjustable): Changed default return value to 1.
        * testsuite/gas/arc/j.d: Updated expected symbol
        * testsuite/gas/arc/jl.d: Likewise
        * testsuite/gas/arc/relax-avoid1.d: Likewise
        * testsuite/gas/arc/st.d: Likewise

ld/
2016-02-29 Cupertino Miranda  <cmiranda@synopsys.com>

	* testsuite/ld-elf/merge.d: Removed xfail for ARC.
	* testsuite/ld-elf/merge2.d: Likewise.
	* testsuite/ld-elf/merge3.d: Likewise.

6 files changed, 66 insertions, 37 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 1815655..4a075bb 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2016-02-29  Cupertino Miranda  <cmiranda@synopsys.com>
+	    Claudiu Zissulescu  <Claudiu.Zissulescu@synopsys.com>
+
+        * config/tc-arc.c (arc_extra_reloc): Change size to 0.
+        (tc_arc_fix_adjustable): Changed default return value to 1.
+        * testsuite/gas/arc/j.d: Updated expected symbol
+        * testsuite/gas/arc/jl.d: Likewise
+        * testsuite/gas/arc/relax-avoid1.d: Likewise
+        * testsuite/gas/arc/st.d: Likewise
+
 2016-02-29  Claudiu Zissulescu  <Claudiu.Zissulescu@synopsys.com>
 
 	* config/tc-arc.c: Enable code density instructions for ARC EM.
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 70a47f9..e509fec 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -591,10 +591,31 @@ arc_extra_reloc (int r_type)
       lab = symbol_find_or_make (lab_name);
       restore_line_pointer (c);
     }
+
+  /* These relocations exist as a mechanism for the compiler to tell the
+     linker how to patch the code if the tls model is optimised.  However,
+     the relocation itself does not require any space within the assembler
+     fragment, and so we pass a size of 0.
+
+     The lines that generate these relocations look like this:
+
+         .tls_gd_ld @.tdata`bl __tls_get_addr@plt
+
+     The '.tls_gd_ld @.tdata' is processed first and generates the
+     additional relocation, while the 'bl __tls_get_addr@plt' is processed
+     second and generates the additional branch.
+
+     It is possible that the additional relocation generated by the
+     '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
+     while the 'bl __tls_get_addr@plt' will be generated as the first thing
+     in the next fragment.  This will be fine; both relocations will still
+     appear to be at the same address in the generated object file.
+     However, this only works as the additional relocation is generated
+     with size of 0 bytes.  */
   fixS *fixP
     = fix_new (frag_now,	/* Which frag?  */
 	       frag_now_fix (),	/* Where in that frag?  */
-	       2,		/* size: 1, 2, or 4 usually.  */
+	       0,		/* size: 1, 2, or 4 usually.  */
 	       sym,		/* X_add_symbol.  */
 	       0,		/* X_add_number.  */
 	       FALSE,		/* TRUE if PC-relative relocation.  */
@@ -3551,7 +3572,7 @@ tc_arc_fix_adjustable (fixS *fixP)
       break;
     }
 
-  return 0; /* FIXME! return 1, fix it in the linker.  */
+  return 1;
 }
 
 /* Compute the reloc type of an expression EXP.  */
diff --git a/gas/testsuite/gas/arc/j.d b/gas/testsuite/gas/arc/j.d
index 8ee8030..341773a 100644
--- a/gas/testsuite/gas/arc/j.d
+++ b/gas/testsuite/gas/arc/j.d
@@ -7,61 +7,61 @@ Disassembly of section .text:
 
 [0-9a-f]+ <text_label>:
    0:	2020 0f80 0000 0000 	j	0
-			4: R_ARC_32_ME	text_label
+			4: R_ARC_32_ME	.text
    8:	20e0 0f80 0000 0000 	j	0
-			c: R_ARC_32_ME	text_label
+			c: R_ARC_32_ME	.text
   10:	20e0 0f80 0000 0000 	j	0
-			14: R_ARC_32_ME	text_label
+			14: R_ARC_32_ME	.text
   18:	20e0 0f81 0000 0000 	jeq	0
-			1c: R_ARC_32_ME	text_label
+			1c: R_ARC_32_ME	.text
   20:	20e0 0f81 0000 0000 	jeq	0
-			24: R_ARC_32_ME	text_label
+			24: R_ARC_32_ME	.text
   28:	20e0 0f82 0000 0000 	jne	0
-			2c: R_ARC_32_ME	text_label
+			2c: R_ARC_32_ME	.text
   30:	20e0 0f82 0000 0000 	jne	0
-			34: R_ARC_32_ME	text_label
+			34: R_ARC_32_ME	.text
   38:	20e0 0f83 0000 0000 	jp	0
-			3c: R_ARC_32_ME	text_label
+			3c: R_ARC_32_ME	.text
   40:	20e0 0f83 0000 0000 	jp	0
-			44: R_ARC_32_ME	text_label
+			44: R_ARC_32_ME	.text
   48:	20e0 0f84 0000 0000 	jn	0
-			4c: R_ARC_32_ME	text_label
+			4c: R_ARC_32_ME	.text
   50:	20e0 0f84 0000 0000 	jn	0
-			54: R_ARC_32_ME	text_label
+			54: R_ARC_32_ME	.text
   58:	20e0 0f85 0000 0000 	jc	0
-			5c: R_ARC_32_ME	text_label
+			5c: R_ARC_32_ME	.text
   60:	20e0 0f85 0000 0000 	jc	0
-			64: R_ARC_32_ME	text_label
+			64: R_ARC_32_ME	.text
   68:	20e0 0f85 0000 0000 	jc	0
-			6c: R_ARC_32_ME	text_label
+			6c: R_ARC_32_ME	.text
   70:	20e0 0f86 0000 0000 	jnc	0
-			74: R_ARC_32_ME	text_label
+			74: R_ARC_32_ME	.text
   78:	20e0 0f86 0000 0000 	jnc	0
-			7c: R_ARC_32_ME	text_label
+			7c: R_ARC_32_ME	.text
   80:	20e0 0f86 0000 0000 	jnc	0
-			84: R_ARC_32_ME	text_label
+			84: R_ARC_32_ME	.text
   88:	20e0 0f87 0000 0000 	jv	0
-			8c: R_ARC_32_ME	text_label
+			8c: R_ARC_32_ME	.text
   90:	20e0 0f87 0000 0000 	jv	0
-			94: R_ARC_32_ME	text_label
+			94: R_ARC_32_ME	.text
   98:	20e0 0f88 0000 0000 	jnv	0
-			9c: R_ARC_32_ME	text_label
+			9c: R_ARC_32_ME	.text
   a0:	20e0 0f88 0000 0000 	jnv	0
-			a4: R_ARC_32_ME	text_label
+			a4: R_ARC_32_ME	.text
   a8:	20e0 0f89 0000 0000 	jgt	0
-			ac: R_ARC_32_ME	text_label
+			ac: R_ARC_32_ME	.text
   b0:	20e0 0f8a 0000 0000 	jge	0
-			b4: R_ARC_32_ME	text_label
+			b4: R_ARC_32_ME	.text
   b8:	20e0 0f8b 0000 0000 	jlt	0
-			bc: R_ARC_32_ME	text_label
+			bc: R_ARC_32_ME	.text
   c0:	20e0 0f8c 0000 0000 	jle	0
-			c4: R_ARC_32_ME	text_label
+			c4: R_ARC_32_ME	.text
   c8:	20e0 0f8d 0000 0000 	jhi	0
-			cc: R_ARC_32_ME	text_label
+			cc: R_ARC_32_ME	.text
   d0:	20e0 0f8e 0000 0000 	jls	0
-			d4: R_ARC_32_ME	text_label
+			d4: R_ARC_32_ME	.text
   d8:	20e0 0f8f 0000 0000 	jpnz	0
-			dc: R_ARC_32_ME	text_label
+			dc: R_ARC_32_ME	.text
   e0:	2020 0f80 0000 0000 	j	0
 			e4: R_ARC_32_ME	external_text_label
   e8:	20a0 0000           	j	0
diff --git a/gas/testsuite/gas/arc/jl.d b/gas/testsuite/gas/arc/jl.d
index 38770f2..ac0c7e7 100644
--- a/gas/testsuite/gas/arc/jl.d
+++ b/gas/testsuite/gas/arc/jl.d
@@ -7,8 +7,8 @@ Disassembly of section .text:
 
 [0-9a-f]+ <text_label>:
    0:	2022 0f80 0000 0000 	jl	0
-			4: R_ARC_32_ME	text_label
+			4: R_ARC_32_ME	.text
    8:	20e3 0042           	jlne.d	\[r1\]
    c:	78e0                	nop_s
    e:	20e2 0f80 0000 0000 	jl	0
-			12: R_ARC_32_ME	text_label
+			12: R_ARC_32_ME	.text
diff --git a/gas/testsuite/gas/arc/relax-avoid1.d b/gas/testsuite/gas/arc/relax-avoid1.d
index 3d6d74e..3a9da7c 100644
--- a/gas/testsuite/gas/arc/relax-avoid1.d
+++ b/gas/testsuite/gas/arc/relax-avoid1.d
@@ -9,5 +9,5 @@ Disassembly of section .text:
 00000000 <.text>:
    0:	78e0                	nop_s
    2:	240a 0f80 0000 0000 	mov	r4,0
-			6: R_ARC_32_ME	.LC2
+			6: R_ARC_32_ME	.rodata
    a:	78e0                	nop_s
diff --git a/gas/testsuite/gas/arc/st.d b/gas/testsuite/gas/arc/st.d
index b329345..4e2ebba 100644
--- a/gas/testsuite/gas/arc/st.d
+++ b/gas/testsuite/gas/arc/st.d
@@ -5,7 +5,7 @@
 
 Disassembly of section .text:
 
-[0-9a-f]+ <.L1-0x40>:
+[0-9a-f]+ <.text>:
    0:	1a00 0040           	st	r1,\[r2\]
    4:	1a0e 0040           	st	r1,\[r2,14\]
    8:	1a00 0042           	stb	r1,\[r2\]
@@ -20,9 +20,7 @@ Disassembly of section .text:
   30:	1a03 0068           	st.di.aw	r1,\[r2,3\]
   34:	1a04 006c           	st[hw]+.di.aw	r1,\[r2,4\]
   38:	1c04 1f80 0000 0000 	st	0,\[r12,4\]
-			3c: R_ARC_32_ME	.L1
-
-[0-9a-f]+ <.L1>:
+			3c: R_ARC_32_ME	.text\+0x40
   40:	212b 0080           	sr	r1,\[r2\]
   44:	216b 0380           	sr	r1,\[0xe\]
   48:	262b 7040 0000 03e8 	sr	0x3e8,\[r1\]