MIPS Documentation fixes

gas/
	* doc/as.texinfo: Update the MIPS FP ABI descriptions.
	* doc/c-mips.texi: Spell check and correct throughout.

3 files changed, 26 insertions, 10 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d246494..3a82302 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2014-10-22  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+	* doc/as.texinfo: Update the MIPS FP ABI descriptions.
+	* doc/c-mips.texi: Spell check and correct throughout.
+
 2014-10-21  Maciej W. Rozycki  <macro@codesourcery.com>
 
 	* config/tc-mips.c (s_insn): Set file options.
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index f93c044..243851b 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -7030,16 +7030,27 @@ The floating-point ABI used by this object file.  The value will be:
 @item
 0 for files not affected by the floating-point ABI.
 @item
-1 for files using the hardware floating-point with a standard double-precision
-FPU.
+1 for files using the hardware floating-point ABI with a standard
+double-precision FPU.
 @item
 2 for files using the hardware floating-point ABI with a single-precision FPU.
 @item
 3 for files using the software floating-point ABI.
 @item
-4 for files using the hardware floating-point ABI with 64-bit wide
-double-precision floating-point registers and 32-bit wide general
-purpose registers.
+4 for files using the deprecated hardware floating-point ABI which used 64-bit
+floating-point registers, 32-bit general-purpose registers and increased the
+number of callee-saved floating-point registers.
+@item
+5 for files using the hardware floating-point ABI with a double-precision FPU
+with either 32-bit or 64-bit floating-point registers and 32-bit
+general-purpose registers.
+@item
+6 for files using the hardware floating-point ABI with 64-bit floating-point
+registers and 32-bit general-purpose registers.
+@item
+7 for files using the hardware floating-point ABI with 64-bit floating-point
+registers, 32-bit general-purpose registers and a rule that forbids the
+direct use of odd-numbered single-precision floating-point registers.
 @end itemize
 @end table
 
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 8d61d04..d960022 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -769,9 +769,9 @@ The @code{.global} and @code{.globl} directives supported by
 region of data not code.  This means that, for example, any
 instructions following such a symbol will not be disassembled by
 @code{objdump} as it will regard them as data.  To change this
-behaviour an optional section name can be placed after the symbol name
+behavior an optional section name can be placed after the symbol name
 in the @code{.global} directive.  If this section exists and is known
-to be a code section, then the symbol will be marked as poiting at
+to be a code section, then the symbol will be marked as pointing at
 code not data.  Ie the syntax for the directive is:
 
   @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
@@ -840,8 +840,8 @@ pass all floating-point data in general-purpose registers.
 
 @item 4 - Deprecated
 This variant existed as an initial attempt at supporting 64-bit wide
-floating-point registers for O32 ABI on a MIPS32r2 cpu.  This has been
-superceded by 5, 6 and 7.
+floating-point registers for O32 ABI on a MIPS32r2 CPU.  This has been
+superseded by 5, 6 and 7.
 
 @item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU
 This variant is used by 32-bit ABIs to indicate that the floating-point
@@ -998,7 +998,7 @@ Release 1 instructions from being accepted.
 @kindex @code{.set nodspr2}
 The directive @code{.set dspr2} makes the assembler accept instructions
 from the DSP Release 2 Application Specific Extension from that point
-on in the assembly.  This dirctive implies @code{.set dsp}.  The
+on in the assembly.  This directive implies @code{.set dsp}.  The
 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
 being accepted.