RISC-V/rvv: Added zve* and zvl* extensions, and clarify the imply rules.

* Recognized zve* and zvl* extensions.
  - zve*: zve64d, zve64f, zve64x, zve32f and zve32x.
  - zvl*: zvl32b, zvl64b, zvl128b, zvl256b, zvl512b, zvl1024b, zvl2048b,
          zvl4096b, zvl8192b, zvl16384b, zvl32768b and zvl65536b.

* Spec said that v requires f and d, zve64d requires d, zve64f and zve32f
  require f.  However, according to the issue 723,
  [https://github.com/riscv/riscv-v-spec/issues/723]

  The general rule is that extension names imply the things they require.
  Therefore, the current imply rules should be as follows,
  - v imply f and d.
  - zve64d imply d.
  - zve64f and zve32f imply f.
  - zvamo imply a.

  Besides, consider the implicit zve and zvl extensions,
  - v imply zve64d and zvl128b.
  - zve64* imply the corresponding zve32*.  For example, zve64f imply zve32f,
    and zve64x imply zve32x.
  - zve*d imply zve*f and zve*x.  For example, zve64d imply zve64f and zve64x.
  - zve*f imply zve*x.  For example, zve64f imply zve64x.
  - zve64* imply zvl64b, and zve32* imply zvl32b.
  - The larger zvl* imply all smaller zvl*.  For example, zvl128b imply zvl64b,
    and zvl32b.

  Therefore, "-march=rv64iv -misa-spec=20191213" will be
  "rv64i2p0_f2p0_d2p0_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0".
  Note: zicsr is the imply extension of f.

* For zve32x, the (segmant) load/store instructions are illegal when EEW is
  64.  Besides, vsew cannot be set to 64 by vsetvli when zve32* is enabled.

* For zvl*b extensions, we also need to enable either v or zve* extensions.
  Otherwise we should issue errors.

bfd/
	* elfxx-riscv.c (riscv_implicit_subsets): Added imply rules for v,
	zve* and zvl*b extensions.
	(riscv_supported_std_z_ext): Added zve* and zvl*b extensions.
	(riscv_parse_check_conflicts): The zvl*b extensions cannot be set
	without v and zve* extensions.
gas/
	* config/tc-riscv.c (riscv_extended_subset_supports): Handle zve*.
	(my_getVsetvliExpression): vsew cannot be set to 64 by vsetvli
	when zve32* is enabled.
	(riscv_ip): The (segmant) loads and stores with EEW 64 cannot be
	used when zve32x is enabled.
	* testsuite/gas/riscv/extended/march-imply-v.d: New testcase.
	* testsuite/gas/riscv/extended/march-imply-zve*.d: Likewise.
	* testsuite/gas/riscv/extended/march-imply-zvl*b.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zve32x.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zve32x.l: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zve32x.s: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zvl.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zvl.l: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Removed
	a-ext from -march since it will be added as implicit ext for zvamo.
	* testsuite/gas/riscv/extended/vector-insns.d: Likewise.
include/
	* opcode/riscv.h: Defined INSN_V_EEW64.
opcodes/
	* riscv-opc.c (riscv_draft_opcodes): Added INSN_V_EEW64 for vector
	loads and stores when the eew encodings are 64.

25 files changed, 633 insertions, 5 deletions

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index cb9edf2..99165f5 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -274,11 +274,17 @@ riscv_extended_subset_supports (int insn_class)
 {
   switch (insn_class)
     {
-    case INSN_CLASS_V: return riscv_subset_supports ("v");
+    case INSN_CLASS_V:
+      return (riscv_subset_supports ("v")
+	      || riscv_subset_supports ("zve64x")
+	      || riscv_subset_supports ("zve32x"));
     case INSN_CLASS_V_AND_F:
-      return riscv_subset_supports ("v") && riscv_subset_supports ("f");
+      return (riscv_subset_supports ("v")
+	      || riscv_subset_supports ("zve64d")
+	      || riscv_subset_supports ("zve64f")
+	      || riscv_subset_supports ("zve32f"));
     case INSN_CLASS_ZVAMO:
-      return riscv_subset_supports ("a") && riscv_subset_supports ("zvamo");
+      return riscv_subset_supports ("zvamo");
 
     case INSN_CLASS_ZFH:
       return riscv_subset_supports ("zfh");
@@ -2453,6 +2459,13 @@ my_getVsetvliExpression (expressionS *ep, char *str)
 	++str;
       if (vsew_found)
 	as_bad (_("multiple vsew constants"));
+      /* The zve32x is the implicit extension of zve32f, and the zve64x is
+	 the implicit extension of zve64f.  */
+      else if (riscv_subset_supports ("zve32x")
+	       && !riscv_subset_supports ("zve64x")
+	       && vsew_value > 2)
+	as_bad (_("illegal vsew %s for zve32x and zve32f"),
+		riscv_vsew[vsew_value]);
       vsew_found = true;
     }
   if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value))
@@ -2862,6 +2875,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		      as_warn (_("read-only CSR is written `%s'"), str);
 		      insn_with_csr = false;
 		    }
+
+		  /* The (segmant) load and store with EEW 64 cannot be used
+		     when zve32x is enabled.  */
+		  if (ip->insn_mo->pinfo & INSN_V_EEW64
+		      && riscv_subset_supports ("zve32x")
+		      && !riscv_subset_supports ("zve64x"))
+		    {
+		      error = _("illegal opcode for zve32x");
+		      break;
+		    }
 		}
 	      if (*asarg != '\0')
 		break;
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-v.d b/gas/testsuite/gas/riscv/extended/march-imply-v.d
new file mode 100644
index 0000000..4177f03
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-v.d
@@ -0,0 +1,6 @@
+#as: -march=rv32iv -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zve32f.d b/gas/testsuite/gas/riscv/extended/march-imply-zve32f.d
new file mode 100644
index 0000000..17b7a67
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zve32f.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32f -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zve32x.d b/gas/testsuite/gas/riscv/extended/march-imply-zve32x.d
new file mode 100644
index 0000000..34742e5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zve32x.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl32b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zve64d.d b/gas/testsuite/gas/riscv/extended/march-imply-zve64d.d
new file mode 100644
index 0000000..f5fb6a5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zve64d.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve64d -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zve64f.d b/gas/testsuite/gas/riscv/extended/march-imply-zve64f.d
new file mode 100644
index 0000000..2cd7224
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zve64f.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve64f -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zve64x.d b/gas/testsuite/gas/riscv/extended/march-imply-zve64x.d
new file mode 100644
index 0000000..96dea6f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zve64x.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve64x -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl1024b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl1024b.d
new file mode 100644
index 0000000..4a68a9c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl1024b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl1024b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl128b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl128b.d
new file mode 100644
index 0000000..ef1ac30
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl128b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl128b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl16384b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl16384b.d
new file mode 100644
index 0000000..a05077a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl16384b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl16384b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl2048b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl2048b.d
new file mode 100644
index 0000000..8c45a98
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl2048b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl2048b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl256b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl256b.d
new file mode 100644
index 0000000..515bfdb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl256b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl256b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl32768b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl32768b.d
new file mode 100644
index 0000000..a10b11a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl32768b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl32768b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl4096b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl4096b.d
new file mode 100644
index 0000000..0951b57
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl4096b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl4096b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl512b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl512b.d
new file mode 100644
index 0000000..14b4390
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl512b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl512b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl64b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl64b.d
new file mode 100644
index 0000000..071bd24
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl64b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl64b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl32b1p0_zvl64b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl65536b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl65536b.d
new file mode 100644
index 0000000..8b1739f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl65536b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl65536b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/march-imply-zvl8192b.d b/gas/testsuite/gas/riscv/extended/march-imply-zvl8192b.d
new file mode 100644
index 0000000..ddfdc50
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/march-imply-zvl8192b.d
@@ -0,0 +1,6 @@
+#as: -march=rv32i_zve32x_zvl8192b -march-attr -misa-spec=20191213
+#readelf: -A
+#source: ../empty.s
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: "rv32i2p1_zve32x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl8192b1p0"
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d
index 8a6de14..ff06d23 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d
@@ -1,3 +1,3 @@
-#as: -march=rv32ia_zvamo -mcheck-constraints
+#as: -march=rv32i_zvamo -mcheck-constraints
 #source: vector-insns-fail-zvamo.s
 #error_output: vector-insns-fail-zvamo.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.d
new file mode 100644
index 0000000..3c60e80
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_zvamo_zve32x
+#source: vector-insns-fail-zve32x.s
+#error_output: vector-insns-fail-zve32x.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.l
new file mode 100644
index 0000000..13f747c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.l
@@ -0,0 +1,82 @@
+.*Assembler messages:
+.*Error: illegal vsew e64 for zve32x and zve32f
+.*Error: illegal vsew e128 for zve32x and zve32f
+.*Error: illegal vsew e256 for zve32x and zve32f
+.*Error: illegal vsew e512 for zve32x and zve32f
+.*Error: illegal vsew e1024 for zve32x and zve32f
+.*Error: illegal opcode for zve32x `vle64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vse64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlse64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vsse64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vloxei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vle64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg2e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg2e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg3e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg3e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg4e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg4e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg5e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg5e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg6e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg6e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg7e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg7e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg8e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vsseg8e64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlsseg2e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg2e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg3e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg3e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg4e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg4e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg5e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg5e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg6e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg6e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg7e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg7e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vlsseg8e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vssseg8e64.v v4,\(a0\),a1'
+.*Error: illegal opcode for zve32x `vloxseg2ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg2ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg3ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg3ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg4ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg4ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg5ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg5ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg6ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg6ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg7ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg7ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vloxseg8ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsoxseg8ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg2ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg2ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg3ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg3ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg4ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg4ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg5ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg5ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg6ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg6ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg7ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg7ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vluxseg8ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vsuxseg8ei64.v v4,\(a0\),v12'
+.*Error: illegal opcode for zve32x `vlseg2e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg3e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg4e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg5e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg6e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg7e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vlseg8e64ff.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vl1re64.v v3,\(a0\)'
+.*Error: illegal opcode for zve32x `vl2re64.v v2,\(a0\)'
+.*Error: illegal opcode for zve32x `vl4re64.v v4,\(a0\)'
+.*Error: illegal opcode for zve32x `vl8re64.v v8,\(a0\)'
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.s b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.s
new file mode 100644
index 0000000..7a0bfe8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zve32x.s
@@ -0,0 +1,413 @@
+	vsetvl a0, a1, a2
+	vsetvli a0, a1, e8
+	vsetvli a0, a1, e16, m2
+	vsetvli a0, a1, e32, m2, ta
+	vsetvli a0, a1, e64, m2, ta, ma
+	vsetvli a0, a1, e128
+	vsetvli a0, a1, e256, m2
+	vsetvli a0, a1, e512, m2, ta
+	vsetvli a0, a1, e1024, m2, ta, ma
+
+	vlm.v v4, (a0)
+	vle1.v v4, (a0)		# Alias of vlm.v
+	vsm.v v4, (a0)
+	vse1.v v4, (a0)		# Alias of vsm.v
+
+	vle8.v v4, (a0)
+	vse8.v v4, (a0)
+	vle16.v v4, (a0)
+	vse16.v v4, (a0)
+	vle32.v v4, (a0)
+	vse32.v v4, (a0)
+	vle64.v v4, (a0)
+	vse64.v v4, (a0)
+
+	vlse8.v v4, (a0), a1
+	vsse8.v v4, (a0), a1
+	vlse16.v v4, (a0), a1
+	vsse16.v v4, (a0), a1
+	vlse32.v v4, (a0), a1
+	vsse32.v v4, (a0), a1
+	vlse64.v v4, (a0), a1
+	vsse64.v v4, (a0), a1
+
+	vloxei8.v v4, (a0), v12
+	vsoxei8.v v4, (a0), v12
+	vluxei8.v v4, (a0), v12
+	vsuxei8.v v4, (a0), v12
+	vloxei16.v v4, (a0), v12
+	vsoxei16.v v4, (a0), v12
+	vluxei16.v v4, (a0), v12
+	vsuxei16.v v4, (a0), v12
+	vloxei32.v v4, (a0), v12
+	vsoxei32.v v4, (a0), v12
+	vluxei32.v v4, (a0), v12
+	vsuxei32.v v4, (a0), v12
+	vloxei64.v v4, (a0), v12
+	vsoxei64.v v4, (a0), v12
+	vluxei64.v v4, (a0), v12
+	vsuxei64.v v4, (a0), v12
+
+	vle8ff.v v4, (a0)
+	vle16ff.v v4, (a0)
+	vle32ff.v v4, (a0)
+	vle64ff.v v4, (a0)
+
+	vlseg2e8.v v4, (a0)
+	vsseg2e8.v v4, (a0)
+	vlseg3e8.v v4, (a0)
+	vsseg3e8.v v4, (a0)
+	vlseg4e8.v v4, (a0)
+	vsseg4e8.v v4, (a0)
+	vlseg5e8.v v4, (a0)
+	vsseg5e8.v v4, (a0)
+	vlseg6e8.v v4, (a0)
+	vsseg6e8.v v4, (a0)
+	vlseg7e8.v v4, (a0)
+	vsseg7e8.v v4, (a0)
+	vlseg8e8.v v4, (a0)
+	vsseg8e8.v v4, (a0)
+	vlseg2e16.v v4, (a0)
+	vsseg2e16.v v4, (a0)
+	vlseg3e16.v v4, (a0)
+	vsseg3e16.v v4, (a0)
+	vlseg4e16.v v4, (a0)
+	vsseg4e16.v v4, (a0)
+	vlseg5e16.v v4, (a0)
+	vsseg5e16.v v4, (a0)
+	vlseg6e16.v v4, (a0)
+	vsseg6e16.v v4, (a0)
+	vlseg7e16.v v4, (a0)
+	vsseg7e16.v v4, (a0)
+	vlseg8e16.v v4, (a0)
+	vsseg8e16.v v4, (a0)
+	vlseg2e32.v v4, (a0)
+	vsseg2e32.v v4, (a0)
+	vlseg3e32.v v4, (a0)
+	vsseg3e32.v v4, (a0)
+	vlseg4e32.v v4, (a0)
+	vsseg4e32.v v4, (a0)
+	vlseg5e32.v v4, (a0)
+	vsseg5e32.v v4, (a0)
+	vlseg6e32.v v4, (a0)
+	vsseg6e32.v v4, (a0)
+	vlseg7e32.v v4, (a0)
+	vsseg7e32.v v4, (a0)
+	vlseg8e32.v v4, (a0)
+	vsseg8e32.v v4, (a0)
+	vlseg2e64.v v4, (a0)
+	vsseg2e64.v v4, (a0)
+	vlseg3e64.v v4, (a0)
+	vsseg3e64.v v4, (a0)
+	vlseg4e64.v v4, (a0)
+	vsseg4e64.v v4, (a0)
+	vlseg5e64.v v4, (a0)
+	vsseg5e64.v v4, (a0)
+	vlseg6e64.v v4, (a0)
+	vsseg6e64.v v4, (a0)
+	vlseg7e64.v v4, (a0)
+	vsseg7e64.v v4, (a0)
+	vlseg8e64.v v4, (a0)
+	vsseg8e64.v v4, (a0)
+
+	vlsseg2e8.v v4, (a0), a1
+	vssseg2e8.v v4, (a0), a1
+	vlsseg3e8.v v4, (a0), a1
+	vssseg3e8.v v4, (a0), a1
+	vlsseg4e8.v v4, (a0), a1
+	vssseg4e8.v v4, (a0), a1
+	vlsseg5e8.v v4, (a0), a1
+	vssseg5e8.v v4, (a0), a1
+	vlsseg6e8.v v4, (a0), a1
+	vssseg6e8.v v4, (a0), a1
+	vlsseg7e8.v v4, (a0), a1
+	vssseg7e8.v v4, (a0), a1
+	vlsseg8e8.v v4, (a0), a1
+	vssseg8e8.v v4, (a0), a1
+	vlsseg2e16.v v4, (a0), a1
+	vssseg2e16.v v4, (a0), a1
+	vlsseg3e16.v v4, (a0), a1
+	vssseg3e16.v v4, (a0), a1
+	vlsseg4e16.v v4, (a0), a1
+	vssseg4e16.v v4, (a0), a1
+	vlsseg5e16.v v4, (a0), a1
+	vssseg5e16.v v4, (a0), a1
+	vlsseg6e16.v v4, (a0), a1
+	vssseg6e16.v v4, (a0), a1
+	vlsseg7e16.v v4, (a0), a1
+	vssseg7e16.v v4, (a0), a1
+	vlsseg8e16.v v4, (a0), a1
+	vssseg8e16.v v4, (a0), a1
+	vlsseg2e32.v v4, (a0), a1
+	vssseg2e32.v v4, (a0), a1
+	vlsseg3e32.v v4, (a0), a1
+	vssseg3e32.v v4, (a0), a1
+	vlsseg4e32.v v4, (a0), a1
+	vssseg4e32.v v4, (a0), a1
+	vlsseg5e32.v v4, (a0), a1
+	vssseg5e32.v v4, (a0), a1
+	vlsseg6e32.v v4, (a0), a1
+	vssseg6e32.v v4, (a0), a1
+	vlsseg7e32.v v4, (a0), a1
+	vssseg7e32.v v4, (a0), a1
+	vlsseg8e32.v v4, (a0), a1
+	vssseg8e32.v v4, (a0), a1
+	vlsseg2e64.v v4, (a0), a1
+	vssseg2e64.v v4, (a0), a1
+	vlsseg3e64.v v4, (a0), a1
+	vssseg3e64.v v4, (a0), a1
+	vlsseg4e64.v v4, (a0), a1
+	vssseg4e64.v v4, (a0), a1
+	vlsseg5e64.v v4, (a0), a1
+	vssseg5e64.v v4, (a0), a1
+	vlsseg6e64.v v4, (a0), a1
+	vssseg6e64.v v4, (a0), a1
+	vlsseg7e64.v v4, (a0), a1
+	vssseg7e64.v v4, (a0), a1
+	vlsseg8e64.v v4, (a0), a1
+	vssseg8e64.v v4, (a0), a1
+
+	vloxseg2ei8.v v4, (a0), v12
+	vsoxseg2ei8.v v4, (a0), v12
+	vloxseg3ei8.v v4, (a0), v12
+	vsoxseg3ei8.v v4, (a0), v12
+	vloxseg4ei8.v v4, (a0), v12
+	vsoxseg4ei8.v v4, (a0), v12
+	vloxseg5ei8.v v4, (a0), v12
+	vsoxseg5ei8.v v4, (a0), v12
+	vloxseg6ei8.v v4, (a0), v12
+	vsoxseg6ei8.v v4, (a0), v12
+	vloxseg7ei8.v v4, (a0), v12
+	vsoxseg7ei8.v v4, (a0), v12
+	vloxseg8ei8.v v4, (a0), v12
+	vsoxseg8ei8.v v4, (a0), v12
+	vloxseg2ei16.v v4, (a0), v12
+	vsoxseg2ei16.v v4, (a0), v12
+	vloxseg3ei16.v v4, (a0), v12
+	vsoxseg3ei16.v v4, (a0), v12
+	vloxseg4ei16.v v4, (a0), v12
+	vsoxseg4ei16.v v4, (a0), v12
+	vloxseg5ei16.v v4, (a0), v12
+	vsoxseg5ei16.v v4, (a0), v12
+	vloxseg6ei16.v v4, (a0), v12
+	vsoxseg6ei16.v v4, (a0), v12
+	vloxseg7ei16.v v4, (a0), v12
+	vsoxseg7ei16.v v4, (a0), v12
+	vloxseg8ei16.v v4, (a0), v12
+	vsoxseg8ei16.v v4, (a0), v12
+	vloxseg2ei32.v v4, (a0), v12
+	vsoxseg2ei32.v v4, (a0), v12
+	vloxseg3ei32.v v4, (a0), v12
+	vsoxseg3ei32.v v4, (a0), v12
+	vloxseg4ei32.v v4, (a0), v12
+	vsoxseg4ei32.v v4, (a0), v12
+	vloxseg5ei32.v v4, (a0), v12
+	vsoxseg5ei32.v v4, (a0), v12
+	vloxseg6ei32.v v4, (a0), v12
+	vsoxseg6ei32.v v4, (a0), v12
+	vloxseg7ei32.v v4, (a0), v12
+	vsoxseg7ei32.v v4, (a0), v12
+	vloxseg8ei32.v v4, (a0), v12
+	vsoxseg8ei32.v v4, (a0), v12
+	vloxseg2ei64.v v4, (a0), v12
+	vsoxseg2ei64.v v4, (a0), v12
+	vloxseg3ei64.v v4, (a0), v12
+	vsoxseg3ei64.v v4, (a0), v12
+	vloxseg4ei64.v v4, (a0), v12
+	vsoxseg4ei64.v v4, (a0), v12
+	vloxseg5ei64.v v4, (a0), v12
+	vsoxseg5ei64.v v4, (a0), v12
+	vloxseg6ei64.v v4, (a0), v12
+	vsoxseg6ei64.v v4, (a0), v12
+	vloxseg7ei64.v v4, (a0), v12
+	vsoxseg7ei64.v v4, (a0), v12
+	vloxseg8ei64.v v4, (a0), v12
+	vsoxseg8ei64.v v4, (a0), v12
+
+	vluxseg2ei8.v v4, (a0), v12
+	vsuxseg2ei8.v v4, (a0), v12
+	vluxseg3ei8.v v4, (a0), v12
+	vsuxseg3ei8.v v4, (a0), v12
+	vluxseg4ei8.v v4, (a0), v12
+	vsuxseg4ei8.v v4, (a0), v12
+	vluxseg5ei8.v v4, (a0), v12
+	vsuxseg5ei8.v v4, (a0), v12
+	vluxseg6ei8.v v4, (a0), v12
+	vsuxseg6ei8.v v4, (a0), v12
+	vluxseg7ei8.v v4, (a0), v12
+	vsuxseg7ei8.v v4, (a0), v12
+	vluxseg8ei8.v v4, (a0), v12
+	vsuxseg8ei8.v v4, (a0), v12
+	vluxseg2ei16.v v4, (a0), v12
+	vsuxseg2ei16.v v4, (a0), v12
+	vluxseg3ei16.v v4, (a0), v12
+	vsuxseg3ei16.v v4, (a0), v12
+	vluxseg4ei16.v v4, (a0), v12
+	vsuxseg4ei16.v v4, (a0), v12
+	vluxseg5ei16.v v4, (a0), v12
+	vsuxseg5ei16.v v4, (a0), v12
+	vluxseg6ei16.v v4, (a0), v12
+	vsuxseg6ei16.v v4, (a0), v12
+	vluxseg7ei16.v v4, (a0), v12
+	vsuxseg7ei16.v v4, (a0), v12
+	vluxseg8ei16.v v4, (a0), v12
+	vsuxseg8ei16.v v4, (a0), v12
+	vluxseg2ei32.v v4, (a0), v12
+	vsuxseg2ei32.v v4, (a0), v12
+	vluxseg3ei32.v v4, (a0), v12
+	vsuxseg3ei32.v v4, (a0), v12
+	vluxseg4ei32.v v4, (a0), v12
+	vsuxseg4ei32.v v4, (a0), v12
+	vluxseg5ei32.v v4, (a0), v12
+	vsuxseg5ei32.v v4, (a0), v12
+	vluxseg6ei32.v v4, (a0), v12
+	vsuxseg6ei32.v v4, (a0), v12
+	vluxseg7ei32.v v4, (a0), v12
+	vsuxseg7ei32.v v4, (a0), v12
+	vluxseg8ei32.v v4, (a0), v12
+	vsuxseg8ei32.v v4, (a0), v12
+	vluxseg2ei64.v v4, (a0), v12
+	vsuxseg2ei64.v v4, (a0), v12
+	vluxseg3ei64.v v4, (a0), v12
+	vsuxseg3ei64.v v4, (a0), v12
+	vluxseg4ei64.v v4, (a0), v12
+	vsuxseg4ei64.v v4, (a0), v12
+	vluxseg5ei64.v v4, (a0), v12
+	vsuxseg5ei64.v v4, (a0), v12
+	vluxseg6ei64.v v4, (a0), v12
+	vsuxseg6ei64.v v4, (a0), v12
+	vluxseg7ei64.v v4, (a0), v12
+	vsuxseg7ei64.v v4, (a0), v12
+	vluxseg8ei64.v v4, (a0), v12
+	vsuxseg8ei64.v v4, (a0), v12
+
+	vlseg2e8ff.v v4, (a0)
+	vlseg3e8ff.v v4, (a0)
+	vlseg4e8ff.v v4, (a0)
+	vlseg5e8ff.v v4, (a0)
+	vlseg6e8ff.v v4, (a0)
+	vlseg7e8ff.v v4, (a0)
+	vlseg8e8ff.v v4, (a0)
+	vlseg2e16ff.v v4, (a0)
+	vlseg3e16ff.v v4, (a0)
+	vlseg4e16ff.v v4, (a0)
+	vlseg5e16ff.v v4, (a0)
+	vlseg6e16ff.v v4, (a0)
+	vlseg7e16ff.v v4, (a0)
+	vlseg8e16ff.v v4, (a0)
+	vlseg2e32ff.v v4, (a0)
+	vlseg3e32ff.v v4, (a0)
+	vlseg4e32ff.v v4, (a0)
+	vlseg5e32ff.v v4, (a0)
+	vlseg6e32ff.v v4, (a0)
+	vlseg7e32ff.v v4, (a0)
+	vlseg8e32ff.v v4, (a0)
+	vlseg2e64ff.v v4, (a0)
+	vlseg3e64ff.v v4, (a0)
+	vlseg4e64ff.v v4, (a0)
+	vlseg5e64ff.v v4, (a0)
+	vlseg6e64ff.v v4, (a0)
+	vlseg7e64ff.v v4, (a0)
+	vlseg8e64ff.v v4, (a0)
+
+	vl1r.v v3, (a0)
+	vl1re8.v v3, (a0)
+	vl1re16.v v3, (a0)
+	vl1re32.v v3, (a0)
+	vl1re64.v v3, (a0)
+	vl2r.v v2, (a0)
+	vl2re8.v v2, (a0)
+	vl2re16.v v2, (a0)
+	vl2re32.v v2, (a0)
+	vl2re64.v v2, (a0)
+	vl4r.v v4, (a0)
+	vl4re8.v v4, (a0)
+	vl4re16.v v4, (a0)
+	vl4re32.v v4, (a0)
+	vl4re64.v v4, (a0)
+	vl8r.v v8, (a0)
+	vl8re8.v v8, (a0)
+	vl8re16.v v8, (a0)
+	vl8re32.v v8, (a0)
+	vl8re64.v v8, (a0)
+
+	vs1r.v v3, (a1)
+	vs2r.v v2, (a1)
+	vs4r.v v4, (a1)
+	vs8r.v v8, (a1)
+
+	vamoaddei8.v v4, (a1), v8, v4
+	vamoswapei8.v v4, (a1), v8, v4
+	vamoxorei8.v v4, (a1), v8, v4
+	vamoandei8.v v4, (a1), v8, v4
+	vamoorei8.v v4, (a1), v8, v4
+	vamominei8.v v4, (a1), v8, v4
+	vamomaxei8.v v4, (a1), v8, v4
+	vamominuei8.v v4, (a1), v8, v4
+	vamomaxuei8.v v4, (a1), v8, v4
+	vamoaddei8.v v4, 0(a1), v8, v4
+	vamoswapei8.v v4, 0(a1), v8, v4
+	vamoxorei8.v v4, 0(a1), v8, v4
+	vamoandei8.v v4, 0(a1), v8, v4
+	vamoorei8.v v4, 0(a1), v8, v4
+	vamominei8.v v4, 0(a1), v8, v4
+	vamomaxei8.v v4, 0(a1), v8, v4
+	vamominuei8.v v4, 0(a1), v8, v4
+	vamomaxuei8.v v4, 0(a1), v8, v4
+
+	vamoaddei16.v v4, (a1), v8, v4
+	vamoswapei16.v v4, (a1), v8, v4
+	vamoxorei16.v v4, (a1), v8, v4
+	vamoandei16.v v4, (a1), v8, v4
+	vamoorei16.v v4, (a1), v8, v4
+	vamominei16.v v4, (a1), v8, v4
+	vamomaxei16.v v4, (a1), v8, v4
+	vamominuei16.v v4, (a1), v8, v4
+	vamomaxuei16.v v4, (a1), v8, v4
+	vamoaddei16.v v4, 0(a1), v8, v4
+	vamoswapei16.v v4, 0(a1), v8, v4
+	vamoxorei16.v v4, 0(a1), v8, v4
+	vamoandei16.v v4, 0(a1), v8, v4
+	vamoorei16.v v4, 0(a1), v8, v4
+	vamominei16.v v4, 0(a1), v8, v4
+	vamomaxei16.v v4, 0(a1), v8, v4
+	vamominuei16.v v4, 0(a1), v8, v4
+	vamomaxuei16.v v4, 0(a1), v8, v4
+
+	vamoaddei32.v v4, (a1), v8, v4
+	vamoswapei32.v v4, (a1), v8, v4
+	vamoxorei32.v v4, (a1), v8, v4
+	vamoandei32.v v4, (a1), v8, v4
+	vamoorei32.v v4, (a1), v8, v4
+	vamominei32.v v4, (a1), v8, v4
+	vamomaxei32.v v4, (a1), v8, v4
+	vamominuei32.v v4, (a1), v8, v4
+	vamomaxuei32.v v4, (a1), v8, v4
+	vamoaddei32.v v4, 0(a1), v8, v4
+	vamoswapei32.v v4, 0(a1), v8, v4
+	vamoxorei32.v v4, 0(a1), v8, v4
+	vamoandei32.v v4, 0(a1), v8, v4
+	vamoorei32.v v4, 0(a1), v8, v4
+	vamominei32.v v4, 0(a1), v8, v4
+	vamomaxei32.v v4, 0(a1), v8, v4
+	vamominuei32.v v4, 0(a1), v8, v4
+	vamomaxuei32.v v4, 0(a1), v8, v4
+
+	vamoaddei64.v v4, (a1), v8, v4
+	vamoswapei64.v v4, (a1), v8, v4
+	vamoxorei64.v v4, (a1), v8, v4
+	vamoandei64.v v4, (a1), v8, v4
+	vamoorei64.v v4, (a1), v8, v4
+	vamominei64.v v4, (a1), v8, v4
+	vamomaxei64.v v4, (a1), v8, v4
+	vamominuei64.v v4, (a1), v8, v4
+	vamomaxuei64.v v4, (a1), v8, v4
+	vamoaddei64.v v4, 0(a1), v8, v4
+	vamoswapei64.v v4, 0(a1), v8, v4
+	vamoxorei64.v v4, 0(a1), v8, v4
+	vamoandei64.v v4, 0(a1), v8, v4
+	vamoorei64.v v4, 0(a1), v8, v4
+	vamominei64.v v4, 0(a1), v8, v4
+	vamomaxei64.v v4, 0(a1), v8, v4
+	vamominuei64.v v4, 0(a1), v8, v4
+	vamomaxuei64.v v4, 0(a1), v8, v4
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.d
new file mode 100644
index 0000000..16884e7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_zvl65536b
+#source: ../empty.s
+#error_output: vector-insns-fail-zvl.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.l
new file mode 100644
index 0000000..d820ded
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvl.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*Error: zvl\*b extensions need to enable either `v' or `zve' extension
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.d b/gas/testsuite/gas/riscv/extended/vector-insns.d
index 4e0ffff..3f9b9a1 100644
--- a/gas/testsuite/gas/riscv/extended/vector-insns.d
+++ b/gas/testsuite/gas/riscv/extended/vector-insns.d
@@ -1,4 +1,4 @@
-#as: -march=rv32iafv_zvamo
+#as: -march=rv32ifv_zvamo
 #objdump: -dr
 
 .*:[ 	]+file format .*