RISC-V/rvv: Add rvv v0.10 instructions.

2021-03-30  Jim Wilson  <jimw@sifive.com>
            Kito Cheng  <kito.cheng@sifive.com>
            Nelson Chu  <nelson.chu@sifive.com>

This patch is porting from the following riscv github,
https://github.com/riscv/riscv-binutils-gdb/tree/rvv-1.0.x

And here is the vector draft spec,
https://github.com/riscv/riscv-v-spec

The match_func in opcodes/riscv-opc.c have many purposes.  One of them is
checking the instruction constraints.  But we got the request before that
the assembler constraint checkings break some hardware exception testcases,
which are written by assmebly code.  Therefore, we add new assembler options
and .option directives to let users can disable/enable the rvv constraints.
For now the constraints are disabled by default, but should we default
enable them for safety?  Besides, the match_func will return different
error constriant messages, so that we can report the details to users.
This should be more user-friendly.

bfd/
	* elfxx-riscv.c (riscv_supported_std_ext): Updated the draft
	version of v.
	(riscv_supported_std_z_ext): Added draft zvamo and zvlsseg.
gas/
	* config/tc-riscv.c (enum DRAFT_EXT): Added.
	(enum riscv_extended_csr_class): Added CSR_CLASS_V for rvv CSRs.
	(enum reg_extended_class): Added vector registers.
	(op_draft_hash): Added draft hash table for rvv.
	(md_begin): Init op_draft_hash and register hash for rvv.
	(riscv_extended_subset_supports): Handle INSN_CLASS_V*.
	(riscv_extended_csr_class_check): Handle CSR_CLASS_V.
	(validate_riscv_extended_insn): Check if the rvv instructions are valid.
	(riscv_find_extended_opcode_hash): Search instruction opcode from
	op_draft_hash.
	(vector_macro): Call macro_build to expand rvv macros into instructions.
	(extended_macro_build): Handle rvv operands for macro_build.
	(extended_macro): Handle M_VMSGE and M_VMSGEU.
	(my_getVsetvliExpression): Similar to my_getVsetvliExpression, but used
	for parsing vsetvli operands.
	(riscv_parse_extended_operands): Handle rvv operands.  Pass &regno from
	riscv_ip, otherwise we will get fail when parsing Vf operand for AMO VS3.
	(riscv_ip): Add two new arguments to match_func, check_constraints and
	&error.  We can disbale the match_func check by setting check_constraints
	to zero; The part of match_func will set different error messages to the
	&error, and them we can report more details to users.
	(riscv_set_options, riscv_opts, s_riscv_option):  Add .option
	checkconstraints and nocheckconstraints, to enable/disable the
	match_func constraints checking.  Disable it by default.
	(enum options, md_longopts, md_parse_option): Add assembler options
	m[no-]check-constraints.
	* testsuite/gas/riscv/extended/extended.exp: Updated.
	* testsuite/gas/riscv/extended/extended-csr.d: New testcase for rvv CSRs.
	* testsuite/gas/riscv/extended/extended-csr.s: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.d:
	New testcase for rvv constriants.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.l: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.s: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-int.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-int.l: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-int.s: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.l: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.s: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.l: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.s: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-load-store.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-load-store.l: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-load-store.s: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-mask.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-mask.l: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-mask.s: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-permutation.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-permutation.l: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-permutation.s: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zvamo.l: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-fail-zvamo.s: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-vmsgtvx.s: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-zero-imm.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns-zero-imm.s: Likewise.
	* testsuite/gas/riscv/extended/vector-insns.d: Likewise.
	* testsuite/gas/riscv/extended/vector-insns.s: Likewise.
include/
	* opcode/riscv-opc-extended.h: Added rvv encoding macros and CSRs.
	* opcode/riscv.h: Added rvv immediate encodings and fields.
	(struct riscv_opcode): Updated match_func.
	(enum riscv_extended_insn_class): Added INSN_CLASS_V*.
	(enum M_VMSGE, M_VMSGEU): Added.
opcodes/
	* riscv-dis.c (print_extended_insn_args): Handle rvv operands.
	(riscv_disassemble_opcode): Updated match_func.
	* riscv-opc.c (match_*): Updated since two new parameters.
	(riscv_vecr_names_numeric): Added rvv register names.
	(riscv_vecm_names_numeric): Added rvv mask register name.
	(riscv_vsew, riscv_vlmul, riscv_vta, riscv_vma): Added for vsetvli.
	(MASK_VD, MASK_VS1, MASK_VS2, MASK_VMASK): Added for rvv match_func.
	(match_vs1_eq_vs2, match_vs1_eq_vs2_neq_vm, match_vd_eq_vs1_eq_vs2):
	Added to check special register usage, cannot be disabled.
	(match_widen_vd_neq_vs1_neq_vs2_neq_vm): The rvv constraint check,
	can be disabled/enabled by m[no-]check-constraints or .option
	[no]checkconstraints.
	(match_widen_vd_neq_vs1_neq_vm): Likewise.
	(match_widen_vd_neq_vs2_neq_vm): Likewise.
	(match_widen_vd_neq_vm): Likewise.
	(match_narrow_vd_neq_vs2_neq_vm): Likewise.
	(match_vd_neq_vs1_neq_vs2): Likewise.
	(match_vd_neq_vs1_neq_vs2_neq_vm): Likewise.
	(match_vd_neq_vs2_neq_vm): Likewise.
	(match_vd_neq_vm): Likewise.
	(match_vls_nf_rv): Likewise.
	(match_vmv_nf_rv): Likewise.
	(riscv_draft_opcodes): Added rvv v0.10 instructions.
	(riscv_extended_opcodes): Updated.

37 files changed, 7385 insertions, 7 deletions

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index cafdda4..6ddb710 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -38,7 +38,8 @@
 /* Used to choose the right opcode hashes for extended extensions.  */
 enum
 {
-  EXTENDED_EXT_NUM = 0
+  DRAFT_EXT = 0,
+  EXTENDED_EXT_NUM
 };
 
 /* Information about an instruction, including its format, operands
@@ -73,6 +74,12 @@ enum riscv_csr_class
   CSR_CLASS_EXTENDED /* Extended CSR  */
 };
 
+/* All RISC-V extended CSR belong to one of these classes.  */
+enum riscv_extended_csr_class
+{
+  CSR_CLASS_V = CSR_CLASS_EXTENDED, /* RVV CSR */
+};
+
 /* This structure holds all restricted conditions for a CSR.  */
 struct riscv_csr_extra
 {
@@ -214,6 +221,7 @@ struct riscv_set_options
   int relax; /* Emit relocs the linker is allowed to relax.  */
   int arch_attr; /* Emit architecture and privileged elf attributes.  */
   int csr_check; /* Enable the CSR checking.  */
+  int check_constraints; /* Enable/disable the match_func checking.  */
 };
 
 static struct riscv_set_options riscv_opts =
@@ -224,6 +232,7 @@ static struct riscv_set_options riscv_opts =
   1, /* relax */
   DEFAULT_RISCV_ATTR, /* arch_attr */
   0, /* csr_check */
+  0, /* check_constraints */
 };
 
 static void
@@ -262,6 +271,16 @@ riscv_extended_subset_supports (int insn_class)
 {
   switch (insn_class)
     {
+    case INSN_CLASS_V: return riscv_subset_supports ("v");
+    case INSN_CLASS_V_AND_F:
+      return riscv_subset_supports ("v") && riscv_subset_supports ("f");
+    case INSN_CLASS_V_OR_ZVAMO:
+      return (riscv_subset_supports ("a")
+	      && (riscv_subset_supports ("v")
+		  || riscv_subset_supports ("zvamo")));
+    case INSN_CLASS_V_OR_ZVLSSEG:
+      return (riscv_subset_supports ("v")
+	      || riscv_subset_supports ("zvlsseg"));
     default:
       as_fatal ("internal: unknown INSN_CLASS (0x%x)", insn_class);
       return false;
@@ -407,6 +426,9 @@ riscv_set_abi_by_arch (void)
 /* Handle of the OPCODE hash table.  */
 static htab_t op_hash = NULL;
 
+/* Handle of the draft OPCODE hash table.  */
+static htab_t op_draft_hash = NULL;
+
 /* Handle of the type of .insn hash table.  */
 static htab_t insn_type_hash = NULL;
 
@@ -848,6 +870,8 @@ opcode_name_lookup (char **s)
 /* Extended registers.  */
 enum reg_extended_class
 {
+  RCLASS_VECR,
+  RCLASS_VECM,
   RCLASS_EXTENDED_NUM,
 };
 
@@ -934,6 +958,10 @@ riscv_extended_csr_class_check (int csr_class)
 {
   switch (csr_class)
     {
+    case CSR_CLASS_V:
+      return (riscv_subset_supports ("v")
+	      || riscv_subset_supports ("zvamo")
+	      || riscv_subset_supports ("zvlsseg"));
     default:
       as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
     }
@@ -1102,6 +1130,30 @@ validate_riscv_extended_insn (insn_t *bits,
 
   switch (*oparg)
     {
+    case 'V': /* RVV */
+      switch (*++oparg)
+	{
+	case 'd':
+	case 'f': USE_BITS (OP_MASK_VD, OP_SH_VD); break;
+	case 'e': USE_BITS (OP_MASK_VWD, OP_SH_VWD); break;
+	case 's': USE_BITS (OP_MASK_VS1, OP_SH_VS1); break;
+	case 't': USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
+	case 'u': USE_BITS (OP_MASK_VS1, OP_SH_VS1);
+		  USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
+	case 'v': USE_BITS (OP_MASK_VD, OP_SH_VD);
+		  USE_BITS (OP_MASK_VS1, OP_SH_VS1);
+		  USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
+	case '0': break;
+	case 'b': used_bits |= ENCODE_RVV_VB_IMM (-1U); break;
+	case 'c': used_bits |= ENCODE_RVV_VC_IMM (-1U); break;
+	case 'i':
+	case 'j':
+	case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break;
+	case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break;
+	default:
+	  return false;
+	}
+      break;
     default:
       return false;
     }
@@ -1350,6 +1402,11 @@ md_begin (void)
 
   /* Set the default alignment for the text section.  */
   record_alignment (text_section, riscv_opts.rvc ? 1 : 2);
+
+  /* Extended settings.  */
+  hash_reg_names (RCLASS_VECR, riscv_vecr_names_numeric, NVECR);
+  hash_reg_names (RCLASS_VECM, riscv_vecm_names_numeric, NVECM);
+  op_draft_hash = init_opcode_hash (riscv_extended_opcodes[DRAFT_EXT], false);
 }
 
 static insn_t
@@ -1455,6 +1512,9 @@ riscv_find_extended_opcode_hash (char *str ATTRIBUTE_UNUSED)
 
       switch (i)
 	{
+	case DRAFT_EXT:
+	  insn = (struct riscv_opcode *) str_hash_find (op_draft_hash, str);
+	  break;
 	default:
 	  break;
 	}
@@ -1483,13 +1543,45 @@ riscv_find_opcode_hash (char *str, htab_t hash)
 static bool
 extended_macro_build (struct riscv_cl_insn* insn_p,
 		      const char **fmt_p,
-		      va_list args ATTRIBUTE_UNUSED)
+		      va_list args)
 {
   struct riscv_cl_insn insn = *insn_p;
   const char *fmt = *fmt_p;
 
   switch (*fmt)
     {
+    case 'V': /* RVV */
+      switch (*++fmt)
+	{
+	case 'd':
+	  INSERT_OPERAND (VD, insn, va_arg (args, int));
+	  break;
+
+	case 's':
+	  INSERT_OPERAND (VS1, insn, va_arg (args, int));
+	  break;
+
+	case 't':
+	  INSERT_OPERAND (VS2, insn, va_arg (args, int));
+	  break;
+
+	case 'm':
+	  {
+	    int reg = va_arg (args, int);
+	    if (reg == -1)
+	      INSERT_OPERAND (VMASK, insn, 1);
+	    else if (reg == 0)
+	      INSERT_OPERAND (VMASK, insn, 0);
+	    else
+	      return false;
+	  }
+	  break;
+
+	default:
+	  return false;
+	}
+      break;
+
     default:
       return false;
     }
@@ -1746,16 +1838,110 @@ riscv_ext (int destreg, int srcreg, unsigned shift, bool sign)
     }
 }
 
+/* Expand RISC-V Vector macros into one or more instructions.  */
+
+static void
+vector_macro (struct riscv_cl_insn *ip)
+{
+  int vd = (ip->insn_opcode >> OP_SH_VD) & OP_MASK_VD;
+  int vs1 = (ip->insn_opcode >> OP_SH_VS1) & OP_MASK_VS1;
+  int vs2 = (ip->insn_opcode >> OP_SH_VS2) & OP_MASK_VS2;
+  int vm = (ip->insn_opcode >> OP_SH_VMASK) & OP_MASK_VMASK;
+  int vtemp = (ip->insn_opcode >> OP_SH_VFUNCT6) & OP_MASK_VFUNCT6;
+  int mask = ip->insn_mo->mask;
+
+  switch (mask)
+    {
+    case M_VMSGE:
+      if (vm)
+	{
+	  /* Unmasked.  */
+	  macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1);
+	  macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd);
+	  break;
+	}
+      if (vtemp != 0)
+	{
+	  /* Masked.  Have vtemp to avoid overlap constraints.  */
+	  if (vd == vm)
+	    {
+	      macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1);
+	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
+	    }
+	  else
+	    {
+	      /* Preserve the value of vd if not updating by vm.  */
+	      macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1);
+	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp);
+	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm);
+	      macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd);
+	    }
+	}
+      else if (vd != vm)
+	{
+	  /* Masked.  This may cause the vd overlaps vs2, when LMUL > 1.  */
+	  macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm);
+	  macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm);
+	}
+      else
+	as_bad (_("must provide temp if destination overlaps mask"));
+      break;
+
+    case M_VMSGEU:
+      if (vm)
+	{
+	  /* Unmasked.  */
+	  macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1);
+	  macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd);
+	  break;
+	}
+      if (vtemp != 0)
+	{
+	  /* Masked.  Have vtemp to avoid overlap constraints.  */
+	  if (vd == vm)
+	    {
+	      macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1);
+	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp);
+	    }
+	  else
+	    {
+	      /* Preserve the value of vd if not updating by vm.  */
+	      macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1);
+	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp);
+	      macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm);
+	      macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd);
+	    }
+	}
+      else if (vd != vm)
+	{
+	  /* Masked.  This may cause the vd overlaps vs2, when LMUL > 1.  */
+	  macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm);
+	  macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm);
+	}
+      else
+	as_bad (_("must provide temp if destination overlaps mask"));
+      break;
+
+    default:
+      break;
+    }
+}
+
 /* Expand RISC-V extended assembly macros into one or more instructions.  */
 
 static bool
-extended_macro (struct riscv_cl_insn *ip ATTRIBUTE_UNUSED,
+extended_macro (struct riscv_cl_insn *ip,
 		int mask,
 		expressionS *imm_expr ATTRIBUTE_UNUSED,
 		bfd_reloc_code_real_type *imm_reloc ATTRIBUTE_UNUSED)
 {
   switch (mask)
     {
+    case M_VMSGE:
+    case M_VMSGEU:
+      vector_macro (ip);
+      break;
+
     default:
       return false;
     }
@@ -2165,6 +2351,66 @@ riscv_is_priv_insn (insn_t insn)
 	  || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0);
 }
 
+/* Parse string STR as a vsetvli operand.  Store the expression in *EP.
+   On exit, EXPR_END points to the first character after the expression.  */
+
+static void
+my_getVsetvliExpression (expressionS *ep, char *str)
+{
+  unsigned int vsew_value = 0, vlmul_value = 0;
+  unsigned int vta_value = 0, vma_value = 0;
+  bool vsew_found = false, vlmul_found = false;
+  bool vta_found = false, vma_found = false;
+
+  if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value))
+    {
+      if (*str == ',')
+	++str;
+      if (vsew_found)
+	as_bad (_("multiple vsew constants"));
+      vsew_found = true;
+    }
+  if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value))
+    {
+      if (*str == ',')
+	++str;
+      if (vlmul_found)
+	as_bad (_("multiple vlmul constants"));
+      vlmul_found = true;
+    }
+  if (arg_lookup (&str, riscv_vta, ARRAY_SIZE (riscv_vta), &vta_value))
+    {
+      if (*str == ',')
+	++str;
+      if (vta_found)
+	as_bad (_("multiple vta constants"));
+      vta_found = true;
+    }
+  if (arg_lookup (&str, riscv_vma, ARRAY_SIZE (riscv_vma), &vma_value))
+    {
+      if (*str == ',')
+	++str;
+      if (vma_found)
+	as_bad (_("multiple vma constants"));
+      vma_found = true;
+    }
+
+  if (vsew_found || vlmul_found || vta_found || vma_found)
+    {
+      ep->X_op = O_constant;
+      ep->X_add_number = (vlmul_value << OP_SH_VLMUL)
+			  | (vsew_value << OP_SH_VSEW)
+			  | (vta_value << OP_SH_VTA)
+			  | (vma_value << OP_SH_VMA);
+      expr_end = str;
+    }
+  else
+    {
+      my_getExpression (ep, str);
+      str = expr_end;
+    }
+}
+
 /* Parse all extended operands for riscv_ip.  */
 
 static bool
@@ -2172,13 +2418,192 @@ riscv_parse_extended_operands (struct riscv_cl_insn *ip ATTRIBUTE_UNUSED,
 			       expressionS *imm_expr ATTRIBUTE_UNUSED,
 			       bfd_reloc_code_real_type *imm_reloc ATTRIBUTE_UNUSED,
 			       const char **opcode_args,
-			       char **assembly_args)
+			       char **assembly_args,
+			       unsigned int *regno_p)
 {
   const char *oparg = *opcode_args;
   char *asarg = *assembly_args;
+  unsigned int regno = *regno_p;
 
   switch (*oparg)
     {
+    case 'V': /* RVV */
+      switch (*++oparg)
+	{
+	case 'd': /* VD */
+	  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
+	    return false;
+	  INSERT_OPERAND (VD, *ip, regno);
+	  break;
+
+	case 'e': /* AMO VD */
+	  if (reg_lookup (&asarg, RCLASS_GPR, &regno) && regno == 0)
+	    INSERT_OPERAND (VWD, *ip, 0);
+	  else if (reg_lookup (&asarg, RCLASS_VECR, &regno))
+	    {
+	      INSERT_OPERAND (VWD, *ip, 1);
+	      INSERT_OPERAND (VD, *ip, regno);
+	    }
+	  else
+	    return false;
+	  break;
+
+	case 'f': /* AMO VS3 */
+	  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
+	    return false;
+	  if (!EXTRACT_OPERAND (VWD, ip->insn_opcode))
+	    INSERT_OPERAND (VD, *ip, regno);
+	  else
+	    {
+	      /* VS3 must match VD.  */
+	      if (EXTRACT_OPERAND (VD, ip->insn_opcode) != regno)
+		return false;
+	    }
+	  break;
+
+	case 's': /* VS1 */
+	  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
+	    return false;
+	  INSERT_OPERAND (VS1, *ip, regno);
+	  break;
+
+	case 't': /* VS2 */
+	  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
+	    return false;
+	  INSERT_OPERAND (VS2, *ip, regno);
+	  break;
+
+	case 'u': /* VS1 == VS2 */
+	  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
+	    return false;
+	  INSERT_OPERAND (VS1, *ip, regno);
+	  INSERT_OPERAND (VS2, *ip, regno);
+	  break;
+
+	case 'v': /* VD == VS1 == VS2 */
+	  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
+	    return false;
+	  INSERT_OPERAND (VD, *ip, regno);
+	  INSERT_OPERAND (VS1, *ip, regno);
+	  INSERT_OPERAND (VS2, *ip, regno);
+	  break;
+
+	/* The `V0` is carry-in register for v[m]adc and v[m]sbc,
+	   and is used to choose vs1/rs1/frs1/imm or vs2 for
+	   v[f]merge.  It uses the same encoding as the vector mask
+	   register.  */
+	case '0':
+	  if (!reg_lookup (&asarg, RCLASS_VECR, &regno) || regno != 0)
+	    return false;
+	  break;
+
+	case 'b': /* vtypei for vsetivli */
+	  my_getVsetvliExpression (imm_expr, asarg);
+	  check_absolute_expr (ip, imm_expr, false);
+	  if (!VALID_RVV_VB_IMM (imm_expr->X_add_number))
+	    {
+	      as_bad (_("bad value for vsetivli immediate field, "
+			"value must be 0..1023"));
+	      return false;
+	    }
+	  ip->insn_opcode
+	    |= ENCODE_RVV_VB_IMM (imm_expr->X_add_number);
+	  imm_expr->X_op = O_absent;
+	  asarg = expr_end;
+	  break;
+
+	case 'c': /* vtypei for vsetvli */
+	  my_getVsetvliExpression (imm_expr, asarg);
+	  check_absolute_expr (ip, imm_expr, false);
+	  if (!VALID_RVV_VC_IMM (imm_expr->X_add_number))
+	    {
+	      as_bad (_("bad value for vsetvli immediate field, "
+			"value must be 0..2047"));
+	      return false;
+	    }
+	  ip->insn_opcode
+	    |= ENCODE_RVV_VC_IMM (imm_expr->X_add_number);
+	  imm_expr->X_op = O_absent;
+	  asarg = expr_end;
+	  break;
+
+	case 'i': /* vector arith signed immediate */
+	  my_getExpression (imm_expr, asarg);
+	  check_absolute_expr (ip, imm_expr, false);
+	  if (imm_expr->X_add_number > 15
+	      || imm_expr->X_add_number < -16)
+	    {
+	      as_bad (_("bad value for vector immediate field, "
+			"value must be -16...15"));
+	      return false;
+	    }
+	  INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number);
+	  imm_expr->X_op = O_absent;
+	  asarg = expr_end;
+	  break;
+
+	case 'j': /* vector arith unsigned immediate */
+	  my_getExpression (imm_expr, asarg);
+	  check_absolute_expr (ip, imm_expr, false);
+	  if (imm_expr->X_add_number < 0
+	      || imm_expr->X_add_number >= 32)
+	    {
+	      as_bad (_("bad value for vector immediate field, "
+			"value must be 0...31"));
+	      return false;
+	    }
+	  INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number);
+	  imm_expr->X_op = O_absent;
+	  asarg = expr_end;
+	  break;
+
+	case 'k': /* vector arith signed immediate, minus 1 */
+	  my_getExpression (imm_expr, asarg);
+	  check_absolute_expr (ip, imm_expr, false);
+	  if (imm_expr->X_add_number > 16
+	      || imm_expr->X_add_number < -15)
+	    {
+	      as_bad (_("bad value for vector immediate field, "
+			"value must be -15...16"));
+	      return false;
+	    }
+	  INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number - 1);
+	  imm_expr->X_op = O_absent;
+	  asarg = expr_end;
+	  break;
+
+	case 'm': /* optional vector mask */
+	  if (*asarg == '\0')
+	    INSERT_OPERAND (VMASK, *ip, 1);
+	  else if (*asarg == ',' && asarg++
+		   && reg_lookup (&asarg, RCLASS_VECM, &regno)
+		   && regno == 0)
+	    INSERT_OPERAND (VMASK, *ip, 0);
+	  else
+	    return false;
+	  break;
+
+	/* The following ones are only used in macros.  */
+	case 'M': /* required vector mask */
+	  if (reg_lookup (&asarg, RCLASS_VECM, &regno) && regno == 0)
+	    INSERT_OPERAND (VMASK, *ip, 0);
+	  else
+	    return false;
+	  break;
+
+	case 'T': /* vector macro temporary register */
+	  if (!reg_lookup (&asarg, RCLASS_VECR, &regno) || regno == 0)
+	    return false;
+	  /* Store it in the FUNCT6 field as we don't have anyplace
+	     else to store it.  */
+	  INSERT_OPERAND (VFUNCT6, *ip, regno);
+	  break;
+
+	default:
+	  return false;
+	}
+      break;
+
     default:
       as_fatal (_("internal: unknown argument type `%s'"),
 		*opcode_args);
@@ -2186,6 +2611,7 @@ riscv_parse_extended_operands (struct riscv_cl_insn *ip ATTRIBUTE_UNUSED,
     }
 
   *opcode_args = oparg;
+  *regno_p = regno;
   *assembly_args = asarg;
   return true;
 }
@@ -2230,6 +2656,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
       if (!riscv_multi_subset_supports (insn->insn_class))
 	continue;
 
+      /* Reset error message of the previous round.  */
+      error = _("illegal operands");
       create_insn (ip, insn);
       argnum = 1;
 
@@ -2246,7 +2674,9 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	    case '\0': /* End of args.  */
 	      if (insn->pinfo != INSN_MACRO)
 		{
-		  if (!insn->match_func (insn, ip->insn_opcode))
+		  if (!insn->match_func (insn, ip->insn_opcode,
+					 riscv_opts.check_constraints,
+					 &error))
 		    break;
 
 		  /* For .insn, insn->match and insn->mask are 0.  */
@@ -2943,13 +3373,12 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 	      parse_extended_operand:
 		oparg = opargStart;
 		if (riscv_parse_extended_operands (ip, imm_expr, imm_reloc,
-						   &oparg, &asarg))
+						   &oparg, &asarg, &regno))
 		  continue;
 	    }
 	  break;
 	}
       asarg = asargStart;
-      error = _("illegal operands");
       insn_with_csr = false;
     }
 
@@ -3073,6 +3502,8 @@ enum options
   OPTION_MPRIV_SPEC,
   OPTION_BIG_ENDIAN,
   OPTION_LITTLE_ENDIAN,
+  OPTION_CHECK_CONSTRAINTS,
+  OPTION_NO_CHECK_CONSTRAINTS,
   OPTION_END_OF_ENUM
 };
 
@@ -3093,6 +3524,8 @@ struct option md_longopts[] =
   {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC},
   {"mbig-endian", no_argument, NULL, OPTION_BIG_ENDIAN},
   {"mlittle-endian", no_argument, NULL, OPTION_LITTLE_ENDIAN},
+  {"mcheck-constraints", no_argument, NULL, OPTION_CHECK_CONSTRAINTS},
+  {"mno-check-constraints", no_argument, NULL, OPTION_NO_CHECK_CONSTRAINTS},
 
   {NULL, no_argument, NULL, 0}
 };
@@ -3177,6 +3610,14 @@ md_parse_option (int c, const char *arg)
       target_big_endian = 0;
       break;
 
+    case OPTION_CHECK_CONSTRAINTS:
+      riscv_opts.check_constraints = true;
+      break;
+
+    case OPTION_NO_CHECK_CONSTRAINTS:
+      riscv_opts.check_constraints = false;
+      break;
+
     default:
       return 0;
     }
@@ -3549,6 +3990,10 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
     riscv_opts.csr_check = true;
   else if (strcmp (name, "no-csr-check") == 0)
     riscv_opts.csr_check = false;
+  else if (strcmp (name, "checkconstraints") == 0)
+    riscv_opts.check_constraints = true;
+  else if (strcmp (name, "nocheckconstraints") == 0)
+    riscv_opts.check_constraints = false;
   else if (strcmp (name, "push") == 0)
     {
       struct riscv_option_stack *s;
diff --git a/gas/testsuite/gas/riscv/extended/extended-csr.d b/gas/testsuite/gas/riscv/extended/extended-csr.d
new file mode 100644
index 0000000..bfe102b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/extended-csr.d
@@ -0,0 +1,16 @@
+#as: -march=rv32iv
+#objdump: -d
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[     	]+[0-9a-f]+:[  	]+00802573[    	]+csrr[     	]+a0,vstart
+[     	]+[0-9a-f]+:[  	]+00902573[    	]+csrr[        	]+a0,vxsat
+[     	]+[0-9a-f]+:[  	]+00a02573[    	]+csrr[       	]+a0,vxrm
+[     	]+[0-9a-f]+:[  	]+00f02573[    	]+csrr[     	]+a0,vcsr
+[     	]+[0-9a-f]+:[  	]+c2002573[    	]+csrr[        	]+a0,vl
+[     	]+[0-9a-f]+:[  	]+c2102573[    	]+csrr[       	]+a0,vtype
+[     	]+[0-9a-f]+:[  	]+c2202573[    	]+csrr[       	]+a0,vlenb
diff --git a/gas/testsuite/gas/riscv/extended/extended-csr.s b/gas/testsuite/gas/riscv/extended/extended-csr.s
new file mode 100644
index 0000000..5826c12
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/extended-csr.s
@@ -0,0 +1,12 @@
+	.macro csr val
+	csrr a0,\val
+	.endm
+
+	# Vector
+	csr vstart
+	csr vxsat
+	csr vxrm
+	csr vcsr
+	csr vl
+	csr vtype
+	csr vlenb
diff --git a/gas/testsuite/gas/riscv/extended/extended.exp b/gas/testsuite/gas/riscv/extended/extended.exp
index 8767c84..3966ef8 100644
--- a/gas/testsuite/gas/riscv/extended/extended.exp
+++ b/gas/testsuite/gas/riscv/extended/extended.exp
@@ -19,4 +19,18 @@
 # MA 02110-1301, USA.
 
 if [istarget riscv*-*-*] {
+    run_dump_tests "vector-insns"
+    run_dump_tests "vector-insns-vmsgtvx"
+    run_dump_tests "vector-insns-zero-imm"
+    run_dump_tests "vector-insns-fail-arith-fixp"
+    run_dump_tests "vector-insns-fail-arith-floatp"
+    run_dump_tests "vector-insns-fail-arith-int"
+    run_dump_tests "vector-insns-fail-arith-narrow"
+    run_dump_tests "vector-insns-fail-arith-widen"
+    run_dump_tests "vector-insns-fail-load-store"
+    run_dump_tests "vector-insns-fail-mask"
+    run_dump_tests "vector-insns-fail-permutation"
+    run_dump_tests "vector-insns-fail-zvamo"
+
+    run_dump_tests "extended-csr"
 }
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.d
new file mode 100644
index 0000000..df48418
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.d
@@ -0,0 +1,3 @@
+#as: -march=rv32iv -mcheck-constraints
+#source: vector-insns-fail-arith-fixp.s
+#error_output: vector-insns-fail-arith-fixp.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.l
new file mode 100644
index 0000000..3481174
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.l
@@ -0,0 +1,27 @@
+.*: Assembler messages:
+.*Error: illegal operands vd cannot overlap vm `vsaddu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsaddu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsaddu.vi v0,v4,15,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsadd.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsadd.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsadd.vi v0,v4,15,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssubu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssubu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssub.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssub.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vaaddu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vaaddu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vaadd.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vaadd.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vasubu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vasubu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vasub.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vasub.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsmul.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsmul.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssrl.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssrl.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssrl.vi v0,v4,31,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssra.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssra.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssra.vi v0,v4,31,v0.t'
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.s b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.s
new file mode 100644
index 0000000..1fbcb60
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-fixp.s
@@ -0,0 +1,81 @@
+# Vector Single-Width Saturating Add and Subtract
+
+	vsaddu.vv v4, v4, v8		# OK
+	vsaddu.vv v8, v4, v8		# OK
+	vsaddu.vv v0, v4, v8, v0.t	# vd overlap vm
+	vsaddu.vx v4, v4, a1		# OK
+	vsaddu.vx v0, v4, a1, v0.t	# vd overlap vm
+	vsaddu.vi v4, v4, 15		# OK
+	vsaddu.vi v0, v4, 15, v0.t	# vd overlap vm
+
+	vsadd.vv v4, v4, v8
+	vsadd.vv v8, v4, v8
+	vsadd.vv v0, v4, v8, v0.t
+	vsadd.vx v4, v4, a1
+	vsadd.vx v0, v4, a1, v0.t
+	vsadd.vi v4, v4, 15
+	vsadd.vi v0, v4, 15, v0.t
+
+	vssubu.vv v4, v4, v8		# OK
+	vssubu.vv v8, v4, v8		# OK
+	vssubu.vv v0, v4, v8, v0.t	# vd overlap vm
+	vssubu.vx v4, v4, a1		# OK
+	vssubu.vx v0, v4, a1, v0.t	# vd overlap vm
+
+	vssub.vv v4, v4, v8
+	vssub.vv v8, v4, v8
+	vssub.vv v0, v4, v8, v0.t
+	vssub.vx v4, v4, a1
+	vssub.vx v0, v4, a1, v0.t
+
+# Vector Single-Width Averaging Add and Subtract
+
+	vaaddu.vv v4, v4, v8		# OK
+	vaaddu.vv v8, v4, v8		# OK
+	vaaddu.vv v0, v4, v8, v0.t	# vd overlap vm
+	vaaddu.vx v4, v4, a1		# OK
+	vaaddu.vx v0, v4, a1, v0.t	# vd overlap vm
+
+	vaadd.vv v4, v4, v8
+	vaadd.vv v8, v4, v8
+	vaadd.vv v0, v4, v8, v0.t
+	vaadd.vx v4, v4, a1
+	vaadd.vx v0, v4, a1, v0.t
+
+	vasubu.vv v4, v4, v8
+	vasubu.vv v8, v4, v8
+	vasubu.vv v0, v4, v8, v0.t
+	vasubu.vx v4, v4, a1
+	vasubu.vx v0, v4, a1, v0.t
+
+	vasub.vv v4, v4, v8
+	vasub.vv v8, v4, v8
+	vasub.vv v0, v4, v8, v0.t
+	vasub.vx v4, v4, a1
+	vasub.vx v0, v4, a1, v0.t
+
+# Vector Single-Width Fractional Multiply with Rounding and Saturation
+
+	vsmul.vv v4, v4, v8		# OK
+	vsmul.vv v8, v4, v8		# OK
+	vsmul.vv v0, v4, v8, v0.t	# vd overlap vm
+	vsmul.vx v4, v4, a1		# OK
+	vsmul.vx v0, v4, a1, v0.t	# vd overlap vm
+
+# Vector Single-Width Scaling Shift Instructions
+
+	vssrl.vv v4, v4, v8		# OK
+	vssrl.vv v8, v4, v8		# OK
+	vssrl.vv v0, v4, v8, v0.t	# vd overlap vm
+	vssrl.vx v4, v4, a1		# OK
+	vssrl.vx v0, v4, a1, v0.t	# vd overlap vm
+	vssrl.vi v4, v4, 31		# OK
+	vssrl.vi v0, v4, 31, v0.t	# vd overlap vm
+
+	vssra.vv v4, v4, v8
+	vssra.vv v8, v4, v8
+	vssra.vv v0, v4, v8, v0.t
+	vssra.vx v4, v4, a1
+	vssra.vx v0, v4, a1, v0.t
+	vssra.vi v4, v4, 31
+	vssra.vi v0, v4, 31, v0.t
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.d
new file mode 100644
index 0000000..796f7e2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.d
@@ -0,0 +1,3 @@
+#as: -march=rv32ifv -mcheck-constraints
+#source: vector-insns-fail-arith-floatp.s
+#error_output: vector-insns-fail-arith-floatp.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l
new file mode 100644
index 0000000..bcc49a0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.l
@@ -0,0 +1,48 @@
+.*: Assembler messages:
+.*Error: illegal operands vd cannot overlap vm `vfadd.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfadd.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsub.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsub.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfrsub.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmul.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmul.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfdiv.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfdiv.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfrdiv.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmacc.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmacc.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmacc.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmacc.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmsac.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmsac.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmsac.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmsac.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmadd.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmadd.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmadd.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmadd.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmsub.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmsub.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmsub.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfnmsub.vf v0,fa1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsqrt.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfrece7.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfrsqrte7.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfclass.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmin.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmin.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmax.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfmax.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfneg.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsgnj.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsgnj.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsgnjn.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsgnjn.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsgnjx.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfsgnjx.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfcvt.xu.f.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfcvt.x.f.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfcvt.rtz.xu.f.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfcvt.rtz.x.f.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfcvt.f.xu.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfcvt.f.x.v v0,v4,v0.t'
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s
new file mode 100644
index 0000000..a48b1a3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-floatp.s
@@ -0,0 +1,155 @@
+# Vector Single-Width Floating-Point Add/Subtract Instructions
+
+	vfadd.vv v4, v4, v8		# OK
+	vfadd.vv v8, v4, v8		# OK
+	vfadd.vv v0, v4, v8, v0.t	# vd overlap vm
+	vfadd.vf v4, v4, fa1		# OK
+	vfadd.vf v0, v4, fa1, v0.t	# vd overlap vm
+
+	vfsub.vv v4, v4, v8
+	vfsub.vv v8, v4, v8
+	vfsub.vv v0, v4, v8, v0.t
+	vfsub.vf v4, v4, fa1
+	vfsub.vf v0, v4, fa1, v0.t
+
+	vfrsub.vf v4, v4, fa1		# OK
+	vfrsub.vf v0, v4, fa1, v0.t	# vd overlap vm
+
+# Vector Single-Width Floating-Point Multiply/Divide Instructions
+
+	vfmul.vv v4, v4, v8		# OK
+	vfmul.vv v8, v4, v8		# OK
+	vfmul.vv v0, v4, v8, v0.t	# vd overlap vm
+	vfmul.vf v4, v4, fa1		# OK
+	vfmul.vf v0, v4, fa1, v0.t	# vd overlap vm
+
+	vfdiv.vv v4, v4, v8
+	vfdiv.vv v8, v4, v8
+	vfdiv.vv v0, v4, v8, v0.t
+	vfdiv.vf v4, v4, fa1
+	vfdiv.vf v0, v4, fa1, v0.t
+
+	vfrdiv.vf v4, v4, fa1		# OK
+	vfrdiv.vf v0, v4, fa1, v0.t	# vd overlap vm
+
+# Vector Single-Width Floating-Point Fused Multiply-Add Instructions
+
+	vfmacc.vv v4, v4, v8		# OK
+	vfmacc.vv v8, v4, v8		# OK
+	vfmacc.vv v0, v4, v8, v0.t	# vd overlap vm
+	vfmacc.vf v4, fa1, v4		# OK
+	vfmacc.vf v0, fa1, v4, v0.t	# vd overlap vm
+
+	vfnmacc.vv v4, v4, v8
+	vfnmacc.vv v8, v4, v8
+	vfnmacc.vv v0, v4, v8, v0.t
+	vfnmacc.vf v4, fa1, v4
+	vfnmacc.vf v0, fa1, v4, v0.t
+
+	vfmsac.vv v4, v4, v8
+	vfmsac.vv v8, v4, v8
+	vfmsac.vv v0, v4, v8, v0.t
+	vfmsac.vf v4, fa1, v4
+	vfmsac.vf v0, fa1, v4, v0.t
+
+	vfnmsac.vv v4, v4, v8
+	vfnmsac.vv v8, v4, v8
+	vfnmsac.vv v0, v4, v8, v0.t
+	vfnmsac.vf v4, fa1, v4
+	vfnmsac.vf v0, fa1, v4, v0.t
+
+	vfmadd.vv v4, v4, v8
+	vfmadd.vv v8, v4, v8
+	vfmadd.vv v0, v4, v8, v0.t
+	vfmadd.vf v4, fa1, v4
+	vfmadd.vf v0, fa1, v4, v0.t
+
+	vfnmadd.vv v4, v4, v8
+	vfnmadd.vv v8, v4, v8
+	vfnmadd.vv v0, v4, v8, v0.t
+	vfnmadd.vf v4, fa1, v4
+	vfnmadd.vf v0, fa1, v4, v0.t
+
+	vfmsub.vv v4, v4, v8
+	vfmsub.vv v8, v4, v8
+	vfmsub.vv v0, v4, v8, v0.t
+	vfmsub.vf v4, fa1, v4
+	vfmsub.vf v0, fa1, v4, v0.t
+
+	vfnmsub.vv v4, v4, v8
+	vfnmsub.vv v8, v4, v8
+	vfnmsub.vv v0, v4, v8, v0.t
+	vfnmsub.vf v4, fa1, v4
+	vfnmsub.vf v0, fa1, v4, v0.t
+
+# Vector Floating-Point Square-Root Instruction
+
+	vfsqrt.v v4, v4			# OK
+	vfsqrt.v v0, v4, v0.t		# vd overlap vm
+
+# Vector Floating-Point Reciprocal Estimate Instruction
+
+	vfrece7.v v4, v4		# OK
+	vfrece7.v v0, v4, v0.t		# vd overlap vm
+
+# Vector Floating-Point Reciprocal Square-Root Estimate Instruction
+
+	vfrsqrte7.v v4, v4		# OK
+	vfrsqrte7.v v0, v4, v0.t	# vd overlap vm
+
+# Vector Floating-Point Classify Instruction
+
+	vfclass.v v4, v4		# OK
+	vfclass.v v0, v4, v0.t		# vd overlap vm
+
+# Vector Floating-Point MIN/MAX Instructions
+
+	vfmin.vv v4, v4, v8		# OK
+	vfmin.vv v8, v4, v8		# OK
+	vfmin.vv v0, v4, v8, v0.t	# vd overlap vm
+	vfmin.vf v4, v4, fa1		# OK
+	vfmin.vf v0, v4, fa1, v0.t	# vd overlap vm
+
+	vfmax.vv v4, v4, v8
+	vfmax.vv v8, v4, v8
+	vfmax.vv v0, v4, v8, v0.t
+	vfmax.vf v4, v4, fa1
+	vfmax.vf v0, v4, fa1, v0.t
+
+# Vector Floating-Point Sign-Injection Instructions
+
+	vfneg.v v4, v4			# OK
+	vfneg.v v0, v4, v0.t		# vd overlap vm
+
+	vfsgnj.vv v4, v4, v8		# OK
+	vfsgnj.vv v8, v4, v8		# OK
+	vfsgnj.vv v0, v4, v8, v0.t	# vd overlap vm
+	vfsgnj.vf v4, v4, fa1		# OK
+	vfsgnj.vf v0, v4, fa1, v0.t	# vd overlap vm
+
+	vfsgnjn.vv v4, v4, v8
+	vfsgnjn.vv v8, v4, v8
+	vfsgnjn.vv v0, v4, v8, v0.t
+	vfsgnjn.vf v4, v4, fa1
+	vfsgnjn.vf v0, v4, fa1, v0.t
+
+	vfsgnjx.vv v4, v4, v8
+	vfsgnjx.vv v8, v4, v8
+	vfsgnjx.vv v0, v4, v8, v0.t
+	vfsgnjx.vf v4, v4, fa1
+	vfsgnjx.vf v0, v4, fa1, v0.t
+
+# Single-Width Floating-Point/Integer Type-Convert Instructions
+
+	vfcvt.xu.f.v v4, v4		# OK
+	vfcvt.xu.f.v v0, v4, v0.t	# vd overlap vm
+	vfcvt.x.f.v v4, v4
+	vfcvt.x.f.v v0, v4, v0.t
+	vfcvt.rtz.xu.f.v v4, v4
+	vfcvt.rtz.xu.f.v v0, v4, v0.t
+	vfcvt.rtz.x.f.v v4, v4
+	vfcvt.rtz.x.f.v v0, v4, v0.t
+	vfcvt.f.xu.v v4, v4
+	vfcvt.f.xu.v v0, v4, v0.t
+	vfcvt.f.x.v v4, v4
+	vfcvt.f.x.v v0, v4, v0.t
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-int.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-int.d
new file mode 100644
index 0000000..55b350b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-int.d
@@ -0,0 +1,3 @@
+#as: -march=rv32iv -mcheck-constraints
+#source: vector-insns-fail-arith-int.s
+#error_output: vector-insns-fail-arith-int.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-int.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-int.l
new file mode 100644
index 0000000..5c9016d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-int.l
@@ -0,0 +1,71 @@
+.*: Assembler messages:
+.*Error: illegal operands vd cannot overlap vm `vneg.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vadd.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vadd.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vadd.vi v0,v4,15,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsub.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsub.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vrsub.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vrsub.vi v0,v4,15,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vzext.vf2 v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsext.vf2 v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vzext.vf4 v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsext.vf4 v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vzext.vf8 v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsext.vf8 v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vadc.vvm v0,v4,v8,v0'
+.*Error: illegal operands vd cannot overlap vm `vadc.vxm v0,v4,a1,v0'
+.*Error: illegal operands vd cannot overlap vm `vadc.vim v0,v4,15,v0'
+.*Error: illegal operands vd cannot overlap vm `vsbc.vvm v0,v4,v8,v0'
+.*Error: illegal operands vd cannot overlap vm `vsbc.vxm v0,v4,a1,v0'
+.*Error: illegal operands vd cannot overlap vm `vnot.v v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vand.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vand.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vand.vi v0,v4,15,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vor.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vor.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vor.vi v0,v4,15,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vxor.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vxor.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vxor.vi v0,v4,15,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsll.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsll.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsll.vi v0,v4,31,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsrl.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsrl.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsrl.vi v0,v4,31,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsra.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsra.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsra.vi v0,v4,31,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vminu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vminu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmin.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmin.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmaxu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmaxu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmax.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmax.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmul.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmul.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmulh.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmulh.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmulhu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmulhu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmulhsu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmulhsu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vdivu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vdivu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vdiv.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vdiv.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vremu.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vremu.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vrem.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vrem.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmacc.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmacc.vx v0,a1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vnmsac.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vnmsac.vx v0,a1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmadd.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vmadd.vx v0,a1,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vnmsub.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vnmsub.vx v0,a1,v4,v0.t'
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-int.s b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-int.s
new file mode 100644
index 0000000..6ce4e42
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-int.s
@@ -0,0 +1,213 @@
+# Vector Single-Width Integer Add and Subtract
+
+	vneg.v v4, v4			# OK
+	vneg.v v0, v4, v0.t		# vd overlap vm
+
+	vadd.vv v4, v4, v8		# OK
+	vadd.vv v8, v4, v8		# OK
+	vadd.vv v0, v4, v8, v0.t	# vd overlap vm
+	vadd.vx v4, v4, a1		# OK
+	vadd.vx v0, v4, a1, v0.t	# vd overlap vm
+	vadd.vi v4, v4, 15		# OK
+	vadd.vi v0, v4, 15, v0.t	# vd overlap vm
+
+	vsub.vv v4, v4, v8		# OK
+	vsub.vv v8, v4, v8		# OK
+	vsub.vv v0, v4, v8, v0.t	# vd overlap vm
+	vsub.vx v4, v4, a1		# OK
+	vsub.vx v0, v4, a1, v0.t	# vd overlap vm
+
+	vrsub.vx v4, v4, a1		# OK
+	vrsub.vx v0, v4, a1, v0.t	# vd overlap vm
+	vrsub.vi v4, v4, 15		# OK
+	vrsub.vi v0, v4, 15, v0.t	# vd overlap vm
+
+# Vector Integer Extension
+
+	vzext.vf2 v4, v4		# OK
+	vzext.vf2 v0, v4, v0.t		# vd overlap vm
+	vsext.vf2 v4, v4
+	vsext.vf2 v0, v4, v0.t
+	vzext.vf4 v4, v4
+	vzext.vf4 v0, v4, v0.t
+	vsext.vf4 v4, v4
+	vsext.vf4 v0, v4, v0.t
+	vzext.vf8 v4, v4
+	vzext.vf8 v0, v4, v0.t
+	vsext.vf8 v4, v4
+	vsext.vf8 v0, v4, v0.t
+
+# Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
+
+	vadc.vvm v4, v4, v8, v0		# OK
+	vadc.vvm v8, v4, v8, v0		# OK
+	vadc.vvm v0, v4, v8, v0		# vd overlap vm
+	vadc.vxm v4, v4, a1, v0		# OK
+	vadc.vxm v0, v4, a1, v0		# vd overlap vm
+	vadc.vim v4, v4, 15, v0		# OK
+	vadc.vim v0, v4, 15, v0		# vd overlap vm
+
+	vsbc.vvm v4, v4, v8, v0		# OK
+	vsbc.vvm v8, v4, v8, v0		# OK
+	vsbc.vvm v0, v4, v8, v0		# vd overlap vm
+	vsbc.vxm v4, v4, a1, v0		# OK
+	vsbc.vxm v0, v4, a1, v0		# vd overlap vm
+
+# Vector Bitwise Logical Instructions
+
+	vnot.v v4, v4			# OK
+	vnot.v v0, v4, v0.t		# vd overlap vm
+
+	vand.vv	v4, v4, v8		# OK
+	vand.vv v8, v4, v8		# OK
+	vand.vv v0, v4, v8, v0.t	# vd overlap vm
+	vand.vx v4, v4, a1		# OK
+	vand.vx v0, v4, a1, v0.t	# vd overlap vm
+	vand.vi v4, v4, 15		# OK
+	vand.vi v0, v4, 15, v0.t	# vd overlap vm
+
+	vor.vv	v4, v4, v8
+	vor.vv v8, v4, v8
+	vor.vv v0, v4, v8, v0.t
+	vor.vx v4, v4, a1
+	vor.vx v0, v4, a1, v0.t
+	vor.vi v4, v4, 15
+	vor.vi v0, v4, 15, v0.t
+
+	vxor.vv	v4, v4, v8
+	vxor.vv v8, v4, v8
+	vxor.vv v0, v4, v8, v0.t
+	vxor.vx v4, v4, a1
+	vxor.vx v0, v4, a1, v0.t
+	vxor.vi v4, v4, 15
+	vxor.vi v0, v4, 15, v0.t
+
+# Vector Single-Width Bit Shift Instructions
+
+	vsll.vv v4, v4, v8		# OK
+	vsll.vv v8, v4, v8		# OK
+	vsll.vv v0, v4, v8, v0.t	# vd overlap vm
+	vsll.vx v4, v4, a1		# OK
+	vsll.vx v0, v4, a1, v0.t	# vd overlap vm
+	vsll.vi v4, v4, 31		# OK
+	vsll.vi v0, v4, 31, v0.t	# vd overlap vm
+
+	vsrl.vv v4, v4, v8
+	vsrl.vv v8, v4, v8
+	vsrl.vv v0, v4, v8, v0.t
+	vsrl.vx v4, v4, a1
+	vsrl.vx v0, v4, a1, v0.t
+	vsrl.vi v4, v4, 31
+	vsrl.vi v0, v4, 31, v0.t
+
+	vsra.vv v4, v4, v8
+	vsra.vv v8, v4, v8
+	vsra.vv v0, v4, v8, v0.t
+	vsra.vx v4, v4, a1
+	vsra.vx v0, v4, a1, v0.t
+	vsra.vi v4, v4, 31
+	vsra.vi v0, v4, 31, v0.t
+
+# Vector Integer Min/Max Instructions
+
+	vminu.vv v4, v4, v8		# OK
+	vminu.vv v8, v4, v8		# OK
+	vminu.vv v0, v4, v8, v0.t	# vd overlap vm
+	vminu.vx v4, v4, a1		# OK
+	vminu.vx v0, v4, a1, v0.t	# vd overlap vm
+
+	vmin.vv v4, v4, v8
+	vmin.vv v8, v4, v8
+	vmin.vv v0, v4, v8, v0.t
+	vmin.vx v4, v4, a1
+	vmin.vx v0, v4, a1, v0.t
+
+	vmaxu.vv v4, v4, v8
+	vmaxu.vv v8, v4, v8
+	vmaxu.vv v0, v4, v8, v0.t
+	vmaxu.vx v4, v4, a1
+	vmaxu.vx v0, v4, a1, v0.t
+
+	vmax.vv v4, v4, v8
+	vmax.vv v8, v4, v8
+	vmax.vv v0, v4, v8, v0.t
+	vmax.vx v4, v4, a1
+	vmax.vx v0, v4, a1, v0.t
+
+# Vector Single-Width Integer Multiply Instructions
+
+	vmul.vv v4, v4, v8		# OK
+	vmul.vv v8, v4, v8		# OK
+	vmul.vv v0, v4, v8, v0.t	# vd overlap vm
+	vmul.vx v4, v4, a1		# OK
+	vmul.vx v0, v4, a1, v0.t	# vd overlap vm
+
+	vmulh.vv v4, v4, v8
+	vmulh.vv v8, v4, v8
+	vmulh.vv v0, v4, v8, v0.t
+	vmulh.vx v4, v4, a1
+	vmulh.vx v0, v4, a1, v0.t
+
+	vmulhu.vv v4, v4, v8
+	vmulhu.vv v8, v4, v8
+	vmulhu.vv v0, v4, v8, v0.t
+	vmulhu.vx v4, v4, a1
+	vmulhu.vx v0, v4, a1, v0.t
+
+	vmulhsu.vv v4, v4, v8
+	vmulhsu.vv v8, v4, v8
+	vmulhsu.vv v0, v4, v8, v0.t
+	vmulhsu.vx v4, v4, a1
+	vmulhsu.vx v0, v4, a1, v0.t
+
+# Vector Integer Divide Instructions
+
+	vdivu.vv v4, v4, v8		# OK
+	vdivu.vv v8, v4, v8		# OK
+	vdivu.vv v0, v4, v8, v0.t	# vd overlap vm
+	vdivu.vx v4, v4, a1		# OK
+	vdivu.vx v0, v4, a1, v0.t	# vd overlap vm
+
+	vdiv.vv v4, v4, v8
+	vdiv.vv v8, v4, v8
+	vdiv.vv v0, v4, v8, v0.t
+	vdiv.vx v4, v4, a1
+	vdiv.vx v0, v4, a1, v0.t
+
+	vremu.vv v4, v4, v8
+	vremu.vv v8, v4, v8
+	vremu.vv v0, v4, v8, v0.t
+	vremu.vx v4, v4, a1
+	vremu.vx v0, v4, a1, v0.t
+
+	vrem.vv v4, v4, v8
+	vrem.vv v8, v4, v8
+	vrem.vv v0, v4, v8, v0.t
+	vrem.vx v4, v4, a1
+	vrem.vx v0, v4, a1, v0.t
+
+# Vector Single-Width Integer Multiply-Add Instructions
+
+	vmacc.vv v4, v4, v8		# OK
+	vmacc.vv v8, v4, v8		# OK
+	vmacc.vv v0, v4, v8, v0.t	# vd overlap vm
+	vmacc.vx v4, a1, v4		# OK
+	vmacc.vx v0, a1, v4, v0.t	# vd overlap vm
+
+	vnmsac.vv v4, v4, v8
+	vnmsac.vv v8, v4, v8
+	vnmsac.vv v0, v4, v8, v0.t
+	vnmsac.vx v4, a1, v4
+	vnmsac.vx v0, a1, v4, v0.t
+
+	vmadd.vv v4, v4, v8
+	vmadd.vv v8, v4, v8
+	vmadd.vv v0, v4, v8, v0.t
+	vmadd.vx v4, a1, v4
+	vmadd.vx v0, a1, v4, v0.t
+
+	vnmsub.vv v4, v4, v8
+	vnmsub.vv v8, v4, v8
+	vnmsub.vv v0, v4, v8, v0.t
+	vnmsub.vx v4, a1, v4
+	vnmsub.vx v0, a1, v4, v0.t
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.d
new file mode 100644
index 0000000..e7a4d4e0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.d
@@ -0,0 +1,3 @@
+#as: -march=rv32ifv -mcheck-constraints
+#source: vector-insns-fail-arith-narrow.s
+#error_output: vector-insns-fail-arith-narrow.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.l
new file mode 100644
index 0000000..3a3634c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.l
@@ -0,0 +1,85 @@
+.*: Assembler messages:
+.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.w v2,v2'
+.*Error: illegal operands vd must be multiple of 2 `vncvt.x.x.w v2,v3'
+.*Error: illegal operands vd cannot overlap vs2 `vncvt.x.x.w v3,v2'
+.*Error: illegal operands vd cannot overlap vm `vncvt.x.x.w v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vnsrl.wv v2,v2,v4'
+.*Error: illegal operands vd must be multiple of 2 `vnsrl.wv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vnsrl.wv v3,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vnsrl.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vnsrl.wx v2,v2,a1'
+.*Error: illegal operands vd must be multiple of 2 `vnsrl.wx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vnsrl.wx v3,v2,a1'
+.*Error: illegal operands vd cannot overlap vm `vnsrl.wx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vnsrl.wi v2,v2,31'
+.*Error: illegal operands vd must be multiple of 2 `vnsrl.wi v2,v3,31'
+.*Error: illegal operands vd cannot overlap vs2 `vnsrl.wi v3,v2,31'
+.*Error: illegal operands vd cannot overlap vm `vnsrl.wi v0,v2,31,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vnsra.wv v2,v2,v4'
+.*Error: illegal operands vd must be multiple of 2 `vnsra.wv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vnsra.wv v3,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vnsra.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vnsra.wx v2,v2,a1'
+.*Error: illegal operands vd must be multiple of 2 `vnsra.wx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vnsra.wx v3,v2,a1'
+.*Error: illegal operands vd cannot overlap vm `vnsra.wx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vnsra.wi v2,v2,31'
+.*Error: illegal operands vd must be multiple of 2 `vnsra.wi v2,v3,31'
+.*Error: illegal operands vd cannot overlap vs2 `vnsra.wi v3,v2,31'
+.*Error: illegal operands vd cannot overlap vm `vnsra.wi v0,v2,31,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vnclipu.wv v2,v2,v4'
+.*Error: illegal operands vd must be multiple of 2 `vnclipu.wv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vnclipu.wv v3,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vnclipu.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vnclipu.wx v2,v2,a1'
+.*Error: illegal operands vd must be multiple of 2 `vnclipu.wx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vnclipu.wx v3,v2,a1'
+.*Error: illegal operands vd cannot overlap vm `vnclipu.wx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vnclipu.wi v2,v2,31'
+.*Error: illegal operands vd must be multiple of 2 `vnclipu.wi v2,v3,31'
+.*Error: illegal operands vd cannot overlap vs2 `vnclipu.wi v3,v2,31'
+.*Error: illegal operands vd cannot overlap vm `vnclipu.wi v0,v2,31,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vnclip.wv v2,v2,v4'
+.*Error: illegal operands vd must be multiple of 2 `vnclip.wv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vnclip.wv v3,v2,v4'
+.*Error: illegal operands vd cannot overlap vm `vnclip.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vnclip.wx v2,v2,a1'
+.*Error: illegal operands vd must be multiple of 2 `vnclip.wx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vnclip.wx v3,v2,a1'
+.*Error: illegal operands vd cannot overlap vm `vnclip.wx v0,v2,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vnclip.wi v2,v2,31'
+.*Error: illegal operands vd must be multiple of 2 `vnclip.wi v2,v3,31'
+.*Error: illegal operands vd cannot overlap vs2 `vnclip.wi v3,v2,31'
+.*Error: illegal operands vd cannot overlap vm `vnclip.wi v0,v2,31,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.xu.f.w v2,v2'
+.*Error: illegal operands vd must be multiple of 2 `vfncvt.xu.f.w v2,v3'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.xu.f.w v3,v2'
+.*Error: illegal operands vd cannot overlap vm `vfncvt.xu.f.w v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.x.f.w v2,v2'
+.*Error: illegal operands vd must be multiple of 2 `vfncvt.x.f.w v2,v3'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.x.f.w v3,v2'
+.*Error: illegal operands vd cannot overlap vm `vfncvt.x.f.w v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.rtz.xu.f.w v2,v2'
+.*Error: illegal operands vd must be multiple of 2 `vfncvt.rtz.xu.f.w v2,v3'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.rtz.xu.f.w v3,v2'
+.*Error: illegal operands vd cannot overlap vm `vfncvt.rtz.xu.f.w v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.rtz.x.f.w v2,v2'
+.*Error: illegal operands vd must be multiple of 2 `vfncvt.rtz.x.f.w v2,v3'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.rtz.x.f.w v3,v2'
+.*Error: illegal operands vd cannot overlap vm `vfncvt.rtz.x.f.w v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.f.xu.w v2,v2'
+.*Error: illegal operands vd must be multiple of 2 `vfncvt.f.xu.w v2,v3'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.f.xu.w v3,v2'
+.*Error: illegal operands vd cannot overlap vm `vfncvt.f.xu.w v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.f.x.w v2,v2'
+.*Error: illegal operands vd must be multiple of 2 `vfncvt.f.x.w v2,v3'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.f.x.w v3,v2'
+.*Error: illegal operands vd cannot overlap vm `vfncvt.f.x.w v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.f.f.w v2,v2'
+.*Error: illegal operands vd must be multiple of 2 `vfncvt.f.f.w v2,v3'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.f.f.w v3,v2'
+.*Error: illegal operands vd cannot overlap vm `vfncvt.f.f.w v0,v2,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.rod.f.f.w v2,v2'
+.*Error: illegal operands vd must be multiple of 2 `vfncvt.rod.f.f.w v2,v3'
+.*Error: illegal operands vd cannot overlap vs2 `vfncvt.rod.f.f.w v3,v2'
+.*Error: illegal operands vd cannot overlap vm `vfncvt.rod.f.f.w v0,v2,v0.t'
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.s b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.s
new file mode 100644
index 0000000..73b96ef
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-narrow.s
@@ -0,0 +1,100 @@
+# Vector Narrowing Integer Right Shift Instructions
+
+	# vncvt.x.x.w vd,vs,vm = vnsrl.wx vd,vs,x0,vm
+	vncvt.x.x.w v2, v2		# vd overlap vs2
+	vncvt.x.x.w v2, v3		# vs2 should be multiple of 2
+	vncvt.x.x.w v3, v2		# vd overlap vs2
+	vncvt.x.x.w v0, v2, v0.t	# vd overlap vm
+
+	vnsrl.wv v2, v2, v4		# vd overlap vs2
+	vnsrl.wv v2, v3, v4		# vs2 should be multiple of 2
+	vnsrl.wv v3, v2, v4		# vd overlap vs2
+	vnsrl.wv v4, v2, v4		# OK
+	vnsrl.wv v0, v2, v4, v0.t	# vd overlap vm
+	vnsrl.wx v2, v2, a1		# vd overlap vs2
+	vnsrl.wx v2, v3, a1		# vs2 should be multiple of 2
+	vnsrl.wx v3, v2, a1		# vd overlap vs2
+	vnsrl.wx v0, v2, a1, v0.t	# vd overlap vm
+	vnsrl.wi v2, v2, 31		# vd overlap vs2
+	vnsrl.wi v2, v3, 31		# vs2 should be multiple of 2
+	vnsrl.wi v3, v2, 31		# vd overlap vs2
+	vnsrl.wi v0, v2, 31, v0.t	# vd overlap vm
+
+	vnsra.wv v2, v2, v4
+	vnsra.wv v2, v3, v4
+	vnsra.wv v3, v2, v4
+	vnsra.wv v4, v2, v4
+	vnsra.wv v0, v2, v4, v0.t
+	vnsra.wx v2, v2, a1
+	vnsra.wx v2, v3, a1
+	vnsra.wx v3, v2, a1
+	vnsra.wx v0, v2, a1, v0.t
+	vnsra.wi v2, v2, 31
+	vnsra.wi v2, v3, 31
+	vnsra.wi v3, v2, 31
+	vnsra.wi v0, v2, 31, v0.t
+
+# Vector Narrowing Fixed-Point Clip Instructions
+
+	vnclipu.wv v2, v2, v4		# vd overlap vs2
+	vnclipu.wv v2, v3, v4		# vs2 should be multiple of 2
+	vnclipu.wv v3, v2, v4		# vd overlap vs2
+	vnclipu.wv v4, v2, v4		# OK
+	vnclipu.wv v0, v2, v4, v0.t	# vd overlap vm
+	vnclipu.wx v2, v2, a1		# vd overlap vs2
+	vnclipu.wx v2, v3, a1		# vs2 should be multiple of 2
+	vnclipu.wx v3, v2, a1		# vd overlap vs2
+	vnclipu.wx v0, v2, a1, v0.t	# vd overlap vm
+	vnclipu.wi v2, v2, 31		# vd overlap vs2
+	vnclipu.wi v2, v3, 31		# vs2 should be multiple of 2
+	vnclipu.wi v3, v2, 31		# vd overlap vs2
+	vnclipu.wi v0, v2, 31, v0.t	# vd overlap vm
+
+	vnclip.wv v2, v2, v4
+	vnclip.wv v2, v3, v4
+	vnclip.wv v3, v2, v4
+	vnclip.wv v4, v2, v4
+	vnclip.wv v0, v2, v4, v0.t
+	vnclip.wx v2, v2, a1
+	vnclip.wx v2, v3, a1
+	vnclip.wx v3, v2, a1
+	vnclip.wx v0, v2, a1, v0.t
+	vnclip.wi v2, v2, 31
+	vnclip.wi v2, v3, 31
+	vnclip.wi v3, v2, 31
+	vnclip.wi v0, v2, 31, v0.t
+
+# Narrowing Floating-Point/Integer Type-Convert Instructions
+
+	vfncvt.xu.f.w v2, v2		# vd overlap vs2
+	vfncvt.xu.f.w v2, v3		# vs2 should be multiple of 2
+	vfncvt.xu.f.w v3, v2		# vd overlap vs2
+	vfncvt.xu.f.w v0, v2, v0.t	# vd overlap vm
+	vfncvt.x.f.w v2, v2
+	vfncvt.x.f.w v2, v3
+	vfncvt.x.f.w v3, v2
+	vfncvt.x.f.w v0, v2, v0.t
+	vfncvt.rtz.xu.f.w v2, v2
+	vfncvt.rtz.xu.f.w v2, v3
+	vfncvt.rtz.xu.f.w v3, v2
+	vfncvt.rtz.xu.f.w v0, v2, v0.t
+	vfncvt.rtz.x.f.w v2, v2
+	vfncvt.rtz.x.f.w v2, v3
+	vfncvt.rtz.x.f.w v3, v2
+	vfncvt.rtz.x.f.w v0, v2, v0.t
+	vfncvt.f.xu.w v2, v2
+	vfncvt.f.xu.w v2, v3
+	vfncvt.f.xu.w v3, v2
+	vfncvt.f.xu.w v0, v2, v0.t
+	vfncvt.f.x.w v2, v2
+	vfncvt.f.x.w v2, v3
+	vfncvt.f.x.w v3, v2
+	vfncvt.f.x.w v0, v2, v0.t
+	vfncvt.f.f.w v2, v2
+	vfncvt.f.f.w v2, v3
+	vfncvt.f.f.w v3, v2
+	vfncvt.f.f.w v0, v2, v0.t
+	vfncvt.rod.f.f.w v2, v2
+	vfncvt.rod.f.f.w v2, v3
+	vfncvt.rod.f.f.w v3, v2
+	vfncvt.rod.f.f.w v0, v2, v0.t
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.d
new file mode 100644
index 0000000..e5f0348
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.d
@@ -0,0 +1,3 @@
+#as: -march=rv32ifv -mcheck-constraints
+#source: vector-insns-fail-arith-widen.s
+#error_output: vector-insns-fail-arith-widen.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.l
new file mode 100644
index 0000000..5f22ca9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.l
@@ -0,0 +1,253 @@
+.*: Assembler messages:
+.*Error: illegal operands vd must be multiple of 2 `vwcvtu.x.x.v v1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vwcvtu.x.x.v v2,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vwcvtu.x.x.v v2,v3'
+.*Error: illegal operands vd cannot overlap vm `vwcvtu.x.x.v v0,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwcvt.x.x.v v1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vwcvt.x.x.v v2,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vwcvt.x.x.v v2,v3'
+.*Error: illegal operands vd cannot overlap vm `vwcvt.x.x.v v0,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwaddu.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwaddu.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwaddu.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwaddu.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwaddu.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vwaddu.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwaddu.vx v1,v2,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vwaddu.vx v2,v2,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vwaddu.vx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vm `vwaddu.vx v0,v2,a1,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwaddu.wv v1,v2,v4'
+.*Error: illegal operands vs2 must be multiple of 2 `vwaddu.wv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwaddu.wv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwaddu.wv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vwaddu.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwaddu.wx v1,v2,a1'
+.*Error: illegal operands vs2 must be multiple of 2 `vwaddu.wx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vm `vwaddu.wx v0,v2,a1,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwsubu.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwsubu.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwsubu.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwsubu.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwsubu.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vwsubu.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwsubu.vx v1,v2,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vwsubu.vx v2,v2,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vwsubu.vx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vm `vwsubu.vx v0,v2,a1,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwsubu.wv v1,v2,v4'
+.*Error: illegal operands vs2 must be multiple of 2 `vwsubu.wv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwsubu.wv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwsubu.wv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vwsubu.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwsubu.wx v1,v2,a1'
+.*Error: illegal operands vs2 must be multiple of 2 `vwsubu.wx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vm `vwsubu.wx v0,v2,a1,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwadd.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwadd.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwadd.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwadd.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwadd.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vwadd.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwadd.vx v1,v2,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vwadd.vx v2,v2,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vwadd.vx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vm `vwadd.vx v0,v2,a1,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwadd.wv v1,v2,v4'
+.*Error: illegal operands vs2 must be multiple of 2 `vwadd.wv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwadd.wv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwadd.wv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vwadd.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwadd.wx v1,v2,a1'
+.*Error: illegal operands vs2 must be multiple of 2 `vwadd.wx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vm `vwadd.wx v0,v2,a1,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwsub.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwsub.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwsub.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwsub.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwsub.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vwsub.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwsub.vx v1,v2,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vwsub.vx v2,v2,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vwsub.vx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vm `vwsub.vx v0,v2,a1,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwsub.wv v1,v2,v4'
+.*Error: illegal operands vs2 must be multiple of 2 `vwsub.wv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwsub.wv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwsub.wv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vwsub.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwsub.wx v1,v2,a1'
+.*Error: illegal operands vs2 must be multiple of 2 `vwsub.wx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vm `vwsub.wx v0,v2,a1,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwmul.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmul.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmul.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmul.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmul.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vwmul.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwmul.vx v1,v2,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vwmul.vx v2,v2,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vwmul.vx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vm `vwmul.vx v0,v2,a1,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwmulu.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmulu.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmulu.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmulu.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmulu.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vwmulu.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwmulu.vx v1,v2,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vwmulu.vx v2,v2,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vwmulu.vx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vm `vwmulu.vx v0,v2,a1,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwmulsu.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmulsu.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmulsu.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmulsu.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmulsu.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vwmulsu.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwmulsu.vx v1,v2,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vwmulsu.vx v2,v2,a1'
+.*Error: illegal operands vd cannot overlap vs2 `vwmulsu.vx v2,v3,a1'
+.*Error: illegal operands vd cannot overlap vm `vwmulsu.vx v0,v2,a1,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwmaccu.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmaccu.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmaccu.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccu.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccu.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vwmaccu.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwmaccu.vx v1,a1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccu.vx v2,a1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccu.vx v2,a1,v3'
+.*Error: illegal operands vd cannot overlap vm `vwmaccu.vx v0,a1,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwmacc.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmacc.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmacc.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmacc.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmacc.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vwmacc.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwmacc.vx v1,a1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vwmacc.vx v2,a1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vwmacc.vx v2,a1,v3'
+.*Error: illegal operands vd cannot overlap vm `vwmacc.vx v0,a1,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwmaccsu.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmaccsu.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vwmaccsu.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccsu.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccsu.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vwmaccsu.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwmaccsu.vx v1,a1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccsu.vx v2,a1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccsu.vx v2,a1,v3'
+.*Error: illegal operands vd cannot overlap vm `vwmaccsu.vx v0,a1,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vwmaccus.vx v1,a1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccus.vx v2,a1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vwmaccus.vx v2,a1,v3'
+.*Error: illegal operands vd cannot overlap vm `vwmaccus.vx v0,a1,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwadd.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwadd.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwadd.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwadd.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwadd.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vfwadd.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwadd.vf v1,v2,fa1'
+.*Error: illegal operands vd cannot overlap vs2 `vfwadd.vf v2,v2,fa1'
+.*Error: illegal operands vd cannot overlap vs2 `vfwadd.vf v2,v3,fa1'
+.*Error: illegal operands vd cannot overlap vm `vfwadd.vf v0,v2,fa1,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwadd.wv v1,v2,v4'
+.*Error: illegal operands vs2 must be multiple of 2 `vfwadd.wv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwadd.wv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwadd.wv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vfwadd.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwsub.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwsub.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwsub.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vfwsub.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwsub.vf v1,v2,fa1'
+.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vf v2,v2,fa1'
+.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vf v2,v3,fa1'
+.*Error: illegal operands vd cannot overlap vm `vfwsub.vf v0,v2,fa1,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwsub.wv v1,v2,v4'
+.*Error: illegal operands vs2 must be multiple of 2 `vfwsub.wv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwsub.wv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwsub.wv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vfwsub.wv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwmul.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmul.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmul.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwmul.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwmul.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vfwmul.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwsub.vf v1,v2,fa1'
+.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vf v2,v2,fa1'
+.*Error: illegal operands vd cannot overlap vs2 `vfwsub.vf v2,v3,fa1'
+.*Error: illegal operands vd cannot overlap vm `vfwsub.vf v0,v2,fa1,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwmacc.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwmacc.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwmacc.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmacc.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmacc.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vfwmacc.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwmacc.vf v1,fa1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmacc.vf v2,fa1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmacc.vf v2,fa1,v3'
+.*Error: illegal operands vd cannot overlap vm `vfwmacc.vf v0,fa1,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwnmacc.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwnmacc.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwnmacc.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwnmacc.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwnmacc.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vfwnmacc.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwnmacc.vf v1,fa1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwnmacc.vf v2,fa1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwnmacc.vf v2,fa1,v3'
+.*Error: illegal operands vd cannot overlap vm `vfwnmacc.vf v0,fa1,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwmsac.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwmsac.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwmsac.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmsac.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmsac.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vfwmsac.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwmsac.vf v1,fa1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmsac.vf v2,fa1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwmsac.vf v2,fa1,v3'
+.*Error: illegal operands vd cannot overlap vm `vfwmsac.vf v0,fa1,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwnmsac.vv v1,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwnmsac.vv v2,v2,v4'
+.*Error: illegal operands vd cannot overlap vs1 `vfwnmsac.vv v2,v3,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwnmsac.vv v4,v2,v4'
+.*Error: illegal operands vd cannot overlap vs2 `vfwnmsac.vv v4,v2,v5'
+.*Error: illegal operands vd cannot overlap vm `vfwnmsac.vv v0,v2,v4,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwnmsac.vf v1,fa1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwnmsac.vf v2,fa1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwnmsac.vf v2,fa1,v3'
+.*Error: illegal operands vd cannot overlap vm `vfwnmsac.vf v0,fa1,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwcvt.xu.f.v v1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.xu.f.v v2,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.xu.f.v v2,v3'
+.*Error: illegal operands vd cannot overlap vm `vfwcvt.xu.f.v v0,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwcvt.x.f.v v1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.x.f.v v2,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.x.f.v v2,v3'
+.*Error: illegal operands vd cannot overlap vm `vfwcvt.x.f.v v0,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwcvt.rtz.xu.f.v v1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.rtz.xu.f.v v2,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.rtz.xu.f.v v2,v3'
+.*Error: illegal operands vd cannot overlap vm `vfwcvt.rtz.xu.f.v v0,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwcvt.rtz.x.f.v v1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.rtz.x.f.v v2,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.rtz.x.f.v v2,v3'
+.*Error: illegal operands vd cannot overlap vm `vfwcvt.rtz.x.f.v v0,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwcvt.f.xu.v v1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.xu.v v2,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.xu.v v2,v3'
+.*Error: illegal operands vd cannot overlap vm `vfwcvt.f.xu.v v0,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwcvt.f.x.v v1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.x.v v2,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.x.v v2,v3'
+.*Error: illegal operands vd cannot overlap vm `vfwcvt.f.x.v v0,v2,v0.t'
+.*Error: illegal operands vd must be multiple of 2 `vfwcvt.f.f.v v1,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.f.v v2,v2'
+.*Error: illegal operands vd cannot overlap vs2 `vfwcvt.f.f.v v2,v3'
+.*Error: illegal operands vd cannot overlap vm `vfwcvt.f.f.v v0,v2,v0.t'
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.s b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.s
new file mode 100644
index 0000000..addedd4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-arith-widen.s
@@ -0,0 +1,297 @@
+# Vector Widening Integer Add/Subtract
+
+	# vwcvtu.x.x.v vd,vs,vm = vwaddu.vx vd,vs,x0,vm
+	vwcvtu.x.x.v v1, v2		# vd should be multiple of 2
+	vwcvtu.x.x.v v2, v2		# vd overlap vs2
+	vwcvtu.x.x.v v2, v3		# vd overlap vs2
+	vwcvtu.x.x.v v0, v2, v0.t	# vd overlap vm
+
+	# vwcvt.x.x.v vd,vs,vm = vwadd.vx vd,vs,x0,vm
+	vwcvt.x.x.v v1, v2
+	vwcvt.x.x.v v2, v2
+	vwcvt.x.x.v v2, v3
+	vwcvt.x.x.v v0, v2, v0.t
+
+	vwaddu.vv v1, v2, v4		# vd should be multiple of 2
+	vwaddu.vv v2, v2, v4		# vd overlap vs2
+	vwaddu.vv v2, v3, v4		# vd overlap vs2
+	vwaddu.vv v4, v2, v4		# vd overlap vs1
+	vwaddu.vv v4, v2, v5		# vd overlap vs1
+	vwaddu.vv v0, v2, v4, v0.t	# vd overlap vm
+	vwaddu.vx v1, v2, a1		# vd should be multiple of 2
+	vwaddu.vx v2, v2, a1		# vd overlap vs2
+	vwaddu.vx v2, v3, a1		# vd overlap vs2
+	vwaddu.vx v0, v2, a1, v0.t	# vd overlap vm
+	vwaddu.wv v1, v2, v4		# vd should be multiple of 2
+	vwaddu.wv v2, v2, v4		# OK
+	vwaddu.wv v2, v3, v4		# vs2 should be multiple of 2
+	vwaddu.wv v4, v2, v4		# vd overlap vs1
+	vwaddu.wv v4, v2, v5		# vd overlap vs1
+	vwaddu.wv v0, v2, v4, v0.t	# vd overlap vm
+	vwaddu.wx v1, v2, a1		# vd should be multiple of 2
+	vwaddu.wx v2, v2, a1		# OK
+	vwaddu.wx v2, v3, a1		# vs2 should be multiple of 2
+	vwaddu.wx v0, v2, a1, v0.t	# vd overlap vm
+
+	vwsubu.vv v1, v2, v4
+	vwsubu.vv v2, v2, v4
+	vwsubu.vv v2, v3, v4
+	vwsubu.vv v4, v2, v4
+	vwsubu.vv v4, v2, v5
+	vwsubu.vv v0, v2, v4, v0.t
+	vwsubu.vx v1, v2, a1
+	vwsubu.vx v2, v2, a1
+	vwsubu.vx v2, v3, a1
+	vwsubu.vx v0, v2, a1, v0.t
+	vwsubu.wv v1, v2, v4
+	vwsubu.wv v2, v2, v4
+	vwsubu.wv v2, v3, v4
+	vwsubu.wv v4, v2, v4
+	vwsubu.wv v4, v2, v5
+	vwsubu.wv v0, v2, v4, v0.t
+	vwsubu.wx v1, v2, a1
+	vwsubu.wx v2, v2, a1
+	vwsubu.wx v2, v3, a1
+	vwsubu.wx v0, v2, a1, v0.t
+
+	vwadd.vv v1, v2, v4
+	vwadd.vv v2, v2, v4
+	vwadd.vv v2, v3, v4
+	vwadd.vv v4, v2, v4
+	vwadd.vv v4, v2, v5
+	vwadd.vv v0, v2, v4, v0.t
+	vwadd.vx v1, v2, a1
+	vwadd.vx v2, v2, a1
+	vwadd.vx v2, v3, a1
+	vwadd.vx v0, v2, a1, v0.t
+	vwadd.wv v1, v2, v4
+	vwadd.wv v2, v2, v4
+	vwadd.wv v2, v3, v4
+	vwadd.wv v4, v2, v4
+	vwadd.wv v4, v2, v5
+	vwadd.wv v0, v2, v4, v0.t
+	vwadd.wx v1, v2, a1
+	vwadd.wx v2, v2, a1
+	vwadd.wx v2, v3, a1
+	vwadd.wx v0, v2, a1, v0.t
+
+	vwsub.vv v1, v2, v4
+	vwsub.vv v2, v2, v4
+	vwsub.vv v2, v3, v4
+	vwsub.vv v4, v2, v4
+	vwsub.vv v4, v2, v5
+	vwsub.vv v0, v2, v4, v0.t
+	vwsub.vx v1, v2, a1
+	vwsub.vx v2, v2, a1
+	vwsub.vx v2, v3, a1
+	vwsub.vx v0, v2, a1, v0.t
+	vwsub.wv v1, v2, v4
+	vwsub.wv v2, v2, v4
+	vwsub.wv v2, v3, v4
+	vwsub.wv v4, v2, v4
+	vwsub.wv v4, v2, v5
+	vwsub.wv v0, v2, v4, v0.t
+	vwsub.wx v1, v2, a1
+	vwsub.wx v2, v2, a1
+	vwsub.wx v2, v3, a1
+	vwsub.wx v0, v2, a1, v0.t
+
+# Vector Widening Integer Multiply Instructions
+
+	vwmul.vv v1, v2, v4		# vd should be multiple of 2
+	vwmul.vv v2, v2, v4		# vd overlap vs2
+	vwmul.vv v2, v3, v4		# vd overlap vs2
+	vwmul.vv v4, v2, v4		# vd overlap vs1
+	vwmul.vv v4, v2, v5		# vd overlap vs1
+	vwmul.vv v0, v2, v4, v0.t	# vd overlap vm
+	vwmul.vx v1, v2, a1		# vd should be multiple of 2
+	vwmul.vx v2, v2, a1		# vd overlap vs2
+	vwmul.vx v2, v3, a1		# vd overlap vs2
+	vwmul.vx v0, v2, a1, v0.t	# vd overlap vm
+
+	vwmulu.vv v1, v2, v4
+	vwmulu.vv v2, v2, v4
+	vwmulu.vv v2, v3, v4
+	vwmulu.vv v4, v2, v4
+	vwmulu.vv v4, v2, v5
+	vwmulu.vv v0, v2, v4, v0.t
+	vwmulu.vx v1, v2, a1
+	vwmulu.vx v2, v2, a1
+	vwmulu.vx v2, v3, a1
+	vwmulu.vx v0, v2, a1, v0.t
+
+	vwmulsu.vv v1, v2, v4
+	vwmulsu.vv v2, v2, v4
+	vwmulsu.vv v2, v3, v4
+	vwmulsu.vv v4, v2, v4
+	vwmulsu.vv v4, v2, v5
+	vwmulsu.vv v0, v2, v4, v0.t
+	vwmulsu.vx v1, v2, a1
+	vwmulsu.vx v2, v2, a1
+	vwmulsu.vx v2, v3, a1
+	vwmulsu.vx v0, v2, a1, v0.t
+
+# Vector Widening Integer Multiply-Add Instructions
+
+	vwmaccu.vv v1, v2, v4		# vd should be multiple of 2
+	vwmaccu.vv v2, v2, v4		# vd overlap vs1
+	vwmaccu.vv v2, v3, v4		# vd overlap vs1
+	vwmaccu.vv v4, v2, v4		# vd overlap vs2
+	vwmaccu.vv v4, v2, v5		# vd overlap vs2
+	vwmaccu.vv v0, v2, v4, v0.t	# vd overlap vm
+	vwmaccu.vx v1, a1, v2		# vd should be multiple of 2
+	vwmaccu.vx v2, a1, v2		# vd overlap vs2
+	vwmaccu.vx v2, a1, v3		# vd overlap vs2
+	vwmaccu.vx v0, a1, v2, v0.t	# vd overlap vm
+
+	vwmacc.vv v1, v2, v4
+	vwmacc.vv v2, v2, v4
+	vwmacc.vv v2, v3, v4
+	vwmacc.vv v4, v2, v4
+	vwmacc.vv v4, v2, v5
+	vwmacc.vv v0, v2, v4, v0.t
+	vwmacc.vx v1, a1, v2
+	vwmacc.vx v2, a1, v2
+	vwmacc.vx v2, a1, v3
+	vwmacc.vx v0, a1, v2, v0.t
+
+	vwmaccsu.vv v1, v2, v4
+	vwmaccsu.vv v2, v2, v4
+	vwmaccsu.vv v2, v3, v4
+	vwmaccsu.vv v4, v2, v4
+	vwmaccsu.vv v4, v2, v5
+	vwmaccsu.vv v0, v2, v4, v0.t
+	vwmaccsu.vx v1, a1, v2
+	vwmaccsu.vx v2, a1, v2
+	vwmaccsu.vx v2, a1, v3
+	vwmaccsu.vx v0, a1, v2, v0.t
+
+	vwmaccus.vx v1, a1, v2		# vd should be multiple of 2
+	vwmaccus.vx v2, a1, v2		# vd overlap vs2
+	vwmaccus.vx v2, a1, v3		# vd overlap vs2
+	vwmaccus.vx v0, a1, v2, v0.t	# vd overlap vm
+
+# Vector Widening Floating-Point Add/Subtract Instructions
+
+	vfwadd.vv v1, v2, v4		# vd should be multiple of 2
+	vfwadd.vv v2, v2, v4		# vd overlap vs2
+	vfwadd.vv v2, v3, v4		# vd overlap vs2
+	vfwadd.vv v4, v2, v4		# vd overlap vs1
+	vfwadd.vv v4, v2, v5		# vd overlap vs1
+	vfwadd.vv v0, v2, v4, v0.t	# vd overlap vm
+	vfwadd.vf v1, v2, fa1		# vd should be multiple of 2
+	vfwadd.vf v2, v2, fa1		# vd overlap vs2
+	vfwadd.vf v2, v3, fa1		# vd overlap vs2
+	vfwadd.vf v0, v2, fa1, v0.t	# vd overlap vm
+	vfwadd.wv v1, v2, v4		# vd should be multiple of 2
+	vfwadd.wv v2, v2, v4		# OK
+	vfwadd.wv v2, v3, v4		# vs2 should be multiple of 2
+	vfwadd.wv v4, v2, v4		# vd overlap vs1
+	vfwadd.wv v4, v2, v5		# vd overlap vs1
+	vfwadd.wv v0, v2, v4, v0.t	# vd overlap vm
+
+	vfwsub.vv v1, v2, v4
+	vfwsub.vv v2, v2, v4
+	vfwsub.vv v2, v3, v4
+	vfwsub.vv v4, v2, v4
+	vfwsub.vv v4, v2, v5
+	vfwsub.vv v0, v2, v4, v0.t
+	vfwsub.vf v1, v2, fa1
+	vfwsub.vf v2, v2, fa1
+	vfwsub.vf v2, v3, fa1
+	vfwsub.vf v0, v2, fa1, v0.t
+	vfwsub.wv v1, v2, v4
+	vfwsub.wv v2, v2, v4
+	vfwsub.wv v2, v3, v4
+	vfwsub.wv v4, v2, v4
+	vfwsub.wv v4, v2, v5
+	vfwsub.wv v0, v2, v4, v0.t
+
+# Vector Widening Floating-Point Multiply
+
+	vfwmul.vv v1, v2, v4		# vd should be multiple of 2
+	vfwmul.vv v2, v2, v4		# vd overlap vs2
+	vfwmul.vv v2, v3, v4		# vd overlap vs2
+	vfwmul.vv v4, v2, v4		# vd overlap vs1
+	vfwmul.vv v4, v2, v5		# vd overlap vs1
+	vfwmul.vv v0, v2, v4, v0.t	# vd overlap vm
+	vfwsub.vf v1, v2, fa1		# vd should be multiple of 2
+	vfwsub.vf v2, v2, fa1		# vd overlap vs2
+	vfwsub.vf v2, v3, fa1		# vd overlap vs2
+	vfwsub.vf v0, v2, fa1, v0.t	# vd overlap vm
+
+# Vector Widening Floating-Point Fused Multiply-Add Instructions
+	vfwmacc.vv v1, v2, v4		# vd should be multiple of 2
+	vfwmacc.vv v2, v2, v4		# vd overlap vs1
+	vfwmacc.vv v2, v3, v4		# vd overlap vs1
+	vfwmacc.vv v4, v2, v4		# vd overlap vs2
+	vfwmacc.vv v4, v2, v5		# vd overlap vs2
+	vfwmacc.vv v0, v2, v4, v0.t	# vd overlap vm
+	vfwmacc.vf v1, fa1, v2		# vd should be multiple of 2
+	vfwmacc.vf v2, fa1, v2		# vd overlap vs2
+	vfwmacc.vf v2, fa1, v3		# vd overlap vs2
+	vfwmacc.vf v0, fa1, v2, v0.t	# vd overlap vm
+
+	vfwnmacc.vv v1, v2, v4
+	vfwnmacc.vv v2, v2, v4
+	vfwnmacc.vv v2, v3, v4
+	vfwnmacc.vv v4, v2, v4
+	vfwnmacc.vv v4, v2, v5
+	vfwnmacc.vv v0, v2, v4, v0.t
+	vfwnmacc.vf v1, fa1, v2
+	vfwnmacc.vf v2, fa1, v2
+	vfwnmacc.vf v2, fa1, v3
+	vfwnmacc.vf v0, fa1, v2, v0.t
+
+	vfwmsac.vv v1, v2, v4
+	vfwmsac.vv v2, v2, v4
+	vfwmsac.vv v2, v3, v4
+	vfwmsac.vv v4, v2, v4
+	vfwmsac.vv v4, v2, v5
+	vfwmsac.vv v0, v2, v4, v0.t
+	vfwmsac.vf v1, fa1, v2
+	vfwmsac.vf v2, fa1, v2
+	vfwmsac.vf v2, fa1, v3
+	vfwmsac.vf v0, fa1, v2, v0.t
+
+	vfwnmsac.vv v1, v2, v4
+	vfwnmsac.vv v2, v2, v4
+	vfwnmsac.vv v2, v3, v4
+	vfwnmsac.vv v4, v2, v4
+	vfwnmsac.vv v4, v2, v5
+	vfwnmsac.vv v0, v2, v4, v0.t
+	vfwnmsac.vf v1, fa1, v2
+	vfwnmsac.vf v2, fa1, v2
+	vfwnmsac.vf v2, fa1, v3
+	vfwnmsac.vf v0, fa1, v2, v0.t
+
+# Widening Floating-Point/Integer Type-Convert Instructions
+
+	vfwcvt.xu.f.v v1, v2		# vd should be multiple of 2
+	vfwcvt.xu.f.v v2, v2		# vd overlap vs2
+	vfwcvt.xu.f.v v2, v3		# vd overlap vs2
+	vfwcvt.xu.f.v v0, v2, v0.t	# vd overlap vm
+	vfwcvt.x.f.v v1, v2
+	vfwcvt.x.f.v v2, v2
+	vfwcvt.x.f.v v2, v3
+	vfwcvt.x.f.v v0, v2, v0.t
+	vfwcvt.rtz.xu.f.v v1, v2
+	vfwcvt.rtz.xu.f.v v2, v2
+	vfwcvt.rtz.xu.f.v v2, v3
+	vfwcvt.rtz.xu.f.v v0, v2, v0.t
+	vfwcvt.rtz.x.f.v v1, v2
+	vfwcvt.rtz.x.f.v v2, v2
+	vfwcvt.rtz.x.f.v v2, v3
+	vfwcvt.rtz.x.f.v v0, v2, v0.t
+	vfwcvt.f.xu.v v1, v2
+	vfwcvt.f.xu.v v2, v2
+	vfwcvt.f.xu.v v2, v3
+	vfwcvt.f.xu.v v0, v2, v0.t
+	vfwcvt.f.x.v v1, v2
+	vfwcvt.f.x.v v2, v2
+	vfwcvt.f.x.v v2, v3
+	vfwcvt.f.x.v v0, v2, v0.t
+	vfwcvt.f.f.v v1, v2
+	vfwcvt.f.f.v v2, v2
+	vfwcvt.f.f.v v2, v3
+	vfwcvt.f.f.v v0, v2, v0.t
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-load-store.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-load-store.d
new file mode 100644
index 0000000..763191f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-load-store.d
@@ -0,0 +1,3 @@
+#as: -march=rv32iv -mcheck-constraints
+#source: vector-insns-fail-load-store.s
+#error_output: vector-insns-fail-load-store.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-load-store.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-load-store.l
new file mode 100644
index 0000000..9ef99a5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-load-store.l
@@ -0,0 +1,419 @@
+.*: Assembler messages:
+.*Error: illegal operands vd cannot overlap vm `vle8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vle8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vle16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vle16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vle32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vle32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vle64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vle64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vse8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vse16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vse32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vse64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlse8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlse16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlse32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlse64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsse8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsse16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsse32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsse64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vloxei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vloxei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vloxei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vloxei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsoxei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsoxei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsoxei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsoxei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vluxei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vluxei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vluxei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vluxei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsuxei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsuxei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsuxei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsuxei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg2e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg3e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg4e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg5e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg6e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg7e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg8e8.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e8ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg2e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg3e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg4e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg5e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg6e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg7e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg8e16.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e16ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg2e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg3e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg4e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg5e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg6e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg7e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg8e32.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e32ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg2e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg2e64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg3e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg3e64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg4e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg4e64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg5e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg5e64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg6e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg6e64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg7e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg7e64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vsseg8e64.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlseg8e64ff.v v0,\(a0\),v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg2e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg2e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg3e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg3e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg4e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg4e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg5e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg5e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg6e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg6e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg7e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg7e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg8e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg8e8.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg2e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg2e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg3e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg3e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg4e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg4e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg5e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg5e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg6e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg6e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg7e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg7e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg8e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg8e16.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg2e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg2e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg3e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg3e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg4e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg4e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg5e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg5e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg6e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg6e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg7e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg7e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg8e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg8e32.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg2e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg2e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg3e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg3e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg4e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg4e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg5e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg5e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg6e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg6e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg7e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg7e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vlsseg8e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vssseg8e64.v v0,\(a0\),a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg2ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg3ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg4ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg5ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg6ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg7ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg8ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg2ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg3ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg4ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg5ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg6ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg7ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg8ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg2ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg3ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg4ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg5ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg6ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg7ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg8ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg2ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg2ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg2ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg2ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg3ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg3ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg3ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg3ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg4ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg4ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg4ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg4ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg5ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg5ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg5ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg5ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg6ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg6ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg6ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg6ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg7ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg7ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg7ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg7ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vloxseg8ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vloxseg8ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsoxseg8ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsoxseg8ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg2ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg3ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg4ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg5ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg6ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg7ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg8ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei8.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei8.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg2ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg3ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg4ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg5ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg6ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg7ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg8ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei16.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei16.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg2ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg3ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg4ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg5ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg6ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg7ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg8ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei32.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei32.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg2ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg2ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg2ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg2ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg3ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg3ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg3ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg3ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg4ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg4ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg4ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg4ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg5ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg5ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg5ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg5ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg6ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg6ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg6ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg6ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg7ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg7ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg7ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg7ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vluxseg8ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vluxseg8ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vsuxseg8ei64.v v4,\(a0\),v4'
+.*Error: illegal operands vd cannot overlap vm `vsuxseg8ei64.v v0,\(a0\),v4,v0.t'
+.*Error: illegal operands vd must be multiple of nf `vl2r.v v31,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl2re8.v v31,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl2re16.v v31,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl2re32.v v31,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl2re64.v v31,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl4r.v v30,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl4re8.v v30,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl4re16.v v30,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl4re32.v v30,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl4re64.v v30,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl8r.v v26,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl8re8.v v26,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl8re16.v v26,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl8re32.v v26,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vl8re64.v v26,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vs2r.v v31,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vs4r.v v30,\(a0\)'
+.*Error: illegal operands vd must be multiple of nf `vs8r.v v26,\(a0\)'
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-load-store.s b/gas/testsuite/gas/riscv/extended/vector-insns-fail-load-store.s
new file mode 100644
index 0000000..274d0b4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-load-store.s
@@ -0,0 +1,481 @@
+# Vector Unit-Stride Loads and Stores
+
+	vle8.v v0, (a0), v0.t		# vd overlap vm
+	vle8ff.v v0, (a0), v0.t		# vd overlap vm
+	vle16.v v0, (a0), v0.t
+	vle16ff.v v0, (a0), v0.t
+	vle32.v v0, (a0), v0.t
+	vle32ff.v v0, (a0), v0.t
+	vle64.v v0, (a0), v0.t
+	vle64ff.v v0, (a0), v0.t
+
+	vse8.v v0, (a0), v0.t		# vd overlap vm
+	vse16.v v0, (a0), v0.t
+	vse32.v v0, (a0), v0.t
+	vse64.v v0, (a0), v0.t
+
+# Vector Strided Loads and Stores
+
+	vlse8.v v0, (a0), a1, v0.t	# vd overlap vm
+	vlse16.v v0, (a0), a1, v0.t
+	vlse32.v v0, (a0), a1, v0.t
+	vlse64.v v0, (a0), a1, v0.t
+
+	vsse8.v v0, (a0), a1, v0.t
+	vsse16.v v0, (a0), a1, v0.t
+	vsse32.v v0, (a0), a1, v0.t
+	vsse64.v v0, (a0), a1, v0.t
+
+# Vector Ordered Indexed Loads and Stores
+
+	vloxei8.v v4, (a0), v4		# OK
+	vloxei8.v v0, (a0), v4, v0.t	# vd overlap vm
+	vloxei16.v v4, (a0), v4
+	vloxei16.v v0, (a0), v4, v0.t
+	vloxei32.v v4, (a0), v4
+	vloxei32.v v0, (a0), v4, v0.t
+	vloxei64.v v4, (a0), v4
+	vloxei64.v v0, (a0), v4, v0.t
+
+	vsoxei8.v v4, (a0), v4
+	vsoxei8.v v0, (a0), v4, v0.t
+	vsoxei16.v v4, (a0), v4
+	vsoxei16.v v0, (a0), v4, v0.t
+	vsoxei32.v v4, (a0), v4
+	vsoxei32.v v0, (a0), v4, v0.t
+	vsoxei64.v v4, (a0), v4
+	vsoxei64.v v0, (a0), v4, v0.t
+
+# Vector Unordered Indexed Loads and Stores
+
+	vluxei8.v v4, (a0), v4		# OK
+	vluxei8.v v0, (a0), v4, v0.t	# vd overlap vm
+	vluxei16.v v4, (a0), v4
+	vluxei16.v v0, (a0), v4, v0.t
+	vluxei32.v v4, (a0), v4
+	vluxei32.v v0, (a0), v4, v0.t
+	vluxei64.v v4, (a0), v4
+	vluxei64.v v0, (a0), v4, v0.t
+
+	vsuxei8.v v4, (a0), v4
+	vsuxei8.v v0, (a0), v4, v0.t
+	vsuxei16.v v4, (a0), v4
+	vsuxei16.v v0, (a0), v4, v0.t
+	vsuxei32.v v4, (a0), v4
+	vsuxei32.v v0, (a0), v4, v0.t
+	vsuxei64.v v4, (a0), v4
+	vsuxei64.v v0, (a0), v4, v0.t
+
+# Vector Unit-Stride Segment Loads and Stores
+
+	vlseg2e8.v v0, (a0), v0.t	# vd overlap vm
+	vsseg2e8.v v0, (a0), v0.t	# vd overlap vm
+	vlseg2e8ff.v v0, (a0), v0.t	# vd overlap vm
+	vlseg3e8.v v0, (a0), v0.t
+	vsseg3e8.v v0, (a0), v0.t
+	vlseg3e8ff.v v0, (a0), v0.t
+	vlseg4e8.v v0, (a0), v0.t
+	vsseg4e8.v v0, (a0), v0.t
+	vlseg4e8ff.v v0, (a0), v0.t
+	vlseg5e8.v v0, (a0), v0.t
+	vsseg5e8.v v0, (a0), v0.t
+	vlseg5e8ff.v v0, (a0), v0.t
+	vlseg6e8.v v0, (a0), v0.t
+	vsseg6e8.v v0, (a0), v0.t
+	vlseg6e8ff.v v0, (a0), v0.t
+	vlseg7e8.v v0, (a0), v0.t
+	vsseg7e8.v v0, (a0), v0.t
+	vlseg7e8ff.v v0, (a0), v0.t
+	vlseg8e8.v v0, (a0), v0.t
+	vsseg8e8.v v0, (a0), v0.t
+	vlseg8e8ff.v v0, (a0), v0.t
+
+	vlseg2e16.v v0, (a0), v0.t
+	vsseg2e16.v v0, (a0), v0.t
+	vlseg2e16ff.v v0, (a0), v0.t
+	vlseg3e16.v v0, (a0), v0.t
+	vsseg3e16.v v0, (a0), v0.t
+	vlseg3e16ff.v v0, (a0), v0.t
+	vlseg4e16.v v0, (a0), v0.t
+	vsseg4e16.v v0, (a0), v0.t
+	vlseg4e16ff.v v0, (a0), v0.t
+	vlseg5e16.v v0, (a0), v0.t
+	vsseg5e16.v v0, (a0), v0.t
+	vlseg5e16ff.v v0, (a0), v0.t
+	vlseg6e16.v v0, (a0), v0.t
+	vsseg6e16.v v0, (a0), v0.t
+	vlseg6e16ff.v v0, (a0), v0.t
+	vlseg7e16.v v0, (a0), v0.t
+	vsseg7e16.v v0, (a0), v0.t
+	vlseg7e16ff.v v0, (a0), v0.t
+	vlseg8e16.v v0, (a0), v0.t
+	vsseg8e16.v v0, (a0), v0.t
+	vlseg8e16ff.v v0, (a0), v0.t
+
+	vlseg2e32.v v0, (a0), v0.t
+	vsseg2e32.v v0, (a0), v0.t
+	vlseg2e32ff.v v0, (a0), v0.t
+	vlseg3e32.v v0, (a0), v0.t
+	vsseg3e32.v v0, (a0), v0.t
+	vlseg3e32ff.v v0, (a0), v0.t
+	vlseg4e32.v v0, (a0), v0.t
+	vsseg4e32.v v0, (a0), v0.t
+	vlseg4e32ff.v v0, (a0), v0.t
+	vlseg5e32.v v0, (a0), v0.t
+	vsseg5e32.v v0, (a0), v0.t
+	vlseg5e32ff.v v0, (a0), v0.t
+	vlseg6e32.v v0, (a0), v0.t
+	vsseg6e32.v v0, (a0), v0.t
+	vlseg6e32ff.v v0, (a0), v0.t
+	vlseg7e32.v v0, (a0), v0.t
+	vsseg7e32.v v0, (a0), v0.t
+	vlseg7e32ff.v v0, (a0), v0.t
+	vlseg8e32.v v0, (a0), v0.t
+	vsseg8e32.v v0, (a0), v0.t
+	vlseg8e32ff.v v0, (a0), v0.t
+
+	vlseg2e64.v v0, (a0), v0.t
+	vsseg2e64.v v0, (a0), v0.t
+	vlseg2e64ff.v v0, (a0), v0.t
+	vlseg3e64.v v0, (a0), v0.t
+	vsseg3e64.v v0, (a0), v0.t
+	vlseg3e64ff.v v0, (a0), v0.t
+	vlseg4e64.v v0, (a0), v0.t
+	vsseg4e64.v v0, (a0), v0.t
+	vlseg4e64ff.v v0, (a0), v0.t
+	vlseg5e64.v v0, (a0), v0.t
+	vsseg5e64.v v0, (a0), v0.t
+	vlseg5e64ff.v v0, (a0), v0.t
+	vlseg6e64.v v0, (a0), v0.t
+	vsseg6e64.v v0, (a0), v0.t
+	vlseg6e64ff.v v0, (a0), v0.t
+	vlseg7e64.v v0, (a0), v0.t
+	vsseg7e64.v v0, (a0), v0.t
+	vlseg7e64ff.v v0, (a0), v0.t
+	vlseg8e64.v v0, (a0), v0.t
+	vsseg8e64.v v0, (a0), v0.t
+	vlseg8e64ff.v v0, (a0), v0.t
+
+# Vector Strided Segment Loads and Stores
+
+	vlsseg2e8.v v0, (a0), a1, v0.t		# vd overlap vm
+	vssseg2e8.v v0, (a0), a1, v0.t		# vd overlap vm
+	vlsseg3e8.v v0, (a0), a1, v0.t
+	vssseg3e8.v v0, (a0), a1, v0.t
+	vlsseg4e8.v v0, (a0), a1, v0.t
+	vssseg4e8.v v0, (a0), a1, v0.t
+	vlsseg5e8.v v0, (a0), a1, v0.t
+	vssseg5e8.v v0, (a0), a1, v0.t
+	vlsseg6e8.v v0, (a0), a1, v0.t
+	vssseg6e8.v v0, (a0), a1, v0.t
+	vlsseg7e8.v v0, (a0), a1, v0.t
+	vssseg7e8.v v0, (a0), a1, v0.t
+	vlsseg8e8.v v0, (a0), a1, v0.t
+	vssseg8e8.v v0, (a0), a1, v0.t
+
+	vlsseg2e16.v v0, (a0), a1, v0.t
+	vssseg2e16.v v0, (a0), a1, v0.t
+	vlsseg3e16.v v0, (a0), a1, v0.t
+	vssseg3e16.v v0, (a0), a1, v0.t
+	vlsseg4e16.v v0, (a0), a1, v0.t
+	vssseg4e16.v v0, (a0), a1, v0.t
+	vlsseg5e16.v v0, (a0), a1, v0.t
+	vssseg5e16.v v0, (a0), a1, v0.t
+	vlsseg6e16.v v0, (a0), a1, v0.t
+	vssseg6e16.v v0, (a0), a1, v0.t
+	vlsseg7e16.v v0, (a0), a1, v0.t
+	vssseg7e16.v v0, (a0), a1, v0.t
+	vlsseg8e16.v v0, (a0), a1, v0.t
+	vssseg8e16.v v0, (a0), a1, v0.t
+
+	vlsseg2e32.v v0, (a0), a1, v0.t
+	vssseg2e32.v v0, (a0), a1, v0.t
+	vlsseg3e32.v v0, (a0), a1, v0.t
+	vssseg3e32.v v0, (a0), a1, v0.t
+	vlsseg4e32.v v0, (a0), a1, v0.t
+	vssseg4e32.v v0, (a0), a1, v0.t
+	vlsseg5e32.v v0, (a0), a1, v0.t
+	vssseg5e32.v v0, (a0), a1, v0.t
+	vlsseg6e32.v v0, (a0), a1, v0.t
+	vssseg6e32.v v0, (a0), a1, v0.t
+	vlsseg7e32.v v0, (a0), a1, v0.t
+	vssseg7e32.v v0, (a0), a1, v0.t
+	vlsseg8e32.v v0, (a0), a1, v0.t
+	vssseg8e32.v v0, (a0), a1, v0.t
+
+	vlsseg2e64.v v0, (a0), a1, v0.t
+	vssseg2e64.v v0, (a0), a1, v0.t
+	vlsseg3e64.v v0, (a0), a1, v0.t
+	vssseg3e64.v v0, (a0), a1, v0.t
+	vlsseg4e64.v v0, (a0), a1, v0.t
+	vssseg4e64.v v0, (a0), a1, v0.t
+	vlsseg5e64.v v0, (a0), a1, v0.t
+	vssseg5e64.v v0, (a0), a1, v0.t
+	vlsseg6e64.v v0, (a0), a1, v0.t
+	vssseg6e64.v v0, (a0), a1, v0.t
+	vlsseg7e64.v v0, (a0), a1, v0.t
+	vssseg7e64.v v0, (a0), a1, v0.t
+	vlsseg8e64.v v0, (a0), a1, v0.t
+	vssseg8e64.v v0, (a0), a1, v0.t
+
+# Vector Ordered Indexed Segment Loads and Stores
+
+	vloxseg2ei8.v v4, (a0), v4		# vd overlap vs2
+	vloxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
+	vsoxseg2ei8.v v4, (a0), v4		# vd overlap vs2
+	vsoxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
+	vloxseg3ei8.v v4, (a0), v4
+	vloxseg3ei8.v v0, (a0), v4, v0.t
+	vsoxseg3ei8.v v4, (a0), v4
+	vsoxseg3ei8.v v0, (a0), v4, v0.t
+	vloxseg4ei8.v v4, (a0), v4
+	vloxseg4ei8.v v0, (a0), v4, v0.t
+	vsoxseg4ei8.v v4, (a0), v4
+	vsoxseg4ei8.v v0, (a0), v4, v0.t
+	vloxseg5ei8.v v4, (a0), v4
+	vloxseg5ei8.v v0, (a0), v4, v0.t
+	vsoxseg5ei8.v v4, (a0), v4
+	vsoxseg5ei8.v v0, (a0), v4, v0.t
+	vloxseg6ei8.v v4, (a0), v4
+	vloxseg6ei8.v v0, (a0), v4, v0.t
+	vsoxseg6ei8.v v4, (a0), v4
+	vsoxseg6ei8.v v0, (a0), v4, v0.t
+	vloxseg7ei8.v v4, (a0), v4
+	vloxseg7ei8.v v0, (a0), v4, v0.t
+	vsoxseg7ei8.v v4, (a0), v4
+	vsoxseg7ei8.v v0, (a0), v4, v0.t
+	vloxseg8ei8.v v4, (a0), v4
+	vloxseg8ei8.v v0, (a0), v4, v0.t
+	vsoxseg8ei8.v v4, (a0), v4
+	vsoxseg8ei8.v v0, (a0), v4, v0.t
+
+	vloxseg2ei16.v v4, (a0), v4
+	vloxseg2ei16.v v0, (a0), v4, v0.t
+	vsoxseg2ei16.v v4, (a0), v4
+	vsoxseg2ei16.v v0, (a0), v4, v0.t
+	vloxseg3ei16.v v4, (a0), v4
+	vloxseg3ei16.v v0, (a0), v4, v0.t
+	vsoxseg3ei16.v v4, (a0), v4
+	vsoxseg3ei16.v v0, (a0), v4, v0.t
+	vloxseg4ei16.v v4, (a0), v4
+	vloxseg4ei16.v v0, (a0), v4, v0.t
+	vsoxseg4ei16.v v4, (a0), v4
+	vsoxseg4ei16.v v0, (a0), v4, v0.t
+	vloxseg5ei16.v v4, (a0), v4
+	vloxseg5ei16.v v0, (a0), v4, v0.t
+	vsoxseg5ei16.v v4, (a0), v4
+	vsoxseg5ei16.v v0, (a0), v4, v0.t
+	vloxseg6ei16.v v4, (a0), v4
+	vloxseg6ei16.v v0, (a0), v4, v0.t
+	vsoxseg6ei16.v v4, (a0), v4
+	vsoxseg6ei16.v v0, (a0), v4, v0.t
+	vloxseg7ei16.v v4, (a0), v4
+	vloxseg7ei16.v v0, (a0), v4, v0.t
+	vsoxseg7ei16.v v4, (a0), v4
+	vsoxseg7ei16.v v0, (a0), v4, v0.t
+	vloxseg8ei16.v v4, (a0), v4
+	vloxseg8ei16.v v0, (a0), v4, v0.t
+	vsoxseg8ei16.v v4, (a0), v4
+	vsoxseg8ei16.v v0, (a0), v4, v0.t
+
+	vloxseg2ei32.v v4, (a0), v4
+	vloxseg2ei32.v v0, (a0), v4, v0.t
+	vsoxseg2ei32.v v4, (a0), v4
+	vsoxseg2ei32.v v0, (a0), v4, v0.t
+	vloxseg3ei32.v v4, (a0), v4
+	vloxseg3ei32.v v0, (a0), v4, v0.t
+	vsoxseg3ei32.v v4, (a0), v4
+	vsoxseg3ei32.v v0, (a0), v4, v0.t
+	vloxseg4ei32.v v4, (a0), v4
+	vloxseg4ei32.v v0, (a0), v4, v0.t
+	vsoxseg4ei32.v v4, (a0), v4
+	vsoxseg4ei32.v v0, (a0), v4, v0.t
+	vloxseg5ei32.v v4, (a0), v4
+	vloxseg5ei32.v v0, (a0), v4, v0.t
+	vsoxseg5ei32.v v4, (a0), v4
+	vsoxseg5ei32.v v0, (a0), v4, v0.t
+	vloxseg6ei32.v v4, (a0), v4
+	vloxseg6ei32.v v0, (a0), v4, v0.t
+	vsoxseg6ei32.v v4, (a0), v4
+	vsoxseg6ei32.v v0, (a0), v4, v0.t
+	vloxseg7ei32.v v4, (a0), v4
+	vloxseg7ei32.v v0, (a0), v4, v0.t
+	vsoxseg7ei32.v v4, (a0), v4
+	vsoxseg7ei32.v v0, (a0), v4, v0.t
+	vloxseg8ei32.v v4, (a0), v4
+	vloxseg8ei32.v v0, (a0), v4, v0.t
+	vsoxseg8ei32.v v4, (a0), v4
+	vsoxseg8ei32.v v0, (a0), v4, v0.t
+
+	vloxseg2ei64.v v4, (a0), v4
+	vloxseg2ei64.v v0, (a0), v4, v0.t
+	vsoxseg2ei64.v v4, (a0), v4
+	vsoxseg2ei64.v v0, (a0), v4, v0.t
+	vloxseg3ei64.v v4, (a0), v4
+	vloxseg3ei64.v v0, (a0), v4, v0.t
+	vsoxseg3ei64.v v4, (a0), v4
+	vsoxseg3ei64.v v0, (a0), v4, v0.t
+	vloxseg4ei64.v v4, (a0), v4
+	vloxseg4ei64.v v0, (a0), v4, v0.t
+	vsoxseg4ei64.v v4, (a0), v4
+	vsoxseg4ei64.v v0, (a0), v4, v0.t
+	vloxseg5ei64.v v4, (a0), v4
+	vloxseg5ei64.v v0, (a0), v4, v0.t
+	vsoxseg5ei64.v v4, (a0), v4
+	vsoxseg5ei64.v v0, (a0), v4, v0.t
+	vloxseg6ei64.v v4, (a0), v4
+	vloxseg6ei64.v v0, (a0), v4, v0.t
+	vsoxseg6ei64.v v4, (a0), v4
+	vsoxseg6ei64.v v0, (a0), v4, v0.t
+	vloxseg7ei64.v v4, (a0), v4
+	vloxseg7ei64.v v0, (a0), v4, v0.t
+	vsoxseg7ei64.v v4, (a0), v4
+	vsoxseg7ei64.v v0, (a0), v4, v0.t
+	vloxseg8ei64.v v4, (a0), v4
+	vloxseg8ei64.v v0, (a0), v4, v0.t
+	vsoxseg8ei64.v v4, (a0), v4
+	vsoxseg8ei64.v v0, (a0), v4, v0.t
+
+# Vector Unordered Indexed Segment Loads and Stores
+
+	vluxseg2ei8.v v4, (a0), v4		# vd overlap vs2
+	vluxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
+	vsuxseg2ei8.v v4, (a0), v4		# vd overlap vs2
+	vsuxseg2ei8.v v0, (a0), v4, v0.t	# vd overlap vm
+	vluxseg3ei8.v v4, (a0), v4
+	vluxseg3ei8.v v0, (a0), v4, v0.t
+	vsuxseg3ei8.v v4, (a0), v4
+	vsuxseg3ei8.v v0, (a0), v4, v0.t
+	vluxseg4ei8.v v4, (a0), v4
+	vluxseg4ei8.v v0, (a0), v4, v0.t
+	vsuxseg4ei8.v v4, (a0), v4
+	vsuxseg4ei8.v v0, (a0), v4, v0.t
+	vluxseg5ei8.v v4, (a0), v4
+	vluxseg5ei8.v v0, (a0), v4, v0.t
+	vsuxseg5ei8.v v4, (a0), v4
+	vsuxseg5ei8.v v0, (a0), v4, v0.t
+	vluxseg6ei8.v v4, (a0), v4
+	vluxseg6ei8.v v0, (a0), v4, v0.t
+	vsuxseg6ei8.v v4, (a0), v4
+	vsuxseg6ei8.v v0, (a0), v4, v0.t
+	vluxseg7ei8.v v4, (a0), v4
+	vluxseg7ei8.v v0, (a0), v4, v0.t
+	vsuxseg7ei8.v v4, (a0), v4
+	vsuxseg7ei8.v v0, (a0), v4, v0.t
+	vluxseg8ei8.v v4, (a0), v4
+	vluxseg8ei8.v v0, (a0), v4, v0.t
+	vsuxseg8ei8.v v4, (a0), v4
+	vsuxseg8ei8.v v0, (a0), v4, v0.t
+
+	vluxseg2ei16.v v4, (a0), v4
+	vluxseg2ei16.v v0, (a0), v4, v0.t
+	vsuxseg2ei16.v v4, (a0), v4
+	vsuxseg2ei16.v v0, (a0), v4, v0.t
+	vluxseg3ei16.v v4, (a0), v4
+	vluxseg3ei16.v v0, (a0), v4, v0.t
+	vsuxseg3ei16.v v4, (a0), v4
+	vsuxseg3ei16.v v0, (a0), v4, v0.t
+	vluxseg4ei16.v v4, (a0), v4
+	vluxseg4ei16.v v0, (a0), v4, v0.t
+	vsuxseg4ei16.v v4, (a0), v4
+	vsuxseg4ei16.v v0, (a0), v4, v0.t
+	vluxseg5ei16.v v4, (a0), v4
+	vluxseg5ei16.v v0, (a0), v4, v0.t
+	vsuxseg5ei16.v v4, (a0), v4
+	vsuxseg5ei16.v v0, (a0), v4, v0.t
+	vluxseg6ei16.v v4, (a0), v4
+	vluxseg6ei16.v v0, (a0), v4, v0.t
+	vsuxseg6ei16.v v4, (a0), v4
+	vsuxseg6ei16.v v0, (a0), v4, v0.t
+	vluxseg7ei16.v v4, (a0), v4
+	vluxseg7ei16.v v0, (a0), v4, v0.t
+	vsuxseg7ei16.v v4, (a0), v4
+	vsuxseg7ei16.v v0, (a0), v4, v0.t
+	vluxseg8ei16.v v4, (a0), v4
+	vluxseg8ei16.v v0, (a0), v4, v0.t
+	vsuxseg8ei16.v v4, (a0), v4
+	vsuxseg8ei16.v v0, (a0), v4, v0.t
+
+	vluxseg2ei32.v v4, (a0), v4
+	vluxseg2ei32.v v0, (a0), v4, v0.t
+	vsuxseg2ei32.v v4, (a0), v4
+	vsuxseg2ei32.v v0, (a0), v4, v0.t
+	vluxseg3ei32.v v4, (a0), v4
+	vluxseg3ei32.v v0, (a0), v4, v0.t
+	vsuxseg3ei32.v v4, (a0), v4
+	vsuxseg3ei32.v v0, (a0), v4, v0.t
+	vluxseg4ei32.v v4, (a0), v4
+	vluxseg4ei32.v v0, (a0), v4, v0.t
+	vsuxseg4ei32.v v4, (a0), v4
+	vsuxseg4ei32.v v0, (a0), v4, v0.t
+	vluxseg5ei32.v v4, (a0), v4
+	vluxseg5ei32.v v0, (a0), v4, v0.t
+	vsuxseg5ei32.v v4, (a0), v4
+	vsuxseg5ei32.v v0, (a0), v4, v0.t
+	vluxseg6ei32.v v4, (a0), v4
+	vluxseg6ei32.v v0, (a0), v4, v0.t
+	vsuxseg6ei32.v v4, (a0), v4
+	vsuxseg6ei32.v v0, (a0), v4, v0.t
+	vluxseg7ei32.v v4, (a0), v4
+	vluxseg7ei32.v v0, (a0), v4, v0.t
+	vsuxseg7ei32.v v4, (a0), v4
+	vsuxseg7ei32.v v0, (a0), v4, v0.t
+	vluxseg8ei32.v v4, (a0), v4
+	vluxseg8ei32.v v0, (a0), v4, v0.t
+	vsuxseg8ei32.v v4, (a0), v4
+	vsuxseg8ei32.v v0, (a0), v4, v0.t
+
+	vluxseg2ei64.v v4, (a0), v4
+	vluxseg2ei64.v v0, (a0), v4, v0.t
+	vsuxseg2ei64.v v4, (a0), v4
+	vsuxseg2ei64.v v0, (a0), v4, v0.t
+	vluxseg3ei64.v v4, (a0), v4
+	vluxseg3ei64.v v0, (a0), v4, v0.t
+	vsuxseg3ei64.v v4, (a0), v4
+	vsuxseg3ei64.v v0, (a0), v4, v0.t
+	vluxseg4ei64.v v4, (a0), v4
+	vluxseg4ei64.v v0, (a0), v4, v0.t
+	vsuxseg4ei64.v v4, (a0), v4
+	vsuxseg4ei64.v v0, (a0), v4, v0.t
+	vluxseg5ei64.v v4, (a0), v4
+	vluxseg5ei64.v v0, (a0), v4, v0.t
+	vsuxseg5ei64.v v4, (a0), v4
+	vsuxseg5ei64.v v0, (a0), v4, v0.t
+	vluxseg6ei64.v v4, (a0), v4
+	vluxseg6ei64.v v0, (a0), v4, v0.t
+	vsuxseg6ei64.v v4, (a0), v4
+	vsuxseg6ei64.v v0, (a0), v4, v0.t
+	vluxseg7ei64.v v4, (a0), v4
+	vluxseg7ei64.v v0, (a0), v4, v0.t
+	vsuxseg7ei64.v v4, (a0), v4
+	vsuxseg7ei64.v v0, (a0), v4, v0.t
+	vluxseg8ei64.v v4, (a0), v4
+	vluxseg8ei64.v v0, (a0), v4, v0.t
+	vsuxseg8ei64.v v4, (a0), v4
+	vsuxseg8ei64.v v0, (a0), v4, v0.t
+
+# Vector Load/Store Whole Register Instructions
+
+	vl1r.v v31, (a0)		# OK
+
+	vl2r.v v31, (a0)		# vd must be aligned to 2
+	vl2re8.v v31, (a0)
+	vl2re16.v v31, (a0)
+	vl2re32.v v31, (a0)
+	vl2re64.v v31, (a0)
+
+	vl4r.v v30, (a0)		# vd must be aligned to 4
+	vl4re8.v v30, (a0)
+	vl4re16.v v30, (a0)
+	vl4re32.v v30, (a0)
+	vl4re64.v v30, (a0)
+
+	vl8r.v v26, (a0)		# vd must be aligned to 8
+	vl8re8.v v26, (a0)
+	vl8re16.v v26, (a0)
+	vl8re32.v v26, (a0)
+	vl8re64.v v26, (a0)
+
+	vs2r.v v31, (a0)		# vs3 must be aligned to 2
+	vs4r.v v30, (a0)		# vs3 must be aligned to 4
+	vs8r.v v26, (a0)		# vs3 must be aligned to 8
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-mask.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-mask.d
new file mode 100644
index 0000000..35f9e2c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-mask.d
@@ -0,0 +1,3 @@
+#as: -march=rv32iv -mcheck-constraints
+#source: vector-insns-fail-mask.s
+#error_output: vector-insns-fail-mask.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-mask.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-mask.l
new file mode 100644
index 0000000..7ff5a3c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-mask.l
@@ -0,0 +1,10 @@
+.*: Assembler messages:
+.*Error: illegal operands vd cannot overlap vs2 `vmsbf.m v4,v4'
+.*Error: illegal operands vd cannot overlap vm `vmsbf.m v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vmsif.m v4,v4'
+.*Error: illegal operands vd cannot overlap vm `vmsif.m v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vmsof.m v4,v4'
+.*Error: illegal operands vd cannot overlap vm `vmsof.m v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `viota.m v4,v4'
+.*Error: illegal operands vd cannot overlap vm `viota.m v0,v4,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vid.v v0,v0.t'
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-mask.s b/gas/testsuite/gas/riscv/extended/vector-insns-fail-mask.s
new file mode 100644
index 0000000..99b19f6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-mask.s
@@ -0,0 +1,23 @@
+# Vector Set-before-first Mask Bit
+
+	vmsbf.m v4, v4		# vd overlap vs2
+	vmsbf.m v0, v4, v0.t	# vd overlap vm
+
+# Vector Set-including-first Mask Bit
+
+	vmsif.m v4, v4		# vd overlap vs2
+	vmsif.m v0, v4, v0.t	# vd overlap vm
+
+# Vector Set-only-first Mask Bit
+
+	vmsof.m v4, v4		# vd overlap vs2
+	vmsof.m v0, v4, v0.t	# vd overlap vm
+
+# Vector Iota Instruction
+
+	viota.m v4, v4		# vd overlap vs2
+	viota.m v0, v4, v0.t	# vd overlap vm
+
+# Vector Element Index Instruction
+
+	vid.v v0, v0.t		# vd overlap vm
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-permutation.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-permutation.d
new file mode 100644
index 0000000..9822e29
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-permutation.d
@@ -0,0 +1,3 @@
+#as: -march=rv32ifv -mcheck-constraints
+#source: vector-insns-fail-permutation.s
+#error_output: vector-insns-fail-permutation.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-permutation.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-permutation.l
new file mode 100644
index 0000000..1ea27f2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-permutation.l
@@ -0,0 +1,31 @@
+.*: Assembler messages:
+.*Error: illegal operands vd cannot overlap vs2 `vslideup.vx v4,v4,a1'
+.*Error: illegal operands vd cannot overlap vm `vslideup.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vslideup.vi v4,v4,31'
+.*Error: illegal operands vd cannot overlap vm `vslideup.vi v0,v4,31,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vslidedown.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vslidedown.vi v0,v4,31,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vslide1up.vx v4,v4,a1'
+.*Error: illegal operands vd cannot overlap vm `vslide1up.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vfslide1up.vf v4,v4,fa1'
+.*Error: illegal operands vd cannot overlap vm `vfslide1up.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vslide1down.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vfslide1down.vf v0,v4,fa1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vrgather.vv v4,v4,v8'
+.*Error: illegal operands vd cannot overlap vs1 `vrgather.vv v8,v4,v8'
+.*Error: illegal operands vd cannot overlap vm `vrgather.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vrgather.vx v4,v4,a1'
+.*Error: illegal operands vd cannot overlap vm `vrgather.vx v0,v4,a1,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vrgather.vi v4,v4,31'
+.*Error: illegal operands vd cannot overlap vm `vrgather.vi v0,v4,31,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vrgatherei16.vv v4,v4,v8'
+.*Error: illegal operands vd cannot overlap vs1 `vrgatherei16.vv v8,v4,v8'
+.*Error: illegal operands vd cannot overlap vm `vrgatherei16.vv v0,v4,v8,v0.t'
+.*Error: illegal operands vd cannot overlap vs2 `vcompress.vm v4,v4,v8'
+.*Error: illegal operands vd cannot overlap vs1 `vcompress.vm v8,v4,v8'
+.*Error: illegal operands vs2 must be multiple of nf `vmv2r.v v30,v31'
+.*Error: illegal operands vd must be multiple of nf `vmv2r.v v31,v30'
+.*Error: illegal operands vs2 must be multiple of nf `vmv4r.v v28,v30'
+.*Error: illegal operands vd must be multiple of nf `vmv4r.v v30,v28'
+.*Error: illegal operands vs2 must be multiple of nf `vmv8r.v v24,v26'
+.*Error: illegal operands vd must be multiple of nf `vmv8r.v v26,v24'
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-permutation.s b/gas/testsuite/gas/riscv/extended/vector-insns-fail-permutation.s
new file mode 100644
index 0000000..8511645
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-permutation.s
@@ -0,0 +1,56 @@
+# Vector Slideup Instructions
+
+	vslideup.vx v4, v4, a1			# vd overlap vs2
+	vslideup.vx v0, v4, a1, v0.t		# vd overlap vm
+	vslideup.vi v4, v4, 31			# vd overlap vs2
+	vslideup.vi v0, v4, 31, v0.t		# vd overlap vm
+
+	vslidedown.vx v4, v4, a1		# OK
+	vslidedown.vx v0, v4, a1, v0.t		# vd overlap vm
+	vslidedown.vi v4, v4, 31		# OK
+	vslidedown.vi v0, v4, 31, v0.t		# vd overlap vm
+
+	vslide1up.vx v4, v4, a1			# vd overlap vs2
+	vslide1up.vx v0, v4, a1, v0.t		# vd overlap vm
+	vfslide1up.vf v4, v4, fa1		# vd overlap vs2
+	vfslide1up.vf v0, v4, fa1, v0.t		# vd overlap vm
+
+	vslide1down.vx v4, v4, a1		# OK
+	vslide1down.vx v0, v4, a1, v0.t		# vd overlap vm
+	vfslide1down.vf v4, v4, fa1		# OK
+	vfslide1down.vf v0, v4, fa1, v0.t	# vd overlap vm
+
+# Vector Register Gather Instructions
+
+	vrgather.vv v4, v4, v8			# vd overlap vs2
+	vrgather.vv v8, v4, v8			# vd overlap vs1
+	vrgather.vv v0, v4, v8, v0.t		# vd overlap vm
+	vrgather.vx v4, v4, a1			# vd overlap vs2
+	vrgather.vx v0, v4, a1, v0.t		# vd overlap vm
+	vrgather.vi v4, v4, 31			# vd overlap vs2
+	vrgather.vi v0, v4, 31, v0.t		# vd overlap vm
+
+	vrgatherei16.vv v4, v4, v8		# vd overlap vs2
+	vrgatherei16.vv v8, v4, v8		# vd overlap vs1
+	vrgatherei16.vv v0, v4, v8, v0.t	# vd overlap vm
+
+# Vector Compress Instruction
+
+	vcompress.vm v4, v4, v8			# vd overlap vs2
+	vcompress.vm v8, v4, v8			# vd overlap vs1
+
+# Whole Vector Register Move
+
+	vmv1r.v v31, v31			# OK, HINT
+
+	vmv2r.v v30, v30			# OK, HINT
+	vmv2r.v v30, v31			# vs2 must be aligned to 2
+	vmv2r.v v31, v30			# vd must be aligned to 2
+
+	vmv4r.v v28, v28			# OK, HINT
+	vmv4r.v v28, v30			# vs2 must be aligned to 4
+	vmv4r.v v30, v28			# vd must be aligned to 4
+
+	vmv8r.v v24, v24			# OK, HINT
+	vmv8r.v v24, v26			# vs2 must be aligned to 8
+	vmv8r.v v26, v24			# vd must be aligned to 8
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d
new file mode 100644
index 0000000..5749449
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.d
@@ -0,0 +1,3 @@
+#as: -march=rv32iav -mcheck-constraints
+#source: vector-insns-fail-zvamo.s
+#error_output: vector-insns-fail-zvamo.l
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.l b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.l
new file mode 100644
index 0000000..ae414f7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.l
@@ -0,0 +1,109 @@
+.*: Assembler messages:
+.*Error: illegal operands `vamoaddei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoswapei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoxorei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoandei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoandei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoandei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoorei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoorei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoorei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominuei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominuei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominuei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxuei8.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei8.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei8.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoaddei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoswapei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoxorei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoandei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoandei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoandei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoorei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoorei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoorei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominuei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominuei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominuei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei16.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxuei16.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei16.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoaddei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoswapei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoxorei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoandei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoandei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoandei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoorei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoorei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoorei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominuei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominuei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominuei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxuei32.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei32.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei32.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoaddei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoaddei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoswapei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoswapei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoxorei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoxorei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoandei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoandei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoandei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamoorei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamoorei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamoorei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamominuei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamominuei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamominuei64.v x0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands `vamomaxuei64.v v4,\(a1\),v4,v0'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei64.v v0,\(a1\),v4,v0,v0.t'
+.*Error: illegal operands vd cannot overlap vm `vamomaxuei64.v x0,\(a1\),v4,v0,v0.t'
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.s b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.s
new file mode 100644
index 0000000..0fd3c26
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-fail-zvamo.s
@@ -0,0 +1,217 @@
+# Vector AMO Operations
+
+	vamoaddei8.v v0, (a1), v4, v0		# OK
+	vamoaddei8.v v4, (a1), v4, v0		# vd must match vs3
+	vamoaddei8.v v0, (a1), v4, v0, v0.t	# vd overlap vm
+	vamoaddei8.v x0, (a1), v4, v0		# OK
+	vamoaddei8.v x0, (a1), v4, v0, v0.t	# vs3 overlap vm
+
+	vamoswapei8.v v0, (a1), v4, v0
+	vamoswapei8.v v4, (a1), v4, v0
+	vamoswapei8.v v0, (a1), v4, v0, v0.t
+	vamoswapei8.v x0, (a1), v4, v0
+	vamoswapei8.v x0, (a1), v4, v0, v0.t
+
+	vamoxorei8.v v0, (a1), v4, v0
+	vamoxorei8.v v4, (a1), v4, v0
+	vamoxorei8.v v0, (a1), v4, v0, v0.t
+	vamoxorei8.v x0, (a1), v4, v0
+	vamoxorei8.v x0, (a1), v4, v0, v0.t
+
+	vamoandei8.v v0, (a1), v4, v0
+	vamoandei8.v v4, (a1), v4, v0
+	vamoandei8.v v0, (a1), v4, v0, v0.t
+	vamoandei8.v x0, (a1), v4, v0
+	vamoandei8.v x0, (a1), v4, v0, v0.t
+
+	vamoorei8.v v0, (a1), v4, v0
+	vamoorei8.v v4, (a1), v4, v0
+	vamoorei8.v v0, (a1), v4, v0, v0.t
+	vamoorei8.v x0, (a1), v4, v0
+	vamoorei8.v x0, (a1), v4, v0, v0.t
+
+	vamominei8.v v0, (a1), v4, v0
+	vamominei8.v v4, (a1), v4, v0
+	vamominei8.v v0, (a1), v4, v0, v0.t
+	vamominei8.v x0, (a1), v4, v0
+	vamominei8.v x0, (a1), v4, v0, v0.t
+
+	vamomaxei8.v v0, (a1), v4, v0
+	vamomaxei8.v v4, (a1), v4, v0
+	vamomaxei8.v v0, (a1), v4, v0, v0.t
+	vamomaxei8.v x0, (a1), v4, v0
+	vamomaxei8.v x0, (a1), v4, v0, v0.t
+
+	vamominuei8.v v0, (a1), v4, v0
+	vamominuei8.v v4, (a1), v4, v0
+	vamominuei8.v v0, (a1), v4, v0, v0.t
+	vamominuei8.v x0, (a1), v4, v0
+	vamominuei8.v x0, (a1), v4, v0, v0.t
+
+	vamomaxuei8.v v0, (a1), v4, v0
+	vamomaxuei8.v v4, (a1), v4, v0
+	vamomaxuei8.v v0, (a1), v4, v0, v0.t
+	vamomaxuei8.v x0, (a1), v4, v0
+	vamomaxuei8.v x0, (a1), v4, v0, v0.t
+
+	vamoaddei16.v v0, (a1), v4, v0
+	vamoaddei16.v v4, (a1), v4, v0
+	vamoaddei16.v v0, (a1), v4, v0, v0.t
+	vamoaddei16.v x0, (a1), v4, v0
+	vamoaddei16.v x0, (a1), v4, v0, v0.t
+
+	vamoswapei16.v v0, (a1), v4, v0
+	vamoswapei16.v v0, (a1), v4, v0, v0.t
+	vamoswapei16.v v4, (a1), v4, v0
+	vamoswapei16.v x0, (a1), v4, v0
+	vamoswapei16.v x0, (a1), v4, v0, v0.t
+
+	vamoxorei16.v v0, (a1), v4, v0
+	vamoxorei16.v v0, (a1), v4, v0, v0.t
+	vamoxorei16.v v4, (a1), v4, v0
+	vamoxorei16.v x0, (a1), v4, v0
+	vamoxorei16.v x0, (a1), v4, v0, v0.t
+
+	vamoandei16.v v0, (a1), v4, v0
+	vamoandei16.v v0, (a1), v4, v0, v0.t
+	vamoandei16.v v4, (a1), v4, v0
+	vamoandei16.v x0, (a1), v4, v0
+	vamoandei16.v x0, (a1), v4, v0, v0.t
+
+	vamoorei16.v v0, (a1), v4, v0
+	vamoorei16.v v0, (a1), v4, v0, v0.t
+	vamoorei16.v v4, (a1), v4, v0
+	vamoorei16.v x0, (a1), v4, v0
+	vamoorei16.v x0, (a1), v4, v0, v0.t
+
+	vamominei16.v v0, (a1), v4, v0
+	vamominei16.v v0, (a1), v4, v0, v0.t
+	vamominei16.v v4, (a1), v4, v0
+	vamominei16.v x0, (a1), v4, v0
+	vamominei16.v x0, (a1), v4, v0, v0.t
+
+	vamomaxei16.v v0, (a1), v4, v0
+	vamomaxei16.v v0, (a1), v4, v0, v0.t
+	vamomaxei16.v v4, (a1), v4, v0
+	vamomaxei16.v x0, (a1), v4, v0
+	vamomaxei16.v x0, (a1), v4, v0, v0.t
+
+	vamominuei16.v v0, (a1), v4, v0
+	vamominuei16.v v0, (a1), v4, v0, v0.t
+	vamominuei16.v v4, (a1), v4, v0
+	vamominuei16.v x0, (a1), v4, v0
+	vamominuei16.v x0, (a1), v4, v0, v0.t
+
+	vamomaxuei16.v v0, (a1), v4, v0
+	vamomaxuei16.v v0, (a1), v4, v0, v0.t
+	vamomaxuei16.v v4, (a1), v4, v0
+	vamomaxuei16.v x0, (a1), v4, v0
+	vamomaxuei16.v x0, (a1), v4, v0, v0.t
+
+	vamoaddei32.v v0, (a1), v4, v0
+	vamoaddei32.v v0, (a1), v4, v0, v0.t
+	vamoaddei32.v v4, (a1), v4, v0
+	vamoaddei32.v x0, (a1), v4, v0
+	vamoaddei32.v x0, (a1), v4, v0, v0.t
+
+	vamoswapei32.v v0, (a1), v4, v0
+	vamoswapei32.v v4, (a1), v4, v0
+	vamoswapei32.v v0, (a1), v4, v0, v0.t
+	vamoswapei32.v x0, (a1), v4, v0
+	vamoswapei32.v x0, (a1), v4, v0, v0.t
+
+	vamoxorei32.v v0, (a1), v4, v0
+	vamoxorei32.v v4, (a1), v4, v0
+	vamoxorei32.v v0, (a1), v4, v0, v0.t
+	vamoxorei32.v x0, (a1), v4, v0
+	vamoxorei32.v x0, (a1), v4, v0, v0.t
+
+	vamoandei32.v v0, (a1), v4, v0
+	vamoandei32.v v4, (a1), v4, v0
+	vamoandei32.v v0, (a1), v4, v0, v0.t
+	vamoandei32.v x0, (a1), v4, v0
+	vamoandei32.v x0, (a1), v4, v0, v0.t
+
+	vamoorei32.v v0, (a1), v4, v0
+	vamoorei32.v v4, (a1), v4, v0
+	vamoorei32.v v0, (a1), v4, v0, v0.t
+	vamoorei32.v x0, (a1), v4, v0
+	vamoorei32.v x0, (a1), v4, v0, v0.t
+
+	vamominei32.v v0, (a1), v4, v0
+	vamominei32.v v4, (a1), v4, v0
+	vamominei32.v v0, (a1), v4, v0, v0.t
+	vamominei32.v x0, (a1), v4, v0
+	vamominei32.v x0, (a1), v4, v0, v0.t
+
+	vamomaxei32.v v0, (a1), v4, v0
+	vamomaxei32.v v4, (a1), v4, v0
+	vamomaxei32.v v0, (a1), v4, v0, v0.t
+	vamomaxei32.v x0, (a1), v4, v0
+	vamomaxei32.v x0, (a1), v4, v0, v0.t
+
+	vamominuei32.v v0, (a1), v4, v0
+	vamominuei32.v v4, (a1), v4, v0
+	vamominuei32.v v0, (a1), v4, v0, v0.t
+	vamominuei32.v x0, (a1), v4, v0
+	vamominuei32.v x0, (a1), v4, v0, v0.t
+
+	vamomaxuei32.v v0, (a1), v4, v0
+	vamomaxuei32.v v4, (a1), v4, v0
+	vamomaxuei32.v v0, (a1), v4, v0, v0.t
+	vamomaxuei32.v x0, (a1), v4, v0
+	vamomaxuei32.v x0, (a1), v4, v0, v0.t
+
+	vamoaddei64.v v0, (a1), v4, v0
+	vamoaddei64.v v4, (a1), v4, v0
+	vamoaddei64.v v0, (a1), v4, v0, v0.t
+	vamoaddei64.v x0, (a1), v4, v0
+	vamoaddei64.v x0, (a1), v4, v0, v0.t
+
+	vamoswapei64.v v0, (a1), v4, v0
+	vamoswapei64.v v4, (a1), v4, v0
+	vamoswapei64.v v0, (a1), v4, v0, v0.t
+	vamoswapei64.v x0, (a1), v4, v0
+	vamoswapei64.v x0, (a1), v4, v0, v0.t
+
+	vamoxorei64.v v0, (a1), v4, v0
+	vamoxorei64.v v4, (a1), v4, v0
+	vamoxorei64.v v0, (a1), v4, v0, v0.t
+	vamoxorei64.v x0, (a1), v4, v0
+	vamoxorei64.v x0, (a1), v4, v0, v0.t
+
+	vamoandei64.v v0, (a1), v4, v0
+	vamoandei64.v v4, (a1), v4, v0
+	vamoandei64.v v0, (a1), v4, v0, v0.t
+	vamoandei64.v x0, (a1), v4, v0
+	vamoandei64.v x0, (a1), v4, v0, v0.t
+
+	vamoorei64.v v0, (a1), v4, v0
+	vamoorei64.v v4, (a1), v4, v0
+	vamoorei64.v v0, (a1), v4, v0, v0.t
+	vamoorei64.v x0, (a1), v4, v0
+	vamoorei64.v x0, (a1), v4, v0, v0.t
+
+	vamominei64.v v0, (a1), v4, v0
+	vamominei64.v v4, (a1), v4, v0
+	vamominei64.v v0, (a1), v4, v0, v0.t
+	vamominei64.v x0, (a1), v4, v0
+	vamominei64.v x0, (a1), v4, v0, v0.t
+
+	vamomaxei64.v v0, (a1), v4, v0
+	vamomaxei64.v v4, (a1), v4, v0
+	vamomaxei64.v v0, (a1), v4, v0, v0.t
+	vamomaxei64.v x0, (a1), v4, v0
+	vamomaxei64.v x0, (a1), v4, v0, v0.t
+
+	vamominuei64.v v0, (a1), v4, v0
+	vamominuei64.v v4, (a1), v4, v0
+	vamominuei64.v v0, (a1), v4, v0, v0.t
+	vamominuei64.v x0, (a1), v4, v0
+	vamominuei64.v x0, (a1), v4, v0, v0.t
+
+	vamomaxuei64.v v0, (a1), v4, v0
+	vamomaxuei64.v v4, (a1), v4, v0
+	vamomaxuei64.v v0, (a1), v4, v0, v0.t
+	vamomaxuei64.v x0, (a1), v4, v0
+	vamomaxuei64.v x0, (a1), v4, v0, v0.t
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d b/gas/testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d
new file mode 100644
index 0000000..4d33fe7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-vmsgtvx.d
@@ -0,0 +1,29 @@
+#as: -march=rv32iv
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+6e85c257[ 	]+vmslt.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+76422257[ 	]+vmnot.m[ 	]+v4,v4
+[ 	]+[0-9a-f]+:[ 	]+6cc64457[ 	]+vmslt.vx[ 	]+v8,v12,a2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+6e802457[ 	]+vmxor.mm[ 	]+v8,v8,v0
+[ 	]+[0-9a-f]+:[ 	]+6c85c657[ 	]+vmslt.vx[ 	]+v12,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandnot.mm[ 	]+v0,v0,v12
+[ 	]+[0-9a-f]+:[ 	]+6c85c657[ 	]+vmslt.vx[ 	]+v12,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandnot.mm[ 	]+v12,v0,v12
+[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandnot.mm[ 	]+v4,v4,v0
+[ 	]+[0-9a-f]+:[ 	]+6ac22257[ 	]+vmor.mm[ 	]+v4,v12,v4
+[ 	]+[0-9a-f]+:[ 	]+6a85c257[ 	]+vmsltu.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+76422257[ 	]+vmnot.m[ 	]+v4,v4
+[ 	]+[0-9a-f]+:[ 	]+68c64457[ 	]+vmsltu.vx[ 	]+v8,v12,a2,v0.t
+[ 	]+[0-9a-f]+:[ 	]+6e802457[ 	]+vmxor.mm[ 	]+v8,v8,v0
+[ 	]+[0-9a-f]+:[ 	]+6885c657[ 	]+vmsltu.vx[ 	]+v12,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+62062057[ 	]+vmandnot.mm[ 	]+v0,v0,v12
+[ 	]+[0-9a-f]+:[ 	]+6885c657[ 	]+vmsltu.vx[ 	]+v12,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+62062657[ 	]+vmandnot.mm[ 	]+v12,v0,v12
+[ 	]+[0-9a-f]+:[ 	]+62402257[ 	]+vmandnot.mm[ 	]+v4,v4,v0
+[ 	]+[0-9a-f]+:[ 	]+6ac22257[ 	]+vmor.mm[ 	]+v4,v12,v4
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-vmsgtvx.s b/gas/testsuite/gas/riscv/extended/vector-insns-vmsgtvx.s
new file mode 100644
index 0000000..afbb7cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-vmsgtvx.s
@@ -0,0 +1,9 @@
+	vmsge.vx v4, v8, a1		# unmasked va >= x
+	vmsge.vx v8, v12, a2, v0.t	# masked va >= x, vd != v0
+	vmsge.vx v0, v8, a1, v0.t, v12	# masked va >= x, vd == v0
+	vmsge.vx v4, v8, a1, v0.t, v12	# masked va >= x, any vd
+
+	vmsgeu.vx v4, v8, a1		# unmasked va >= x
+	vmsgeu.vx v8, v12, a2, v0.t	# masked va >= x, vd != v0
+	vmsgeu.vx v0, v8, a1, v0.t, v12	# masked va >= x, vd == v0
+	vmsgeu.vx v4, v8, a1, v0.t, v12	# masked va >= x, any vd
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-zero-imm.d b/gas/testsuite/gas/riscv/extended/vector-insns-zero-imm.d
new file mode 100644
index 0000000..f6fe2ff
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-zero-imm.d
@@ -0,0 +1,17 @@
+#as: -march=rv32ifv
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+768fb257[ 	]+vmsle.vi[ 	]+v4,v8,-1
+[ 	]+[0-9a-f]+:[ 	]+748fb257[ 	]+vmsle.vi[ 	]+v4,v8,-1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+66840257[ 	]+vmsne.vv[ 	]+v4,v8,v8
+[ 	]+[0-9a-f]+:[ 	]+64840257[ 	]+vmsne.vv[ 	]+v4,v8,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+7e8fb257[ 	]+vmsgt.vi[ 	]+v4,v8,-1
+[ 	]+[0-9a-f]+:[ 	]+7c8fb257[ 	]+vmsgt.vi[ 	]+v4,v8,-1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+62840257[ 	]+vmseq.vv[ 	]+v4,v8,v8
+[ 	]+[0-9a-f]+:[ 	]+60840257[ 	]+vmseq.vv[ 	]+v4,v8,v8,v0.t
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns-zero-imm.s b/gas/testsuite/gas/riscv/extended/vector-insns-zero-imm.s
new file mode 100644
index 0000000..98b7063
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns-zero-imm.s
@@ -0,0 +1,8 @@
+	vmslt.vi v4, v8, 0
+	vmslt.vi v4, v8, 0, v0.t
+	vmsltu.vi v4, v8, 0
+	vmsltu.vi v4, v8, 0, v0.t
+	vmsge.vi v4, v8, 0
+	vmsge.vi v4, v8, 0, v0.t
+	vmsgeu.vi v4, v8, 0
+	vmsgeu.vi v4, v8, 0, v0.t
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.d b/gas/testsuite/gas/riscv/extended/vector-insns.d
new file mode 100644
index 0000000..01770c4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns.d
@@ -0,0 +1,1942 @@
+#as: -march=rv32iafv
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+80c5f557[ 	]+vsetvl[ 	]+a0,a1,a2
+[ 	]+[0-9a-f]+:[ 	]+0005f557[ 	]+vsetvli[ 	]+a0,a1,e8,m1,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+7ff5f557[ 	]+vsetvli[ 	]+a0,a1,2047
+[ 	]+[0-9a-f]+:[ 	]+0095f557[ 	]+vsetvli[ 	]+a0,a1,e16,m2,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+02b5f557[ 	]+vsetvli[ 	]+a0,a1,e256,m8,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+0335f557[ 	]+vsetvli[ 	]+a0,a1,e512,m8,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+03b5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,m8,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+0385f557[ 	]+vsetvli[ 	]+a0,a1,e1024,m1,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+03f5f557[ 	]+vsetvli[ 	]+a0,a1,e1024,mf2,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+0365f557[ 	]+vsetvli[ 	]+a0,a1,e512,mf4,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+02d5f557[ 	]+vsetvli[ 	]+a0,a1,e256,mf8,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+0695f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,mu
+[ 	]+[0-9a-f]+:[ 	]+0a95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,ma
+[ 	]+[0-9a-f]+:[ 	]+0295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+0295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+0e95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,ma
+[ 	]+[0-9a-f]+:[ 	]+0a95f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,ma
+[ 	]+[0-9a-f]+:[ 	]+0695f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,ta,mu
+[ 	]+[0-9a-f]+:[ 	]+0295f557[ 	]+vsetvli[ 	]+a0,a1,e256,m2,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+c005f557[ 	]+vsetivli[ 	]+a0,11,e8,m1,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+fff5f557[ 	]+vsetivli[ 	]+a0,11,e1024,mf2,ta,ma
+[ 	]+[0-9a-f]+:[ 	]+c095f557[ 	]+vsetivli[ 	]+a0,11,e16,m2,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+c2b5f557[ 	]+vsetivli[ 	]+a0,11,e256,m8,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+c335f557[ 	]+vsetivli[ 	]+a0,11,e512,m8,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+c3b5f557[ 	]+vsetivli[ 	]+a0,11,e1024,m8,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+c385f557[ 	]+vsetivli[ 	]+a0,11,e1024,m1,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+c3f5f557[ 	]+vsetivli[ 	]+a0,11,e1024,mf2,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+c365f557[ 	]+vsetivli[ 	]+a0,11,e512,mf4,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+c2d5f557[ 	]+vsetivli[ 	]+a0,11,e256,mf8,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+c695f557[ 	]+vsetivli[ 	]+a0,11,e256,m2,ta,mu
+[ 	]+[0-9a-f]+:[ 	]+ca95f557[ 	]+vsetivli[ 	]+a0,11,e256,m2,tu,ma
+[ 	]+[0-9a-f]+:[ 	]+c295f557[ 	]+vsetivli[ 	]+a0,11,e256,m2,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+c295f557[ 	]+vsetivli[ 	]+a0,11,e256,m2,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+ce95f557[ 	]+vsetivli[ 	]+a0,11,e256,m2,ta,ma
+[ 	]+[0-9a-f]+:[ 	]+ca95f557[ 	]+vsetivli[ 	]+a0,11,e256,m2,tu,ma
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+[ 	]+[0-9a-f]+:[ 	]+c2860257[ 	]+vwredsumu.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+c6860257[ 	]+vwredsum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+c0860257[ 	]+vwredsumu.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c4860257[ 	]+vwredsum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0e861257[ 	]+vfredosum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+06861257[ 	]+vfredsum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+1e861257[ 	]+vfredmax.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+16861257[ 	]+vfredmin.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+0c861257[ 	]+vfredosum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+04861257[ 	]+vfredsum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+1c861257[ 	]+vfredmax.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+14861257[ 	]+vfredmin.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ce861257[ 	]+vfwredosum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+c6861257[ 	]+vfwredsum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+cc861257[ 	]+vfwredosum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c4861257[ 	]+vfwredsum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+66842257[ 	]+vmmv.m[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+66842257[ 	]+vmmv.m[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+6e422257[ 	]+vmclr.m[ 	]+v4
+[ 	]+[0-9a-f]+:[ 	]+7e422257[ 	]+vmset.m[ 	]+v4
+[ 	]+[0-9a-f]+:[ 	]+76842257[ 	]+vmnot.m[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+66862257[ 	]+vmand.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+76862257[ 	]+vmnand.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+62862257[ 	]+vmandnot.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+6e862257[ 	]+vmxor.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+6a862257[ 	]+vmor.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+7a862257[ 	]+vmnor.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+72862257[ 	]+vmornot.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+7e862257[ 	]+vmxnor.mm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+42c82557[ 	]+vpopc.m[ 	]+a0,v12
+[ 	]+[0-9a-f]+:[ 	]+42c8a557[ 	]+vfirst.m[ 	]+a0,v12
+[ 	]+[0-9a-f]+:[ 	]+5280a257[ 	]+vmsbf.m[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+5281a257[ 	]+vmsif.m[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+52812257[ 	]+vmsof.m[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+52882257[ 	]+viota.m[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+5208a257[ 	]+vid.v[ 	]+v4
+[ 	]+[0-9a-f]+:[ 	]+40c82557[ 	]+vpopc.m[ 	]+a0,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+40c8a557[ 	]+vfirst.m[ 	]+a0,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5080a257[ 	]+vmsbf.m[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5081a257[ 	]+vmsif.m[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+50812257[ 	]+vmsof.m[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+50882257[ 	]+viota.m[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5008a257[ 	]+vid.v[ 	]+v4,v0.t
+[ 	]+[0-9a-f]+:[ 	]+42c02557[ 	]+vmv.x.s[ 	]+a0,v12
+[ 	]+[0-9a-f]+:[ 	]+42056257[ 	]+vmv.s.x[ 	]+v4,a0
+[ 	]+[0-9a-f]+:[ 	]+42801557[ 	]+vfmv.f.s[ 	]+fa0,v8
+[ 	]+[0-9a-f]+:[ 	]+4205d257[ 	]+vfmv.s.f[ 	]+v4,fa1
+[ 	]+[0-9a-f]+:[ 	]+3a85c257[ 	]+vslideup.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3a803257[ 	]+vslideup.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+3a8fb257[ 	]+vslideup.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+3e85c257[ 	]+vslidedown.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3e803257[ 	]+vslidedown.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+3e8fb257[ 	]+vslidedown.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+3885c257[ 	]+vslideup.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+38803257[ 	]+vslideup.vi[ 	]+v4,v8,0,v0.t
+[ 	]+[0-9a-f]+:[ 	]+388fb257[ 	]+vslideup.vi[ 	]+v4,v8,31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3c85c257[ 	]+vslidedown.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3c803257[ 	]+vslidedown.vi[ 	]+v4,v8,0,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3c8fb257[ 	]+vslidedown.vi[ 	]+v4,v8,31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3a85e257[ 	]+vslide1up.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3e85e257[ 	]+vslide1down.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3885e257[ 	]+vslide1up.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3c85e257[ 	]+vslide1down.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3a85d257[ 	]+vfslide1up.vf[ 	]+v4,v8,fa1
+[ 	]+[0-9a-f]+:[ 	]+3e85d257[ 	]+vfslide1down.vf[ 	]+v4,v8,fa1
+[ 	]+[0-9a-f]+:[ 	]+3885d257[ 	]+vfslide1up.vf[ 	]+v4,v8,fa1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3c85d257[ 	]+vfslide1down.vf[ 	]+v4,v8,fa1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+32860257[ 	]+vrgather.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+3285c257[ 	]+vrgather.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+32803257[ 	]+vrgather.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+328fb257[ 	]+vrgather.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+30860257[ 	]+vrgather.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3085c257[ 	]+vrgather.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+30803257[ 	]+vrgather.vi[ 	]+v4,v8,0,v0.t
+[ 	]+[0-9a-f]+:[ 	]+308fb257[ 	]+vrgather.vi[ 	]+v4,v8,31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3a860257[ 	]+vrgatherei16.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+38860257[ 	]+vrgatherei16.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+5e862257[ 	]+vcompress.vm[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+9e2030d7[ 	]+vmv1r.v[ 	]+v1,v2
+[ 	]+[0-9a-f]+:[ 	]+9e40b157[ 	]+vmv2r.v[ 	]+v2,v4
+[ 	]+[0-9a-f]+:[ 	]+9e81b257[ 	]+vmv4r.v[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+9e83b057[ 	]+vmv8r.v[ 	]+v0,v8
diff --git a/gas/testsuite/gas/riscv/extended/vector-insns.s b/gas/testsuite/gas/riscv/extended/vector-insns.s
new file mode 100644
index 0000000..5c78e28
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/vector-insns.s
@@ -0,0 +1,2183 @@
+	vsetvl a0, a1, a2
+	vsetvli a0, a1, 0
+	vsetvli a0, a1, 0x7ff
+	vsetvli a0, a1, e16, m2
+	vsetvli a0, a1, e256, m8
+	vsetvli a0, a1, e512, m8
+	vsetvli a0, a1, e1024, m8
+	vsetvli a0, a1, e1024, m1
+	vsetvli a0, a1, e1024, mf2
+	vsetvli a0, a1, e512, mf4
+	vsetvli a0, a1, e256, mf8
+	vsetvli a0, a1, e256, m2, ta
+	vsetvli a0, a1, e256, m2, ma
+	vsetvli a0, a1, e256, m2, tu
+	vsetvli a0, a1, e256, m2, mu
+	vsetvli a0, a1, e256, m2, ta, ma
+	vsetvli a0, a1, e256, m2, tu, ma
+	vsetvli a0, a1, e256, m2, ta, mu
+	vsetvli a0, a1, e256, m2, tu, mu
+	vsetivli a0, 0xb, 0
+	vsetivli a0, 0xb, 0x3ff
+	vsetivli a0, 0xb, e16, m2
+	vsetivli a0, 0xb, e256, m8
+	vsetivli a0, 0xb, e512, m8
+	vsetivli a0, 0xb, e1024, m8
+	vsetivli a0, 0xb, e1024, m1
+	vsetivli a0, 0xb, e1024, mf2
+	vsetivli a0, 0xb, e512, mf4
+	vsetivli a0, 0xb, e256, mf8
+	vsetivli a0, 0xb, e256, m2, ta
+	vsetivli a0, 0xb, e256, m2, ma
+	vsetivli a0, 0xb, e256, m2, tu
+	vsetivli a0, 0xb, e256, m2, mu
+	vsetivli a0, 0xb, e256, m2, ta, ma
+	vsetivli a0, 0xb, e256, m2, tu, ma
+	vsetivli a0, 0xb, e256, m2, ta, mu
+	vsetivli a0, 0xb, e256, m2, tu, mu
+
+	vle1.v v4, (a0)
+	vle1.v v4, 0(a0)
+	vse1.v v4, (a0)
+	vse1.v v4, 0(a0)
+
+	vle8.v v4, (a0)
+	vle8.v v4, 0(a0)
+	vle8.v v4, (a0), v0.t
+	vse8.v v4, (a0)
+	vse8.v v4, 0(a0)
+	vse8.v v4, (a0), v0.t
+
+	vle16.v v4, (a0)
+	vle16.v v4, 0(a0)
+	vle16.v v4, (a0), v0.t
+	vse16.v v4, (a0)
+	vse16.v v4, 0(a0)
+	vse16.v v4, (a0), v0.t
+
+	vle32.v v4, (a0)
+	vle32.v v4, 0(a0)
+	vle32.v v4, (a0), v0.t
+	vse32.v v4, (a0)
+	vse32.v v4, 0(a0)
+	vse32.v v4, (a0), v0.t
+
+	vle64.v v4, (a0)
+	vle64.v v4, 0(a0)
+	vle64.v v4, (a0), v0.t
+	vse64.v v4, (a0)
+	vse64.v v4, 0(a0)
+	vse64.v v4, (a0), v0.t
+
+	vlse8.v v4, (a0), a1
+	vlse8.v v4, 0(a0), a1
+	vlse8.v v4, (a0), a1, v0.t
+	vsse8.v v4, (a0), a1
+	vsse8.v v4, 0(a0), a1
+	vsse8.v v4, (a0), a1, v0.t
+
+	vlse16.v v4, (a0), a1
+	vlse16.v v4, 0(a0), a1
+	vlse16.v v4, (a0), a1, v0.t
+	vsse16.v v4, (a0), a1
+	vsse16.v v4, 0(a0), a1
+	vsse16.v v4, (a0), a1, v0.t
+
+	vlse32.v v4, (a0), a1
+	vlse32.v v4, 0(a0), a1
+	vlse32.v v4, (a0), a1, v0.t
+	vsse32.v v4, (a0), a1
+	vsse32.v v4, 0(a0), a1
+	vsse32.v v4, (a0), a1, v0.t
+
+	vlse64.v v4, (a0), a1
+	vlse64.v v4, 0(a0), a1
+	vlse64.v v4, (a0), a1, v0.t
+	vsse64.v v4, (a0), a1
+	vsse64.v v4, 0(a0), a1
+	vsse64.v v4, (a0), a1, v0.t
+
+	vloxei8.v v4, (a0), v12
+	vloxei8.v v4, 0(a0), v12
+	vloxei8.v v4, (a0), v12, v0.t
+	vsoxei8.v v4, (a0), v12
+	vsoxei8.v v4, 0(a0), v12
+	vsoxei8.v v4, (a0), v12, v0.t
+	vluxei8.v v4, (a0), v12
+	vluxei8.v v4, 0(a0), v12
+	vluxei8.v v4, (a0), v12, v0.t
+	vsuxei8.v v4, (a0), v12
+	vsuxei8.v v4, 0(a0), v12
+	vsuxei8.v v4, (a0), v12, v0.t
+
+	vloxei16.v v4, (a0), v12
+	vloxei16.v v4, 0(a0), v12
+	vloxei16.v v4, (a0), v12, v0.t
+	vsoxei16.v v4, (a0), v12
+	vsoxei16.v v4, 0(a0), v12
+	vsoxei16.v v4, (a0), v12, v0.t
+	vluxei16.v v4, (a0), v12
+	vluxei16.v v4, 0(a0), v12
+	vluxei16.v v4, (a0), v12, v0.t
+	vsuxei16.v v4, (a0), v12
+	vsuxei16.v v4, 0(a0), v12
+	vsuxei16.v v4, (a0), v12, v0.t
+
+	vloxei32.v v4, (a0), v12
+	vloxei32.v v4, 0(a0), v12
+	vloxei32.v v4, (a0), v12, v0.t
+	vsoxei32.v v4, (a0), v12
+	vsoxei32.v v4, 0(a0), v12
+	vsoxei32.v v4, (a0), v12, v0.t
+	vluxei32.v v4, (a0), v12
+	vluxei32.v v4, 0(a0), v12
+	vluxei32.v v4, (a0), v12, v0.t
+	vsuxei32.v v4, (a0), v12
+	vsuxei32.v v4, 0(a0), v12
+	vsuxei32.v v4, (a0), v12, v0.t
+
+	vloxei64.v v4, (a0), v12
+	vloxei64.v v4, 0(a0), v12
+	vloxei64.v v4, (a0), v12, v0.t
+	vsoxei64.v v4, (a0), v12
+	vsoxei64.v v4, 0(a0), v12
+	vsoxei64.v v4, (a0), v12, v0.t
+	vluxei64.v v4, (a0), v12
+	vluxei64.v v4, 0(a0), v12
+	vluxei64.v v4, (a0), v12, v0.t
+	vsuxei64.v v4, (a0), v12
+	vsuxei64.v v4, 0(a0), v12
+	vsuxei64.v v4, (a0), v12, v0.t
+
+	vle8ff.v v4, (a0)
+	vle8ff.v v4, 0(a0)
+	vle8ff.v v4, (a0), v0.t
+
+	vle16ff.v v4, (a0)
+	vle16ff.v v4, 0(a0)
+	vle16ff.v v4, (a0), v0.t
+
+	vle32ff.v v4, (a0)
+	vle32ff.v v4, 0(a0)
+	vle32ff.v v4, (a0), v0.t
+
+	vle64ff.v v4, (a0)
+	vle64ff.v v4, 0(a0)
+	vle64ff.v v4, (a0), v0.t
+
+	vlseg2e8.v v4, (a0)
+	vlseg2e8.v v4, 0(a0)
+	vlseg2e8.v v4, (a0), v0.t
+	vsseg2e8.v v4, (a0)
+	vsseg2e8.v v4, 0(a0)
+	vsseg2e8.v v4, (a0), v0.t
+
+	vlseg3e8.v v4, (a0)
+	vlseg3e8.v v4, 0(a0)
+	vlseg3e8.v v4, (a0), v0.t
+	vsseg3e8.v v4, (a0)
+	vsseg3e8.v v4, 0(a0)
+	vsseg3e8.v v4, (a0), v0.t
+
+	vlseg4e8.v v4, (a0)
+	vlseg4e8.v v4, 0(a0)
+	vlseg4e8.v v4, (a0), v0.t
+	vsseg4e8.v v4, (a0)
+	vsseg4e8.v v4, 0(a0)
+	vsseg4e8.v v4, (a0), v0.t
+
+	vlseg5e8.v v4, (a0)
+	vlseg5e8.v v4, 0(a0)
+	vlseg5e8.v v4, (a0), v0.t
+	vsseg5e8.v v4, (a0)
+	vsseg5e8.v v4, 0(a0)
+	vsseg5e8.v v4, (a0), v0.t
+
+	vlseg6e8.v v4, (a0)
+	vlseg6e8.v v4, 0(a0)
+	vlseg6e8.v v4, (a0), v0.t
+	vsseg6e8.v v4, (a0)
+	vsseg6e8.v v4, 0(a0)
+	vsseg6e8.v v4, (a0), v0.t
+
+	vlseg7e8.v v4, (a0)
+	vlseg7e8.v v4, 0(a0)
+	vlseg7e8.v v4, (a0), v0.t
+	vsseg7e8.v v4, (a0)
+	vsseg7e8.v v4, 0(a0)
+	vsseg7e8.v v4, (a0), v0.t
+
+	vlseg8e8.v v4, (a0)
+	vlseg8e8.v v4, 0(a0)
+	vlseg8e8.v v4, (a0), v0.t
+	vsseg8e8.v v4, (a0)
+	vsseg8e8.v v4, 0(a0)
+	vsseg8e8.v v4, (a0), v0.t
+
+	vlseg2e16.v v4, (a0)
+	vlseg2e16.v v4, 0(a0)
+	vlseg2e16.v v4, (a0), v0.t
+	vsseg2e16.v v4, (a0)
+	vsseg2e16.v v4, 0(a0)
+	vsseg2e16.v v4, (a0), v0.t
+
+	vlseg3e16.v v4, (a0)
+	vlseg3e16.v v4, 0(a0)
+	vlseg3e16.v v4, (a0), v0.t
+	vsseg3e16.v v4, (a0)
+	vsseg3e16.v v4, 0(a0)
+	vsseg3e16.v v4, (a0), v0.t
+
+	vlseg4e16.v v4, (a0)
+	vlseg4e16.v v4, 0(a0)
+	vlseg4e16.v v4, (a0), v0.t
+	vsseg4e16.v v4, (a0)
+	vsseg4e16.v v4, 0(a0)
+	vsseg4e16.v v4, (a0), v0.t
+
+	vlseg5e16.v v4, (a0)
+	vlseg5e16.v v4, 0(a0)
+	vlseg5e16.v v4, (a0), v0.t
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+	vl4r.v v4, 0(a0)
+	vl4re8.v v4, (a0)
+	vl4re8.v v4, 0(a0)
+	vl4re16.v v4, (a0)
+	vl4re16.v v4, 0(a0)
+	vl4re32.v v4, (a0)
+	vl4re32.v v4, 0(a0)
+	vl4re64.v v4, (a0)
+	vl4re64.v v4, 0(a0)
+
+	vl8r.v v8, (a0)
+	vl8r.v v8, 0(a0)
+	vl8re8.v v8, (a0)
+	vl8re8.v v8, 0(a0)
+	vl8re16.v v8, (a0)
+	vl8re16.v v8, 0(a0)
+	vl8re32.v v8, (a0)
+	vl8re32.v v8, 0(a0)
+	vl8re64.v v8, (a0)
+	vl8re64.v v8, 0(a0)
+
+	vs1r.v v3, (a1)
+	vs1r.v v3, 0(a1)
+	vs2r.v v2, (a1)
+	vs2r.v v2, 0(a1)
+	vs4r.v v4, (a1)
+	vs4r.v v4, 0(a1)
+	vs8r.v v8, (a1)
+	vs8r.v v8, 0(a1)
+
+	vamoaddei8.v v4, (a1), v8, v4
+	vamoaddei8.v x0, (a1), v8, v4
+	vamoaddei8.v v4, (a1), v8, v4, v0.t
+	vamoaddei8.v x0, (a1), v8, v4, v0.t
+	vamoswapei8.v v4, (a1), v8, v4
+	vamoswapei8.v x0, (a1), v8, v4
+	vamoswapei8.v v4, (a1), v8, v4, v0.t
+	vamoswapei8.v x0, (a1), v8, v4, v0.t
+
+	vamoxorei8.v v4, (a1), v8, v4
+	vamoxorei8.v x0, (a1), v8, v4
+	vamoxorei8.v v4, (a1), v8, v4, v0.t
+	vamoxorei8.v x0, (a1), v8, v4, v0.t
+	vamoandei8.v v4, (a1), v8, v4
+	vamoandei8.v x0, (a1), v8, v4
+	vamoandei8.v v4, (a1), v8, v4, v0.t
+	vamoandei8.v x0, (a1), v8, v4, v0.t
+	vamoorei8.v v4, (a1), v8, v4
+	vamoorei8.v x0, (a1), v8, v4
+	vamoorei8.v v4, (a1), v8, v4, v0.t
+	vamoorei8.v x0, (a1), v8, v4, v0.t
+
+	vamominei8.v v4, (a1), v8, v4
+	vamominei8.v x0, (a1), v8, v4
+	vamominei8.v v4, (a1), v8, v4, v0.t
+	vamominei8.v x0, (a1), v8, v4, v0.t
+	vamomaxei8.v v4, (a1), v8, v4
+	vamomaxei8.v x0, (a1), v8, v4
+	vamomaxei8.v v4, (a1), v8, v4, v0.t
+	vamomaxei8.v x0, (a1), v8, v4, v0.t
+	vamominuei8.v v4, (a1), v8, v4
+	vamominuei8.v x0, (a1), v8, v4
+	vamominuei8.v v4, (a1), v8, v4, v0.t
+	vamominuei8.v x0, (a1), v8, v4, v0.t
+	vamomaxuei8.v v4, (a1), v8, v4
+	vamomaxuei8.v x0, (a1), v8, v4
+	vamomaxuei8.v v4, (a1), v8, v4, v0.t
+	vamomaxuei8.v x0, (a1), v8, v4, v0.t
+
+	vamoaddei8.v v4, 0(a1), v8, v4
+	vamoaddei8.v x0, 0(a1), v8, v4
+	vamoaddei8.v v4, 0(a1), v8, v4, v0.t
+	vamoaddei8.v x0, 0(a1), v8, v4, v0.t
+	vamoswapei8.v v4, 0(a1), v8, v4
+	vamoswapei8.v x0, 0(a1), v8, v4
+	vamoswapei8.v v4, 0(a1), v8, v4, v0.t
+	vamoswapei8.v x0, 0(a1), v8, v4, v0.t
+
+	vamoxorei8.v v4, 0(a1), v8, v4
+	vamoxorei8.v x0, 0(a1), v8, v4
+	vamoxorei8.v v4, 0(a1), v8, v4, v0.t
+	vamoxorei8.v x0, 0(a1), v8, v4, v0.t
+	vamoandei8.v v4, 0(a1), v8, v4
+	vamoandei8.v x0, 0(a1), v8, v4
+	vamoandei8.v v4, 0(a1), v8, v4, v0.t
+	vamoandei8.v x0, 0(a1), v8, v4, v0.t
+	vamoorei8.v v4, 0(a1), v8, v4
+	vamoorei8.v x0, 0(a1), v8, v4
+	vamoorei8.v v4, 0(a1), v8, v4, v0.t
+	vamoorei8.v x0, 0(a1), v8, v4, v0.t
+
+	vamominei8.v v4, 0(a1), v8, v4
+	vamominei8.v x0, 0(a1), v8, v4
+	vamominei8.v v4, 0(a1), v8, v4, v0.t
+	vamominei8.v x0, 0(a1), v8, v4, v0.t
+	vamomaxei8.v v4, 0(a1), v8, v4
+	vamomaxei8.v x0, 0(a1), v8, v4
+	vamomaxei8.v v4, 0(a1), v8, v4, v0.t
+	vamomaxei8.v x0, 0(a1), v8, v4, v0.t
+	vamominuei8.v v4, 0(a1), v8, v4
+	vamominuei8.v x0, 0(a1), v8, v4
+	vamominuei8.v v4, 0(a1), v8, v4, v0.t
+	vamominuei8.v x0, 0(a1), v8, v4, v0.t
+	vamomaxuei8.v v4, 0(a1), v8, v4
+	vamomaxuei8.v x0, 0(a1), v8, v4
+	vamomaxuei8.v v4, 0(a1), v8, v4, v0.t
+	vamomaxuei8.v x0, 0(a1), v8, v4, v0.t
+
+	vamoaddei16.v v4, (a1), v8, v4
+	vamoaddei16.v x0, (a1), v8, v4
+	vamoaddei16.v v4, (a1), v8, v4, v0.t
+	vamoaddei16.v x0, (a1), v8, v4, v0.t
+	vamoswapei16.v v4, (a1), v8, v4
+	vamoswapei16.v x0, (a1), v8, v4
+	vamoswapei16.v v4, (a1), v8, v4, v0.t
+	vamoswapei16.v x0, (a1), v8, v4, v0.t
+
+	vamoxorei16.v v4, (a1), v8, v4
+	vamoxorei16.v x0, (a1), v8, v4
+	vamoxorei16.v v4, (a1), v8, v4, v0.t
+	vamoxorei16.v x0, (a1), v8, v4, v0.t
+	vamoandei16.v v4, (a1), v8, v4
+	vamoandei16.v x0, (a1), v8, v4
+	vamoandei16.v v4, (a1), v8, v4, v0.t
+	vamoandei16.v x0, (a1), v8, v4, v0.t
+	vamoorei16.v v4, (a1), v8, v4
+	vamoorei16.v x0, (a1), v8, v4
+	vamoorei16.v v4, (a1), v8, v4, v0.t
+	vamoorei16.v x0, (a1), v8, v4, v0.t
+
+	vamominei16.v v4, (a1), v8, v4
+	vamominei16.v x0, (a1), v8, v4
+	vamominei16.v v4, (a1), v8, v4, v0.t
+	vamominei16.v x0, (a1), v8, v4, v0.t
+	vamomaxei16.v v4, (a1), v8, v4
+	vamomaxei16.v x0, (a1), v8, v4
+	vamomaxei16.v v4, (a1), v8, v4, v0.t
+	vamomaxei16.v x0, (a1), v8, v4, v0.t
+	vamominuei16.v v4, (a1), v8, v4
+	vamominuei16.v x0, (a1), v8, v4
+	vamominuei16.v v4, (a1), v8, v4, v0.t
+	vamominuei16.v x0, (a1), v8, v4, v0.t
+	vamomaxuei16.v v4, (a1), v8, v4
+	vamomaxuei16.v x0, (a1), v8, v4
+	vamomaxuei16.v v4, (a1), v8, v4, v0.t
+	vamomaxuei16.v x0, (a1), v8, v4, v0.t
+
+	vamoaddei16.v v4, 0(a1), v8, v4
+	vamoaddei16.v x0, 0(a1), v8, v4
+	vamoaddei16.v v4, 0(a1), v8, v4, v0.t
+	vamoaddei16.v x0, 0(a1), v8, v4, v0.t
+	vamoswapei16.v v4, 0(a1), v8, v4
+	vamoswapei16.v x0, 0(a1), v8, v4
+	vamoswapei16.v v4, 0(a1), v8, v4, v0.t
+	vamoswapei16.v x0, 0(a1), v8, v4, v0.t
+
+	vamoxorei16.v v4, 0(a1), v8, v4
+	vamoxorei16.v x0, 0(a1), v8, v4
+	vamoxorei16.v v4, 0(a1), v8, v4, v0.t
+	vamoxorei16.v x0, 0(a1), v8, v4, v0.t
+	vamoandei16.v v4, 0(a1), v8, v4
+	vamoandei16.v x0, 0(a1), v8, v4
+	vamoandei16.v v4, 0(a1), v8, v4, v0.t
+	vamoandei16.v x0, 0(a1), v8, v4, v0.t
+	vamoorei16.v v4, 0(a1), v8, v4
+	vamoorei16.v x0, 0(a1), v8, v4
+	vamoorei16.v v4, 0(a1), v8, v4, v0.t
+	vamoorei16.v x0, 0(a1), v8, v4, v0.t
+
+	vamominei16.v v4, 0(a1), v8, v4
+	vamominei16.v x0, 0(a1), v8, v4
+	vamominei16.v v4, 0(a1), v8, v4, v0.t
+	vamominei16.v x0, 0(a1), v8, v4, v0.t
+	vamomaxei16.v v4, 0(a1), v8, v4
+	vamomaxei16.v x0, 0(a1), v8, v4
+	vamomaxei16.v v4, 0(a1), v8, v4, v0.t
+	vamomaxei16.v x0, 0(a1), v8, v4, v0.t
+	vamominuei16.v v4, 0(a1), v8, v4
+	vamominuei16.v x0, 0(a1), v8, v4
+	vamominuei16.v v4, 0(a1), v8, v4, v0.t
+	vamominuei16.v x0, 0(a1), v8, v4, v0.t
+	vamomaxuei16.v v4, 0(a1), v8, v4
+	vamomaxuei16.v x0, 0(a1), v8, v4
+	vamomaxuei16.v v4, 0(a1), v8, v4, v0.t
+	vamomaxuei16.v x0, 0(a1), v8, v4, v0.t
+
+	vamoaddei32.v v4, (a1), v8, v4
+	vamoaddei32.v x0, (a1), v8, v4
+	vamoaddei32.v v4, (a1), v8, v4, v0.t
+	vamoaddei32.v x0, (a1), v8, v4, v0.t
+	vamoswapei32.v v4, (a1), v8, v4
+	vamoswapei32.v x0, (a1), v8, v4
+	vamoswapei32.v v4, (a1), v8, v4, v0.t
+	vamoswapei32.v x0, (a1), v8, v4, v0.t
+
+	vamoxorei32.v v4, (a1), v8, v4
+	vamoxorei32.v x0, (a1), v8, v4
+	vamoxorei32.v v4, (a1), v8, v4, v0.t
+	vamoxorei32.v x0, (a1), v8, v4, v0.t
+	vamoandei32.v v4, (a1), v8, v4
+	vamoandei32.v x0, (a1), v8, v4
+	vamoandei32.v v4, (a1), v8, v4, v0.t
+	vamoandei32.v x0, (a1), v8, v4, v0.t
+	vamoorei32.v v4, (a1), v8, v4
+	vamoorei32.v x0, (a1), v8, v4
+	vamoorei32.v v4, (a1), v8, v4, v0.t
+	vamoorei32.v x0, (a1), v8, v4, v0.t
+
+	vamominei32.v v4, (a1), v8, v4
+	vamominei32.v x0, (a1), v8, v4
+	vamominei32.v v4, (a1), v8, v4, v0.t
+	vamominei32.v x0, (a1), v8, v4, v0.t
+	vamomaxei32.v v4, (a1), v8, v4
+	vamomaxei32.v x0, (a1), v8, v4
+	vamomaxei32.v v4, (a1), v8, v4, v0.t
+	vamomaxei32.v x0, (a1), v8, v4, v0.t
+	vamominuei32.v v4, (a1), v8, v4
+	vamominuei32.v x0, (a1), v8, v4
+	vamominuei32.v v4, (a1), v8, v4, v0.t
+	vamominuei32.v x0, (a1), v8, v4, v0.t
+	vamomaxuei32.v v4, (a1), v8, v4
+	vamomaxuei32.v x0, (a1), v8, v4
+	vamomaxuei32.v v4, (a1), v8, v4, v0.t
+	vamomaxuei32.v x0, (a1), v8, v4, v0.t
+
+	vamoaddei32.v v4, 0(a1), v8, v4
+	vamoaddei32.v x0, 0(a1), v8, v4
+	vamoaddei32.v v4, 0(a1), v8, v4, v0.t
+	vamoaddei32.v x0, 0(a1), v8, v4, v0.t
+	vamoswapei32.v v4, 0(a1), v8, v4
+	vamoswapei32.v x0, 0(a1), v8, v4
+	vamoswapei32.v v4, 0(a1), v8, v4, v0.t
+	vamoswapei32.v x0, 0(a1), v8, v4, v0.t
+
+	vamoxorei32.v v4, 0(a1), v8, v4
+	vamoxorei32.v x0, 0(a1), v8, v4
+	vamoxorei32.v v4, 0(a1), v8, v4, v0.t
+	vamoxorei32.v x0, 0(a1), v8, v4, v0.t
+	vamoandei32.v v4, 0(a1), v8, v4
+	vamoandei32.v x0, 0(a1), v8, v4
+	vamoandei32.v v4, 0(a1), v8, v4, v0.t
+	vamoandei32.v x0, 0(a1), v8, v4, v0.t
+	vamoorei32.v v4, 0(a1), v8, v4
+	vamoorei32.v x0, 0(a1), v8, v4
+	vamoorei32.v v4, 0(a1), v8, v4, v0.t
+	vamoorei32.v x0, 0(a1), v8, v4, v0.t
+
+	vamominei32.v v4, 0(a1), v8, v4
+	vamominei32.v x0, 0(a1), v8, v4
+	vamominei32.v v4, 0(a1), v8, v4, v0.t
+	vamominei32.v x0, 0(a1), v8, v4, v0.t
+	vamomaxei32.v v4, 0(a1), v8, v4
+	vamomaxei32.v x0, 0(a1), v8, v4
+	vamomaxei32.v v4, 0(a1), v8, v4, v0.t
+	vamomaxei32.v x0, 0(a1), v8, v4, v0.t
+	vamominuei32.v v4, 0(a1), v8, v4
+	vamominuei32.v x0, 0(a1), v8, v4
+	vamominuei32.v v4, 0(a1), v8, v4, v0.t
+	vamominuei32.v x0, 0(a1), v8, v4, v0.t
+	vamomaxuei32.v v4, 0(a1), v8, v4
+	vamomaxuei32.v x0, 0(a1), v8, v4
+	vamomaxuei32.v v4, 0(a1), v8, v4, v0.t
+	vamomaxuei32.v x0, 0(a1), v8, v4, v0.t
+
+	vamoaddei64.v v4, (a1), v8, v4
+	vamoaddei64.v x0, (a1), v8, v4
+	vamoaddei64.v v4, (a1), v8, v4, v0.t
+	vamoaddei64.v x0, (a1), v8, v4, v0.t
+	vamoswapei64.v v4, (a1), v8, v4
+	vamoswapei64.v x0, (a1), v8, v4
+	vamoswapei64.v v4, (a1), v8, v4, v0.t
+	vamoswapei64.v x0, (a1), v8, v4, v0.t
+
+	vamoxorei64.v v4, (a1), v8, v4
+	vamoxorei64.v x0, (a1), v8, v4
+	vamoxorei64.v v4, (a1), v8, v4, v0.t
+	vamoxorei64.v x0, (a1), v8, v4, v0.t
+	vamoandei64.v v4, (a1), v8, v4
+	vamoandei64.v x0, (a1), v8, v4
+	vamoandei64.v v4, (a1), v8, v4, v0.t
+	vamoandei64.v x0, (a1), v8, v4, v0.t
+	vamoorei64.v v4, (a1), v8, v4
+	vamoorei64.v x0, (a1), v8, v4
+	vamoorei64.v v4, (a1), v8, v4, v0.t
+	vamoorei64.v x0, (a1), v8, v4, v0.t
+
+	vamominei64.v v4, (a1), v8, v4
+	vamominei64.v x0, (a1), v8, v4
+	vamominei64.v v4, (a1), v8, v4, v0.t
+	vamominei64.v x0, (a1), v8, v4, v0.t
+	vamomaxei64.v v4, (a1), v8, v4
+	vamomaxei64.v x0, (a1), v8, v4
+	vamomaxei64.v v4, (a1), v8, v4, v0.t
+	vamomaxei64.v x0, (a1), v8, v4, v0.t
+	vamominuei64.v v4, (a1), v8, v4
+	vamominuei64.v x0, (a1), v8, v4
+	vamominuei64.v v4, (a1), v8, v4, v0.t
+	vamominuei64.v x0, (a1), v8, v4, v0.t
+	vamomaxuei64.v v4, (a1), v8, v4
+	vamomaxuei64.v x0, (a1), v8, v4
+	vamomaxuei64.v v4, (a1), v8, v4, v0.t
+	vamomaxuei64.v x0, (a1), v8, v4, v0.t
+
+	vamoaddei64.v v4, 0(a1), v8, v4
+	vamoaddei64.v x0, 0(a1), v8, v4
+	vamoaddei64.v v4, 0(a1), v8, v4, v0.t
+	vamoaddei64.v x0, 0(a1), v8, v4, v0.t
+	vamoswapei64.v v4, 0(a1), v8, v4
+	vamoswapei64.v x0, 0(a1), v8, v4
+	vamoswapei64.v v4, 0(a1), v8, v4, v0.t
+	vamoswapei64.v x0, 0(a1), v8, v4, v0.t
+
+	vamoxorei64.v v4, 0(a1), v8, v4
+	vamoxorei64.v x0, 0(a1), v8, v4
+	vamoxorei64.v v4, 0(a1), v8, v4, v0.t
+	vamoxorei64.v x0, 0(a1), v8, v4, v0.t
+	vamoandei64.v v4, 0(a1), v8, v4
+	vamoandei64.v x0, 0(a1), v8, v4
+	vamoandei64.v v4, 0(a1), v8, v4, v0.t
+	vamoandei64.v x0, 0(a1), v8, v4, v0.t
+	vamoorei64.v v4, 0(a1), v8, v4
+	vamoorei64.v x0, 0(a1), v8, v4
+	vamoorei64.v v4, 0(a1), v8, v4, v0.t
+	vamoorei64.v x0, 0(a1), v8, v4, v0.t
+
+	vamominei64.v v4, 0(a1), v8, v4
+	vamominei64.v x0, 0(a1), v8, v4
+	vamominei64.v v4, 0(a1), v8, v4, v0.t
+	vamominei64.v x0, 0(a1), v8, v4, v0.t
+	vamomaxei64.v v4, 0(a1), v8, v4
+	vamomaxei64.v x0, 0(a1), v8, v4
+	vamomaxei64.v v4, 0(a1), v8, v4, v0.t
+	vamomaxei64.v x0, 0(a1), v8, v4, v0.t
+	vamominuei64.v v4, 0(a1), v8, v4
+	vamominuei64.v x0, 0(a1), v8, v4
+	vamominuei64.v v4, 0(a1), v8, v4, v0.t
+	vamominuei64.v x0, 0(a1), v8, v4, v0.t
+	vamomaxuei64.v v4, 0(a1), v8, v4
+	vamomaxuei64.v x0, 0(a1), v8, v4
+	vamomaxuei64.v v4, 0(a1), v8, v4, v0.t
+	vamomaxuei64.v x0, 0(a1), v8, v4, v0.t
+
+	vneg.v v4, v8
+	vneg.v v4, v8, v0.t
+
+	vadd.vv v4, v8, v12
+	vadd.vx v4, v8, a1
+	vadd.vi v4, v8, 15
+	vadd.vi v4, v8, -16
+	vadd.vv v4, v8, v12, v0.t
+	vadd.vx v4, v8, a1, v0.t
+	vadd.vi v4, v8, 15, v0.t
+	vadd.vi v4, v8, -16, v0.t
+	vsub.vv v4, v8, v12
+	vsub.vx v4, v8, a1
+	vrsub.vx v4, v8, a1
+	vrsub.vi v4, v8, 15
+	vrsub.vi v4, v8, -16
+	vsub.vv v4, v8, v12, v0.t
+	vsub.vx v4, v8, a1, v0.t
+	vrsub.vx v4, v8, a1, v0.t
+	vrsub.vi v4, v8, 15, v0.t
+	vrsub.vi v4, v8, -16, v0.t
+
+	# Aliases
+	vwcvt.x.x.v v4, v8
+	vwcvtu.x.x.v v4, v8
+	vwcvt.x.x.v v4, v8, v0.t
+	vwcvtu.x.x.v v4, v8, v0.t
+
+	vwaddu.vv v4, v8, v12
+	vwaddu.vx v4, v8, a1
+	vwaddu.vv v4, v8, v12, v0.t
+	vwaddu.vx v4, v8, a1, v0.t
+	vwsubu.vv v4, v8, v12
+	vwsubu.vx v4, v8, a1
+	vwsubu.vv v4, v8, v12, v0.t
+	vwsubu.vx v4, v8, a1, v0.t
+	vwadd.vv v4, v8, v12
+	vwadd.vx v4, v8, a1
+	vwadd.vv v4, v8, v12, v0.t
+	vwadd.vx v4, v8, a1, v0.t
+	vwsub.vv v4, v8, v12
+	vwsub.vx v4, v8, a1
+	vwsub.vv v4, v8, v12, v0.t
+	vwsub.vx v4, v8, a1, v0.t
+	vwaddu.wv v4, v8, v12
+	vwaddu.wx v4, v8, a1
+	vwaddu.wv v4, v8, v12, v0.t
+	vwaddu.wx v4, v8, a1, v0.t
+	vwsubu.wv v4, v8, v12
+	vwsubu.wx v4, v8, a1
+	vwsubu.wv v4, v8, v12, v0.t
+	vwsubu.wx v4, v8, a1, v0.t
+	vwadd.wv v4, v8, v12
+	vwadd.wx v4, v8, a1
+	vwadd.wv v4, v8, v12, v0.t
+	vwadd.wx v4, v8, a1, v0.t
+	vwsub.wv v4, v8, v12
+	vwsub.wx v4, v8, a1
+	vwsub.wv v4, v8, v12, v0.t
+	vwsub.wx v4, v8, a1, v0.t
+
+	vzext.vf2 v4, v8
+	vzext.vf2 v4, v8, v0.t
+	vsext.vf2 v4, v8
+	vsext.vf2 v4, v8, v0.t
+	vzext.vf4 v4, v8
+	vzext.vf4 v4, v8, v0.t
+	vsext.vf4 v4, v8
+	vsext.vf4 v4, v8, v0.t
+	vzext.vf8 v4, v8
+	vzext.vf8 v4, v8, v0.t
+	vsext.vf8 v4, v8
+	vsext.vf8 v4, v8, v0.t
+
+	vadc.vvm v4, v8, v12, v0
+	vadc.vxm v4, v8, a1, v0
+	vadc.vim v4, v8, 15, v0
+	vadc.vim v4, v8, -16, v0
+	vmadc.vvm v4, v8, v12, v0
+	vmadc.vxm v4, v8, a1, v0
+	vmadc.vim v4, v8, 15, v0
+	vmadc.vim v4, v8, -16, v0
+	vmadc.vv v4, v8, v12
+	vmadc.vx v4, v8, a1
+	vmadc.vi v4, v8, 15
+	vmadc.vi v4, v8, -16
+	vsbc.vvm v4, v8, v12, v0
+	vsbc.vxm v4, v8, a1, v0
+	vmsbc.vvm v4, v8, v12, v0
+	vmsbc.vxm v4, v8, a1, v0
+	vmsbc.vv v4, v8, v12
+	vmsbc.vx v4, v8, a1
+
+	# Aliases
+	vnot.v v4, v8
+	vnot.v v4, v8, v0.t
+
+	vand.vv v4, v8, v12
+	vand.vx v4, v8, a1
+	vand.vi v4, v8, 15
+	vand.vi v4, v8, -16
+	vand.vv v4, v8, v12, v0.t
+	vand.vx v4, v8, a1, v0.t
+	vand.vi v4, v8, 15, v0.t
+	vand.vi v4, v8, -16, v0.t
+	vor.vv v4, v8, v12
+	vor.vx v4, v8, a1
+	vor.vi v4, v8, 15
+	vor.vi v4, v8, -16
+	vor.vv v4, v8, v12, v0.t
+	vor.vx v4, v8, a1, v0.t
+	vor.vi v4, v8, 15, v0.t
+	vor.vi v4, v8, -16, v0.t
+	vxor.vv v4, v8, v12
+	vxor.vx v4, v8, a1
+	vxor.vi v4, v8, 15
+	vxor.vi v4, v8, -16
+	vxor.vv v4, v8, v12, v0.t
+	vxor.vx v4, v8, a1, v0.t
+	vxor.vi v4, v8, 15, v0.t
+	vxor.vi v4, v8, -16, v0.t
+
+	vsll.vv v4, v8, v12
+	vsll.vx v4, v8, a1
+	vsll.vi v4, v8, 1
+	vsll.vi v4, v8, 31
+	vsll.vv v4, v8, v12, v0.t
+	vsll.vx v4, v8, a1, v0.t
+	vsll.vi v4, v8, 1, v0.t
+	vsll.vi v4, v8, 31, v0.t
+	vsrl.vv v4, v8, v12
+	vsrl.vx v4, v8, a1
+	vsrl.vi v4, v8, 1
+	vsrl.vi v4, v8, 31
+	vsrl.vv v4, v8, v12, v0.t
+	vsrl.vx v4, v8, a1, v0.t
+	vsrl.vi v4, v8, 1, v0.t
+	vsrl.vi v4, v8, 31, v0.t
+	vsra.vv v4, v8, v12
+	vsra.vx v4, v8, a1
+	vsra.vi v4, v8, 1
+	vsra.vi v4, v8, 31
+	vsra.vv v4, v8, v12, v0.t
+	vsra.vx v4, v8, a1, v0.t
+	vsra.vi v4, v8, 1, v0.t
+	vsra.vi v4, v8, 31, v0.t
+
+	# Aliases
+	vncvt.x.x.w v4, v8
+	vncvt.x.x.w v4, v8, v0.t
+
+	vnsrl.wv v4, v8, v12
+	vnsrl.wx v4, v8, a1
+	vnsrl.wi v4, v8, 1
+	vnsrl.wi v4, v8, 31
+	vnsrl.wv v4, v8, v12, v0.t
+	vnsrl.wx v4, v8, a1, v0.t
+	vnsrl.wi v4, v8, 1, v0.t
+	vnsrl.wi v4, v8, 31, v0.t
+	vnsra.wv v4, v8, v12
+	vnsra.wx v4, v8, a1
+	vnsra.wi v4, v8, 1
+	vnsra.wi v4, v8, 31
+	vnsra.wv v4, v8, v12, v0.t
+	vnsra.wx v4, v8, a1, v0.t
+	vnsra.wi v4, v8, 1, v0.t
+	vnsra.wi v4, v8, 31, v0.t
+
+	# Aliases
+	vmsgt.vv v4, v8, v12
+	vmsgtu.vv v4, v8, v12
+	vmsge.vv v4, v8, v12
+	vmsgeu.vv v4, v8, v12
+	vmsgt.vv v4, v8, v12, v0.t
+	vmsgtu.vv v4, v8, v12, v0.t
+	vmsge.vv v4, v8, v12, v0.t
+	vmsgeu.vv v4, v8, v12, v0.t
+	vmslt.vi v4, v8, 16
+	vmslt.vi v4, v8, -15
+	vmsltu.vi v4, v8, 16
+	vmsltu.vi v4, v8, -15
+	vmsge.vi v4, v8, 16
+	vmsge.vi v4, v8, -15
+	vmsgeu.vi v4, v8, 16
+	vmsgeu.vi v4, v8, -15
+	vmslt.vi v4, v8, 16, v0.t
+	vmslt.vi v4, v8, -15, v0.t
+	vmsltu.vi v4, v8, 16, v0.t
+	vmsltu.vi v4, v8, -15, v0.t
+	vmsge.vi v4, v8, 16, v0.t
+	vmsge.vi v4, v8, -15, v0.t
+	vmsgeu.vi v4, v8, 16, v0.t
+	vmsgeu.vi v4, v8, -15, v0.t
+
+	vmseq.vv v4, v8, v12
+	vmseq.vx v4, v8, a1
+	vmseq.vi v4, v8, 15
+	vmseq.vi v4, v8, -16
+	vmseq.vv v4, v8, v12, v0.t
+	vmseq.vx v4, v8, a1, v0.t
+	vmseq.vi v4, v8, 15, v0.t
+	vmseq.vi v4, v8, -16, v0.t
+	vmsne.vv v4, v8, v12
+	vmsne.vx v4, v8, a1
+	vmsne.vi v4, v8, 15
+	vmsne.vi v4, v8, -16
+	vmsne.vv v4, v8, v12, v0.t
+	vmsne.vx v4, v8, a1, v0.t
+	vmsne.vi v4, v8, 15, v0.t
+	vmsne.vi v4, v8, -16, v0.t
+	vmsltu.vv v4, v8, v12
+	vmsltu.vx v4, v8, a1
+	vmsltu.vv v4, v8, v12, v0.t
+	vmsltu.vx v4, v8, a1, v0.t
+	vmslt.vv v4, v8, v12
+	vmslt.vx v4, v8, a1
+	vmslt.vv v4, v8, v12, v0.t
+	vmslt.vx v4, v8, a1, v0.t
+	vmsleu.vv v4, v8, v12
+	vmsleu.vx v4, v8, a1
+	vmsleu.vi v4, v8, 15
+	vmsleu.vi v4, v8, -16
+	vmsleu.vv v4, v8, v12, v0.t
+	vmsleu.vx v4, v8, a1, v0.t
+	vmsleu.vi v4, v8, 15, v0.t
+	vmsleu.vi v4, v8, -16, v0.t
+	vmsle.vv v4, v8, v12
+	vmsle.vx v4, v8, a1
+	vmsle.vi v4, v8, 15
+	vmsle.vi v4, v8, -16
+	vmsle.vv v4, v8, v12, v0.t
+	vmsle.vx v4, v8, a1, v0.t
+	vmsle.vi v4, v8, 15, v0.t
+	vmsle.vi v4, v8, -16, v0.t
+	vmsgtu.vx v4, v8, a1
+	vmsgtu.vi v4, v8, 15
+	vmsgtu.vi v4, v8, -16
+	vmsgtu.vx v4, v8, a1, v0.t
+	vmsgtu.vi v4, v8, 15, v0.t
+	vmsgtu.vi v4, v8, -16, v0.t
+	vmsgt.vx v4, v8, a1
+	vmsgt.vi v4, v8, 15
+	vmsgt.vi v4, v8, -16
+	vmsgt.vx v4, v8, a1, v0.t
+	vmsgt.vi v4, v8, 15, v0.t
+	vmsgt.vi v4, v8, -16, v0.t
+
+	vminu.vv v4, v8, v12
+	vminu.vx v4, v8, a1
+	vminu.vv v4, v8, v12, v0.t
+	vminu.vx v4, v8, a1, v0.t
+	vmin.vv v4, v8, v12
+	vmin.vx v4, v8, a1
+	vmin.vv v4, v8, v12, v0.t
+	vmin.vx v4, v8, a1, v0.t
+	vmaxu.vv v4, v8, v12
+	vmaxu.vx v4, v8, a1
+	vmaxu.vv v4, v8, v12, v0.t
+	vmaxu.vx v4, v8, a1, v0.t
+	vmax.vv v4, v8, v12
+	vmax.vx v4, v8, a1
+	vmax.vv v4, v8, v12, v0.t
+	vmax.vx v4, v8, a1, v0.t
+
+	vmul.vv v4, v8, v12
+	vmul.vx v4, v8, a1
+	vmul.vv v4, v8, v12, v0.t
+	vmul.vx v4, v8, a1, v0.t
+	vmulh.vv v4, v8, v12
+	vmulh.vx v4, v8, a1
+	vmulh.vv v4, v8, v12, v0.t
+	vmulh.vx v4, v8, a1, v0.t
+	vmulhu.vv v4, v8, v12
+	vmulhu.vx v4, v8, a1
+	vmulhu.vv v4, v8, v12, v0.t
+	vmulhu.vx v4, v8, a1, v0.t
+	vmulhsu.vv v4, v8, v12
+	vmulhsu.vx v4, v8, a1
+	vmulhsu.vv v4, v8, v12, v0.t
+	vmulhsu.vx v4, v8, a1, v0.t
+
+	vwmul.vv v4, v8, v12
+	vwmul.vx v4, v8, a1
+	vwmul.vv v4, v8, v12, v0.t
+	vwmul.vx v4, v8, a1, v0.t
+	vwmulu.vv v4, v8, v12
+	vwmulu.vx v4, v8, a1
+	vwmulu.vv v4, v8, v12, v0.t
+	vwmulu.vx v4, v8, a1, v0.t
+	vwmulsu.vv v4, v8, v12
+	vwmulsu.vx v4, v8, a1
+	vwmulsu.vv v4, v8, v12, v0.t
+	vwmulsu.vx v4, v8, a1, v0.t
+
+	vmacc.vv v4, v12, v8
+	vmacc.vx v4, a1, v8
+	vmacc.vv v4, v12, v8, v0.t
+	vmacc.vx v4, a1, v8, v0.t
+	vnmsac.vv v4, v12, v8
+	vnmsac.vx v4, a1, v8
+	vnmsac.vv v4, v12, v8, v0.t
+	vnmsac.vx v4, a1, v8, v0.t
+	vmadd.vv v4, v12, v8
+	vmadd.vx v4, a1, v8
+	vmadd.vv v4, v12, v8, v0.t
+	vmadd.vx v4, a1, v8, v0.t
+	vnmsub.vv v4, v12, v8
+	vnmsub.vx v4, a1, v8
+	vnmsub.vv v4, v12, v8, v0.t
+	vnmsub.vx v4, a1, v8, v0.t
+
+	vwmaccu.vv v4, v12, v8
+	vwmaccu.vx v4, a1, v8
+	vwmaccu.vv v4, v12, v8, v0.t
+	vwmaccu.vx v4, a1, v8, v0.t
+	vwmacc.vv v4, v12, v8
+	vwmacc.vx v4, a1, v8
+	vwmacc.vv v4, v12, v8, v0.t
+	vwmacc.vx v4, a1, v8, v0.t
+	vwmaccsu.vv v4, v12, v8
+	vwmaccsu.vx v4, a1, v8
+	vwmaccsu.vv v4, v12, v8, v0.t
+	vwmaccsu.vx v4, a1, v8, v0.t
+	vwmaccus.vx v4, a1, v8
+	vwmaccus.vx v4, a1, v8, v0.t
+
+	vdivu.vv v4, v8, v12
+	vdivu.vx v4, v8, a1
+	vdivu.vv v4, v8, v12, v0.t
+	vdivu.vx v4, v8, a1, v0.t
+	vdiv.vv v4, v8, v12
+	vdiv.vx v4, v8, a1
+	vdiv.vv v4, v8, v12, v0.t
+	vdiv.vx v4, v8, a1, v0.t
+	vremu.vv v4, v8, v12
+	vremu.vx v4, v8, a1
+	vremu.vv v4, v8, v12, v0.t
+	vremu.vx v4, v8, a1, v0.t
+	vrem.vv v4, v8, v12
+	vrem.vx v4, v8, a1
+	vrem.vv v4, v8, v12, v0.t
+	vrem.vx v4, v8, a1, v0.t
+
+	vmerge.vvm v4, v8, v12, v0
+	vmerge.vxm v4, v8, a1, v0
+	vmerge.vim v4, v8, 15, v0
+	vmerge.vim v4, v8, -16, v0
+
+	vmv.v.v v8, v12
+	vmv.v.x v8, a1
+	vmv.v.i v8, 15
+	vmv.v.i v8, -16
+
+	vsaddu.vv v4, v8, v12
+	vsaddu.vx v4, v8, a1
+	vsaddu.vi v4, v8, 15
+	vsaddu.vi v4, v8, -16
+	vsaddu.vv v4, v8, v12, v0.t
+	vsaddu.vx v4, v8, a1, v0.t
+	vsaddu.vi v4, v8, 15, v0.t
+	vsaddu.vi v4, v8, -16, v0.t
+	vsadd.vv v4, v8, v12
+	vsadd.vx v4, v8, a1
+	vsadd.vi v4, v8, 15
+	vsadd.vi v4, v8, -16
+	vsadd.vv v4, v8, v12, v0.t
+	vsadd.vx v4, v8, a1, v0.t
+	vsadd.vi v4, v8, 15, v0.t
+	vsadd.vi v4, v8, -16, v0.t
+	vssubu.vv v4, v8, v12
+	vssubu.vx v4, v8, a1
+	vssubu.vv v4, v8, v12, v0.t
+	vssubu.vx v4, v8, a1, v0.t
+	vssub.vv v4, v8, v12
+	vssub.vx v4, v8, a1
+	vssub.vv v4, v8, v12, v0.t
+	vssub.vx v4, v8, a1, v0.t
+
+	vaaddu.vv v4, v8, v12
+	vaaddu.vx v4, v8, a1
+	vaaddu.vv v4, v8, v12, v0.t
+	vaaddu.vx v4, v8, a1, v0.t
+	vaadd.vv v4, v8, v12
+	vaadd.vx v4, v8, a1
+	vaadd.vv v4, v8, v12, v0.t
+	vaadd.vx v4, v8, a1, v0.t
+	vasubu.vv v4, v8, v12
+	vasubu.vx v4, v8, a1
+	vasubu.vv v4, v8, v12, v0.t
+	vasubu.vx v4, v8, a1, v0.t
+	vasub.vv v4, v8, v12
+	vasub.vx v4, v8, a1
+	vasub.vv v4, v8, v12, v0.t
+	vasub.vx v4, v8, a1, v0.t
+
+	vsmul.vv v4, v8, v12
+	vsmul.vx v4, v8, a1
+	vsmul.vv v4, v8, v12, v0.t
+	vsmul.vx v4, v8, a1, v0.t
+
+	vssrl.vv v4, v8, v12
+	vssrl.vx v4, v8, a1
+	vssrl.vi v4, v8, 1
+	vssrl.vi v4, v8, 31
+	vssrl.vv v4, v8, v12, v0.t
+	vssrl.vx v4, v8, a1, v0.t
+	vssrl.vi v4, v8, 1, v0.t
+	vssrl.vi v4, v8, 31, v0.t
+	vssra.vv v4, v8, v12
+	vssra.vx v4, v8, a1
+	vssra.vi v4, v8, 1
+	vssra.vi v4, v8, 31
+	vssra.vv v4, v8, v12, v0.t
+	vssra.vx v4, v8, a1, v0.t
+	vssra.vi v4, v8, 1, v0.t
+	vssra.vi v4, v8, 31, v0.t
+
+	vnclipu.wv v4, v8, v12
+	vnclipu.wx v4, v8, a1
+	vnclipu.wi v4, v8, 1
+	vnclipu.wi v4, v8, 31
+	vnclipu.wv v4, v8, v12, v0.t
+	vnclipu.wx v4, v8, a1, v0.t
+	vnclipu.wi v4, v8, 1, v0.t
+	vnclipu.wi v4, v8, 31, v0.t
+	vnclip.wv v4, v8, v12
+	vnclip.wx v4, v8, a1
+	vnclip.wi v4, v8, 1
+	vnclip.wi v4, v8, 31
+	vnclip.wv v4, v8, v12, v0.t
+	vnclip.wx v4, v8, a1, v0.t
+	vnclip.wi v4, v8, 1, v0.t
+	vnclip.wi v4, v8, 31, v0.t
+
+	vfadd.vv v4, v8, v12
+	vfadd.vf v4, v8, fa2
+	vfadd.vv v4, v8, v12, v0.t
+	vfadd.vf v4, v8, fa2, v0.t
+	vfsub.vv v4, v8, v12
+	vfsub.vf v4, v8, fa2
+	vfsub.vv v4, v8, v12, v0.t
+	vfsub.vf v4, v8, fa2, v0.t
+	vfrsub.vf v4, v8, fa2
+	vfrsub.vf v4, v8, fa2, v0.t
+
+	vfwadd.vv v4, v8, v12
+	vfwadd.vf v4, v8, fa2
+	vfwadd.vv v4, v8, v12, v0.t
+	vfwadd.vf v4, v8, fa2, v0.t
+	vfwsub.vv v4, v8, v12
+	vfwsub.vf v4, v8, fa2
+	vfwsub.vv v4, v8, v12, v0.t
+	vfwsub.vf v4, v8, fa2, v0.t
+	vfwadd.wv v4, v8, v12
+	vfwadd.wf v4, v8, fa2
+	vfwadd.wv v4, v8, v12, v0.t
+	vfwadd.wf v4, v8, fa2, v0.t
+	vfwsub.wv v4, v8, v12
+	vfwsub.wf v4, v8, fa2
+	vfwsub.wv v4, v8, v12, v0.t
+	vfwsub.wf v4, v8, fa2, v0.t
+
+	vfmul.vv v4, v8, v12
+	vfmul.vf v4, v8, fa2
+	vfmul.vv v4, v8, v12, v0.t
+	vfmul.vf v4, v8, fa2, v0.t
+	vfdiv.vv v4, v8, v12
+	vfdiv.vf v4, v8, fa2
+	vfdiv.vv v4, v8, v12, v0.t
+	vfdiv.vf v4, v8, fa2, v0.t
+	vfrdiv.vf v4, v8, fa2
+	vfrdiv.vf v4, v8, fa2, v0.t
+
+	vfwmul.vv v4, v8, v12
+	vfwmul.vf v4, v8, fa2
+	vfwmul.vv v4, v8, v12, v0.t
+	vfwmul.vf v4, v8, fa2, v0.t
+
+	vfmadd.vv v4, v12, v8
+	vfmadd.vf v4, fa2, v8
+	vfnmadd.vv v4, v12, v8
+	vfnmadd.vf v4, fa2, v8
+	vfmsub.vv v4, v12, v8
+	vfmsub.vf v4, fa2, v8
+	vfnmsub.vv v4, v12, v8
+	vfnmsub.vf v4, fa2, v8
+	vfmadd.vv v4, v12, v8, v0.t
+	vfmadd.vf v4, fa2, v8, v0.t
+	vfnmadd.vv v4, v12, v8, v0.t
+	vfnmadd.vf v4, fa2, v8, v0.t
+	vfmsub.vv v4, v12, v8, v0.t
+	vfmsub.vf v4, fa2, v8, v0.t
+	vfnmsub.vv v4, v12, v8, v0.t
+	vfnmsub.vf v4, fa2, v8, v0.t
+	vfmacc.vv v4, v12, v8
+	vfmacc.vf v4, fa2, v8
+	vfnmacc.vv v4, v12, v8
+	vfnmacc.vf v4, fa2, v8
+	vfmsac.vv v4, v12, v8
+	vfmsac.vf v4, fa2, v8
+	vfnmsac.vv v4, v12, v8
+	vfnmsac.vf v4, fa2, v8
+	vfmacc.vv v4, v12, v8, v0.t
+	vfmacc.vf v4, fa2, v8, v0.t
+	vfnmacc.vv v4, v12, v8, v0.t
+	vfnmacc.vf v4, fa2, v8, v0.t
+	vfmsac.vv v4, v12, v8, v0.t
+	vfmsac.vf v4, fa2, v8, v0.t
+	vfnmsac.vv v4, v12, v8, v0.t
+	vfnmsac.vf v4, fa2, v8, v0.t
+
+	vfwmacc.vv v4, v12, v8
+	vfwmacc.vf v4, fa2, v8
+	vfwnmacc.vv v4, v12, v8
+	vfwnmacc.vf v4, fa2, v8
+	vfwmsac.vv v4, v12, v8
+	vfwmsac.vf v4, fa2, v8
+	vfwnmsac.vv v4, v12, v8
+	vfwnmsac.vf v4, fa2, v8
+	vfwmacc.vv v4, v12, v8, v0.t
+	vfwmacc.vf v4, fa2, v8, v0.t
+	vfwnmacc.vv v4, v12, v8, v0.t
+	vfwnmacc.vf v4, fa2, v8, v0.t
+	vfwmsac.vv v4, v12, v8, v0.t
+	vfwmsac.vf v4, fa2, v8, v0.t
+	vfwnmsac.vv v4, v12, v8, v0.t
+	vfwnmsac.vf v4, fa2, v8, v0.t
+
+	vfsqrt.v v4, v8
+	vfsqrt.v v4, v8, v0.t
+	vfrsqrte7.v v4, v8
+	vfrsqrte7.v v4, v8, v0.t
+	vfrsqrt7.v v4, v8
+	vfrsqrt7.v v4, v8, v0.t
+	vfrece7.v v4, v8
+	vfrece7.v v4, v8, v0.t
+	vfrec7.v v4, v8
+	vfrec7.v v4, v8, v0.t
+	vfclass.v v4, v8
+	vfclass.v v4, v8, v0.t
+
+	vfmin.vv v4, v8, v12
+	vfmin.vf v4, v8, fa2
+	vfmax.vv v4, v8, v12
+	vfmax.vf v4, v8, fa2
+	vfmin.vv v4, v8, v12, v0.t
+	vfmin.vf v4, v8, fa2, v0.t
+	vfmax.vv v4, v8, v12, v0.t
+	vfmax.vf v4, v8, fa2, v0.t
+
+	vfneg.v v4, v8
+	vfneg.v v4, v8, v0.t
+
+	vfsgnj.vv v4, v8, v12
+	vfsgnj.vf v4, v8, fa2
+	vfsgnjn.vv v4, v8, v12
+	vfsgnjn.vf v4, v8, fa2
+	vfsgnjx.vv v4, v8, v12
+	vfsgnjx.vf v4, v8, fa2
+	vfsgnj.vv v4, v8, v12, v0.t
+	vfsgnj.vf v4, v8, fa2, v0.t
+	vfsgnjn.vv v4, v8, v12, v0.t
+	vfsgnjn.vf v4, v8, fa2, v0.t
+	vfsgnjx.vv v4, v8, v12, v0.t
+	vfsgnjx.vf v4, v8, fa2, v0.t
+
+	# Aliases
+	vmfgt.vv v4, v8, v12
+	vmfge.vv v4, v8, v12
+	vmfgt.vv v4, v8, v12, v0.t
+	vmfge.vv v4, v8, v12, v0.t
+
+	vmfeq.vv v4, v8, v12
+	vmfeq.vf v4, v8, fa2
+	vmfne.vv v4, v8, v12
+	vmfne.vf v4, v8, fa2
+	vmflt.vv v4, v8, v12
+	vmflt.vf v4, v8, fa2
+	vmfle.vv v4, v8, v12
+	vmfle.vf v4, v8, fa2
+	vmfgt.vf v4, v8, fa2
+	vmfge.vf v4, v8, fa2
+	vmfeq.vv v4, v8, v12, v0.t
+	vmfeq.vf v4, v8, fa2, v0.t
+	vmfne.vv v4, v8, v12, v0.t
+	vmfne.vf v4, v8, fa2, v0.t
+	vmflt.vv v4, v8, v12, v0.t
+	vmflt.vf v4, v8, fa2, v0.t
+	vmfle.vv v4, v8, v12, v0.t
+	vmfle.vf v4, v8, fa2, v0.t
+	vmfgt.vf v4, v8, fa2, v0.t
+	vmfge.vf v4, v8, fa2, v0.t
+
+	vfmerge.vfm v4, v8, fa2, v0
+	vfmv.v.f v4, fa1
+
+	vfcvt.xu.f.v v4, v8
+	vfcvt.x.f.v v4, v8
+	vfcvt.rtz.xu.f.v v4, v8
+	vfcvt.rtz.x.f.v v4, v8
+	vfcvt.f.xu.v v4, v8
+	vfcvt.f.x.v v4, v8
+	vfcvt.xu.f.v v4, v8, v0.t
+	vfcvt.x.f.v v4, v8, v0.t
+	vfcvt.rtz.xu.f.v v4, v8, v0.t
+	vfcvt.rtz.x.f.v v4, v8, v0.t
+	vfcvt.f.xu.v v4, v8, v0.t
+	vfcvt.f.x.v v4, v8, v0.t
+
+	vfwcvt.xu.f.v v4, v8
+	vfwcvt.x.f.v v4, v8
+	vfwcvt.rtz.xu.f.v v4, v8
+	vfwcvt.rtz.x.f.v v4, v8
+	vfwcvt.f.xu.v v4, v8
+	vfwcvt.f.x.v v4, v8
+	vfwcvt.f.f.v v4, v8
+	vfwcvt.xu.f.v v4, v8, v0.t
+	vfwcvt.x.f.v v4, v8, v0.t
+	vfwcvt.rtz.xu.f.v v4, v8, v0.t
+	vfwcvt.rtz.x.f.v v4, v8, v0.t
+	vfwcvt.f.xu.v v4, v8, v0.t
+	vfwcvt.f.x.v v4, v8, v0.t
+	vfwcvt.f.f.v v4, v8, v0.t
+
+	vfncvt.xu.f.w v4, v8
+	vfncvt.x.f.w v4, v8
+	vfncvt.rtz.xu.f.w v4, v8
+	vfncvt.rtz.x.f.w v4, v8
+	vfncvt.f.xu.w v4, v8
+	vfncvt.f.x.w v4, v8
+	vfncvt.f.f.w v4, v8
+	vfncvt.rod.f.f.w v4, v8
+	vfncvt.xu.f.w v4, v8, v0.t
+	vfncvt.x.f.w v4, v8, v0.t
+	vfncvt.rtz.xu.f.w v4, v8, v0.t
+	vfncvt.rtz.x.f.w v4, v8, v0.t
+	vfncvt.f.xu.w v4, v8, v0.t
+	vfncvt.f.x.w v4, v8, v0.t
+	vfncvt.f.f.w v4, v8, v0.t
+	vfncvt.rod.f.f.w v4, v8, v0.t
+
+	vredsum.vs v4, v8, v12
+	vredmaxu.vs v4, v8, v8
+	vredmax.vs v4, v8, v8
+	vredminu.vs v4, v8, v8
+	vredmin.vs v4, v8, v8
+	vredand.vs v4, v8, v12
+	vredor.vs v4, v8, v12
+	vredxor.vs v4, v8, v12
+	vredsum.vs v4, v8, v12, v0.t
+	vredmaxu.vs v4, v8, v8, v0.t
+	vredmax.vs v4, v8, v8, v0.t
+	vredminu.vs v4, v8, v8, v0.t
+	vredmin.vs v4, v8, v8, v0.t
+	vredand.vs v4, v8, v12, v0.t
+	vredor.vs v4, v8, v12, v0.t
+	vredxor.vs v4, v8, v12, v0.t
+
+	vwredsumu.vs v4, v8, v12
+	vwredsum.vs v4, v8, v12
+	vwredsumu.vs v4, v8, v12, v0.t
+	vwredsum.vs v4, v8, v12, v0.t
+
+	vfredosum.vs v4, v8, v12
+	vfredsum.vs v4, v8, v12
+	vfredmax.vs v4, v8, v12
+	vfredmin.vs v4, v8, v12
+	vfredosum.vs v4, v8, v12, v0.t
+	vfredsum.vs v4, v8, v12, v0.t
+	vfredmax.vs v4, v8, v12, v0.t
+	vfredmin.vs v4, v8, v12, v0.t
+
+	vfwredosum.vs v4, v8, v12
+	vfwredsum.vs v4, v8, v12
+	vfwredosum.vs v4, v8, v12, v0.t
+	vfwredsum.vs v4, v8, v12, v0.t
+
+	# Aliases
+	vmcpy.m v4, v8
+	vmmv.m v4, v8
+	vmclr.m v4
+	vmset.m v4
+	vmnot.m v4, v8
+
+	vmand.mm v4, v8, v12
+	vmnand.mm v4, v8, v12
+	vmandnot.mm v4, v8, v12
+	vmxor.mm v4, v8, v12
+	vmor.mm v4, v8, v12
+	vmnor.mm v4, v8, v12
+	vmornot.mm v4, v8, v12
+	vmxnor.mm v4, v8, v12
+
+	vpopc.m a0, v12
+	vfirst.m a0, v12
+	vmsbf.m v4, v8
+	vmsif.m v4, v8
+	vmsof.m v4, v8
+	viota.m v4, v8
+	vid.v v4
+	vpopc.m a0, v12, v0.t
+	vfirst.m a0, v12, v0.t
+	vmsbf.m v4, v8, v0.t
+	vmsif.m v4, v8, v0.t
+	vmsof.m v4, v8, v0.t
+	viota.m v4, v8, v0.t
+	vid.v v4, v0.t
+
+	vmv.x.s a0, v12
+	vmv.s.x v4, a0
+
+	vfmv.f.s fa0, v8
+	vfmv.s.f v4, fa1
+
+	vslideup.vx v4, v8, a1
+	vslideup.vi v4, v8, 0
+	vslideup.vi v4, v8, 31
+	vslidedown.vx v4, v8, a1
+	vslidedown.vi v4, v8, 0
+	vslidedown.vi v4, v8, 31
+	vslideup.vx v4, v8, a1, v0.t
+	vslideup.vi v4, v8, 0, v0.t
+	vslideup.vi v4, v8, 31, v0.t
+	vslidedown.vx v4, v8, a1, v0.t
+	vslidedown.vi v4, v8, 0, v0.t
+	vslidedown.vi v4, v8, 31, v0.t
+
+	vslide1up.vx v4, v8, a1
+	vslide1down.vx v4, v8, a1
+	vslide1up.vx v4, v8, a1, v0.t
+	vslide1down.vx v4, v8, a1, v0.t
+
+	vfslide1up.vf v4, v8, fa1
+	vfslide1down.vf v4, v8, fa1
+	vfslide1up.vf v4, v8, fa1, v0.t
+	vfslide1down.vf v4, v8, fa1, v0.t
+
+	vrgather.vv v4, v8, v12
+	vrgather.vx v4, v8, a1
+	vrgather.vi v4, v8, 0
+	vrgather.vi v4, v8, 31
+	vrgather.vv v4, v8, v12, v0.t
+	vrgather.vx v4, v8, a1, v0.t
+	vrgather.vi v4, v8, 0, v0.t
+	vrgather.vi v4, v8, 31, v0.t
+
+	vrgatherei16.vv v4, v8, v12
+	vrgatherei16.vv v4, v8, v12, v0.t
+
+	vcompress.vm v4, v8, v12
+
+	vmv1r.v v1, v2
+	vmv2r.v v2, v4
+	vmv4r.v v4, v8
+	vmv8r.v v0, v8