RISC-V/SiFive: Added SiFive custom cache control instructions.users/riscv/binutils-integration-branch

According to the chapter 10 of the following U74-MC manual,
https://sifive.cdn.prismic.io/sifive/6d9a2510-2632-44f3-adb9-d0430f139372_sifive_coreip_U74MC_AXI4_rtl_v19_08p2p0_release_manual.pdf

and the implementations of freedom-metal,
https://github.com/sifive/freedom-metal/blob/v201908-branch/src/cache.c

* Encodings,
31-25   24-20 19-15 14-12  11-7  6-0
FUNCT7  RS2   RS1   FUNCT3 RD    OPCODE
1111110 00000 xxxxx 000    00000 1110011 CFLUSH.D.L1
1111110 00010 xxxxx 000    00000 1110011 CDISCARD.D.L1
1111110 00001 00000 000    00000 1110011 CFLUSH.I.L1

* Extension names,
xsfcflushdlone:   CFLUSH.D.L1.
xsfcdiscarddlone: CDISCARD.D.L1.
xsfcflushilone:   CFLUSH.I.L1.

* Vendor target triples,
For assembler, the target vendor is defined as TARGET_VENDOR in the
gas/config.h, but I don't see any related settings in bfd/config.h
and opcode/config.  Since we may have vendor relocations in the future,
and these relocation numbers may repeat, I add a new RISCV_TARGET_VENDOR
in the bfd/config.h for riscv.  The vendor name will be stored in the
bfd/cpu-riscv.c, so that all tools (gas, bfd, opcode, ...) can get
the vendor name from the configure setting.

If the --with-arch configure option, -march gas option and elf architecture
attributes are not set, then we will generate the default ISA string
according to the chosen target vendor.  For example, if you build the
binutils with the configure option, --target=riscv64-sifive-elf, then
the assembler will find the whole supported extension tables in the
bfd/elfxx-riscv.c, and generate the suitable ISA string.

bfd/
	* configure.ac (RISCV_TARGET_VENDOR): Defined to store target_vendor,
	only when the target is riscv*.
	* config.in: Regenerated.
	* configure: Regenerated.
	* cpu-riscv.c (riscv_vendor_name): Defined to RISCV_TARGET_VENDOR.
	* cpu-riscv.h (enum riscv_spec_class): Added VENDOR_SPEC_CLASS_SIFIVE.
	* elfxx-riscv. (EXT_SIFIVE): Defined to choose the default extensions
	for sifive.
	(riscv_supported_vendor_sifive_ext): Added extensions for sifive cache
	control instructions.
	(riscv_supported_std_ext, riscv_all_supported_ext): Updated.
	(riscv_get_default_ext_version): Updated.
	(riscv_set_default_arch): Updated.
gas/
	* config/tc-riscv.c (VENDOR_SIFIVE_EXT): Added.
	(riscv_extended_subset_supports): Handle INSN_CLASS_XSF*.
	(op_vendor_sifive_hash): Added to store sifive opcodes.
	(md_begin): Init the op_vendor_sifive_hash.
	(riscv_find_extended_opcode_hash): Find the opcodes from
	op_vendor_sifive_hash.
	* testsuite/gas/riscv/extended/sifive-insns.d: New testcase.
	* testsuite/gas/riscv/extended/sifive-insns.s: Likewise.
include/
	* opcode/riscv-opc-extended.h: Added opcodes for sifive cache
	instructions.
	* opcode/riscv.h (enum riscv_extended_insn_class): Added INSN_CLASS_XSF*.
opcodes/
	* riscv-opc.c (riscv_vendor_sifive_opcodes): Added.
	(riscv_extended_opcodes): Updated.

3 files changed, 33 insertions, 1 deletions

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 99165f5..8e28adb7 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -40,6 +40,7 @@ enum
 {
   DRAFT_EXT = 0,
   VENDOR_THEAD_EXT,
+  VENDOR_SIFIVE_EXT,
   EXTENDED_EXT_NUM
 };
 
@@ -310,6 +311,13 @@ riscv_extended_subset_supports (int insn_class)
     case INSN_CLASS_THEADSE:
       return riscv_subset_supports ("xtheadse");
 
+    case INSN_CLASS_XSF_CDISCARDDLONE:
+      return riscv_subset_supports ("xsfcdiscarddlone");
+    case INSN_CLASS_XSF_CFLUSHDLONE:
+      return riscv_subset_supports ("xsfcflushdlone");
+    case INSN_CLASS_XSF_CFLUSHILONE:
+      return riscv_subset_supports ("xsfcflushilone");
+
     default:
       as_fatal ("internal: unknown INSN_CLASS (0x%x)", insn_class);
       return false;
@@ -461,6 +469,9 @@ static htab_t op_draft_hash = NULL;
 /* Handle of the T-HEAD OPCODE hash table.  */
 static htab_t op_vendor_thead_hash = NULL;
 
+/* Handle of the sifive OPCODE hash table.  */
+static htab_t op_vendor_sifive_hash = NULL;
+
 /* Handle of the type of .insn hash table.  */
 static htab_t insn_type_hash = NULL;
 
@@ -1481,7 +1492,10 @@ md_begin (void)
   hash_reg_names (RCLASS_VECR, riscv_vecr_names_numeric, NVECR);
   hash_reg_names (RCLASS_VECM, riscv_vecm_names_numeric, NVECM);
   op_draft_hash = init_opcode_hash (riscv_extended_opcodes[DRAFT_EXT], false);
-  op_vendor_thead_hash = init_opcode_hash (riscv_extended_opcodes[VENDOR_THEAD_EXT], false);
+  op_vendor_thead_hash =
+	init_opcode_hash (riscv_extended_opcodes[VENDOR_THEAD_EXT], false);
+  op_vendor_sifive_hash =
+	init_opcode_hash (riscv_extended_opcodes[VENDOR_SIFIVE_EXT], false);
 }
 
 static insn_t
@@ -1593,6 +1607,8 @@ riscv_find_extended_opcode_hash (char *str ATTRIBUTE_UNUSED)
 	case VENDOR_THEAD_EXT:
 	  insn = (struct riscv_opcode *) str_hash_find (op_vendor_thead_hash, str);
 	  break;
+	case VENDOR_SIFIVE_EXT:
+	  insn = (struct riscv_opcode *) str_hash_find (op_vendor_sifive_hash, str);
 	default:
 	  break;
 	}
diff --git a/gas/testsuite/gas/riscv/extended/sifive-insns.d b/gas/testsuite/gas/riscv/extended/sifive-insns.d
new file mode 100644
index 0000000..ea6377a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/sifive-insns.d
@@ -0,0 +1,12 @@
+#as: -march=rv32i_xsfcdiscarddlone_xsfcflushdlone_xsfcflushilone
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+fc050073[ 	]+cflush.d.l1[ 	]+a0
+[ 	]+4:[ 	]+fc250073[ 	]+cdiscard.d.l1[ 	]+a0
+[ 	]+8:[ 	]+fc100073[ 	]+cflush.i.l1
diff --git a/gas/testsuite/gas/riscv/extended/sifive-insns.s b/gas/testsuite/gas/riscv/extended/sifive-insns.s
new file mode 100644
index 0000000..b44dad0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/extended/sifive-insns.s
@@ -0,0 +1,4 @@
+target:
+	cflush.d.l1	x10
+	cdiscard.d.l1	x10
+	cflush.i.l1