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authorJim Wilson <jimw@sifive.com>2018-01-17 14:04:16 -0800
committerJim Wilson <jimw@sifive.com>2018-01-17 14:04:16 -0800
commite925c834ecdb4a0ce595ad8d3da9c7d4f499ede0 (patch)
treef323c5eb0919e82237abab99213414c1e822d3e0 /gas
parent9e14690d06ac55136b7f051a2d2b8e173fa3bbdf (diff)
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RISC-V: Fix bug in prior addi/c.nop patch.
gas/ * config/tc-riscv.c (validate_riscv_insn) <'z'>: New. (riscv_ip) <'z'>: New. opcodes/ * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/config/tc-riscv.c10
2 files changed, 15 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 04c922b..a6c0e6c 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2018-01-17 Jim Wilson <jimw@sifive.com>
+
+ * config/tc-riscv.c (validate_riscv_insn) <'z'>: New.
+ (riscv_ip) <'z'>: New.
+
2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
* config/tc-i386.c (cpu_arch): Delete .cet. Add .ibt, .shstk.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index f60bea1..a84240d 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -570,6 +570,7 @@ validate_riscv_insn (const struct riscv_opcode *opc)
case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
+ case 'z': break;
case '[': break;
case ']': break;
case '0': break;
@@ -1712,6 +1713,15 @@ jump:
*imm_reloc = BFD_RELOC_RISCV_CALL;
continue;
+ case 'z':
+ if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
+ || imm_expr->X_op != O_constant
+ || imm_expr->X_add_number != 0)
+ break;
+ s = expr_end;
+ imm_expr->X_op = O_absent;
+ continue;
+
default:
as_fatal (_("internal error: bad argument type %c"), *args);
}