2010-02-10 Quentin Neill <quentin.neill@amd.com>

            Sebastian Pop  <sebastian.pop@amd.com>

gas:
        * config/tc-i386.c (vec_imm4) New operand type.
        (fits_in_imm4): New.
        (VEX_check_operands): New.
        (check_reverse): Call VEX_check_operands.
        (build_modrm_byte): Reintroduce code for 5
        operand insns.  Fix whitespace.

gas/testsuite:
        * gas/i386/x86-64-xop.d: Add vpermil2p[sd] tests.
        * gas/i386/x86-64-xop.s: Likewise.
        * gas/i386/xop.d: Likewise.
        * gas/i386/xop.s: Likewise.

opcodes:
        * i386-dis.c (OP_EX_VexImmW): Reintroduced
        function to handle 5th imm8 operand.
        (PREFIX_VEX_3A48): Added.
        (PREFIX_VEX_3A49): Added.
        (VEX_W_3A48_P_2): Added.
        (VEX_W_3A49_P_2): Added.
        (prefix table): Added entries for PREFIX_VEX_3A48
        and PREFIX_VEX_3A49.
        (vex table): Added entries for VEX_W_3A48_P_2 and
        and VEX_W_3A49_P_2.
        * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
        for Vec_Imm4 operands.
        * i386-opc.h (enum): Added Vec_Imm4.
        (i386_operand_type): Added vec_imm4.
        * i386-opc.tbl: Add entries for vpermilp[ds].
        * i386-init.h: Regenerated.
        * i386-tbl.h: Regenerated.

7 files changed, 432 insertions, 42 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9d78944..1861e6b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2010-02-10  Quentin Neill  <quentin.neill@amd.com>
+	    Sebastian Pop  <sebastian.pop@amd.com>
+
+	* config/tc-i386.c (vec_imm4) New operand type.
+	(fits_in_imm4): New.
+	(VEX_check_operands): New.
+	(check_reverse): Call VEX_check_operands.
+	(build_modrm_byte): Reintroduce code for 5
+	operand insns.  Fix whitespace.
+
 2010-02-10  Richard Sandiford  <r.sandiford@uk.ibm.com>
 
 	* config/tc-ppc.c (md_show_usage): Add -mpwr4, -mpwr5, -mpwr5x,
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index f091aa2..d9b9de4 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1436,6 +1436,7 @@ static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
+static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
 
 enum operand_type
 {
@@ -1711,6 +1712,12 @@ fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
 #endif
 }				/* fits_in_unsigned_long() */
 
+static INLINE int
+fits_in_imm4 (offsetT num)
+{
+  return (num & 0xf) == num;
+}
+
 static i386_operand_type
 smallest_imm_type (offsetT num)
 {
@@ -3724,6 +3731,29 @@ optimize_disp (void)
       }
 }
 
+/* Check if operands are valid for the instrucrtion.  Update VEX
+   operand types.  */
+
+static int
+VEX_check_operands (const insn_template *t)
+{
+  if (!t->opcode_modifier.vex)
+    return 0;
+
+  /* Only check VEX_Imm4, which must be the first operand.  */
+  if (t->operand_types[0].bitfield.vec_imm4)
+    {
+      if (i.op[0].imms->X_op != O_constant
+	  || !fits_in_imm4 (i.op[0].imms->X_add_number))
+	return 1;
+
+      /* Turn off Imm8 so that update_imm won't complain.  */
+      i.types[0] = vec_imm4;
+    }
+
+  return 0;
+}
+
 static const insn_template *
 match_template (void)
 {
@@ -4028,6 +4058,10 @@ check_reverse:
 	  continue;
 	}
 
+      /* Check if VEX operands are valid.  */
+      if (VEX_check_operands (t))
+	continue;
+
       /* We've found a match; break out of loop.  */
       break;
     }
@@ -4960,53 +4994,119 @@ build_modrm_byte (void)
       expressionS *exp;
 
       if (i.tm.opcode_modifier.veximmext
-	  && i.tm.opcode_modifier.immext)
-	{
-	  dest = i.operands - 2;
-	  gas_assert (dest == 3);
-	}
+          && i.tm.opcode_modifier.immext)
+        {
+          dest = i.operands - 2;
+          gas_assert (dest == 3);
+        }
       else
-	dest = i.operands - 1;
+        dest = i.operands - 1;
       nds = dest - 1;
 
-      /* This instruction must have 4 register operands
-	 or 3 register operands plus 1 memory operand.
-	 It must have VexNDS and VexImmExt.  */
+      /* There are 2 kinds of instructions:
+         1. 5 operands: 4 register operands or 3 register operands
+         plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
+         VexW0 or VexW1.  The destination must be either XMM or YMM
+         register.
+         2. 4 operands: 4 register operands or 3 register operands
+         plus 1 memory operand, VexXDS, and VexImmExt  */
       gas_assert ((i.reg_operands == 4
-		      || (i.reg_operands == 3 && i.mem_operands == 1))
-		  && i.tm.opcode_modifier.vexvvvv == VEXXDS
-		  && i.tm.opcode_modifier.veximmext
-	    && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
-		|| operand_type_equal (&i.tm.operand_types[dest], &regymm)));
-
-      /* Generate an 8bit immediate operand to encode the register
-	 operand.  */
-      exp = &im_expressions[i.imm_operands++];
-      i.op[i.operands].imms = exp;
-      i.types[i.operands] = imm8;
-      i.operands++;
-      /* If VexW1 is set, the first operand is the source and
-	 the second operand is encoded in the immediate operand.  */
-      if (i.tm.opcode_modifier.vexw == VEXW1)
-	{
-	  source = 0;
-	  reg_slot = 1;
-	}
+                   || (i.reg_operands == 3 && i.mem_operands == 1))
+                  && i.tm.opcode_modifier.vexvvvv == VEXXDS
+                  && (i.tm.opcode_modifier.veximmext
+                      || (i.imm_operands == 1
+                          && i.types[0].bitfield.vec_imm4
+                          && (i.tm.opcode_modifier.vexw == VEXW0
+                              || i.tm.opcode_modifier.vexw == VEXW1)
+                          && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
+                              || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
+
+      if (i.imm_operands == 0)
+        {
+          /* When there is no immediate operand, generate an 8bit
+             immediate operand to encode the first operand.  */
+          exp = &im_expressions[i.imm_operands++];
+          i.op[i.operands].imms = exp;
+          i.types[i.operands] = imm8;
+          i.operands++;
+          /* If VexW1 is set, the first operand is the source and
+             the second operand is encoded in the immediate operand.  */
+          if (i.tm.opcode_modifier.vexw == VEXW1)
+            {
+              source = 0;
+              reg_slot = 1;
+            }
+          else
+            {
+              source = 1;
+              reg_slot = 0;
+            }
+
+          /* FMA swaps REG and NDS.  */
+          if (i.tm.cpu_flags.bitfield.cpufma)
+            {
+              unsigned int tmp;
+              tmp = reg_slot;
+              reg_slot = nds;
+              nds = tmp;
+            }
+
+          gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], &regxmm)
+                      || operand_type_equal (&i.tm.operand_types[reg_slot],
+                                             &regymm));
+          exp->X_op = O_constant;
+          exp->X_add_number
+              = ((i.op[reg_slot].regs->reg_num
+                  + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
+        }
       else
-	{
-	  source = 1;
-	  reg_slot = 0;
-	}
-      gas_assert ((operand_type_equal (&i.tm.operand_types[reg_slot], &regxmm)
-		   || operand_type_equal (&i.tm.operand_types[reg_slot],
-					  &regymm))
-		  && (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
-		      || operand_type_equal (&i.tm.operand_types[nds],
-					     &regymm)));
-      exp->X_op = O_constant;
-      exp->X_add_number
-	= ((i.op[reg_slot].regs->reg_num
-	    + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
+        {
+          unsigned int imm_slot;
+
+          if (i.tm.opcode_modifier.vexw == VEXW0)
+            {
+              /* If VexW0 is set, the third operand is the source and
+                 the second operand is encoded in the immediate
+                 operand.  */
+              source = 2;
+              reg_slot = 1;
+            }
+          else
+            {
+              /* VexW1 is set, the second operand is the source and
+                 the third operand is encoded in the immediate
+                 operand.  */
+              source = 1;
+              reg_slot = 2;
+            }
+
+          if (i.tm.opcode_modifier.immext)
+            {
+              /* When ImmExt is set, the immdiate byte is the last
+                 operand.  */
+              imm_slot = i.operands - 1;
+              source--;
+              reg_slot--;
+            }
+          else
+            {
+              imm_slot = 0;
+
+              /* Turn on Imm8 so that output_imm will generate it.  */
+              i.types[imm_slot].bitfield.imm8 = 1;
+            }
+
+          gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], &regxmm)
+                  || operand_type_equal (&i.tm.operand_types[reg_slot],
+                                         &regymm));
+          i.op[imm_slot].imms->X_add_number
+              |= ((i.op[reg_slot].regs->reg_num
+                   + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
+        }
+
+      gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
+                  || operand_type_equal (&i.tm.operand_types[nds],
+                                         &regymm));
       i.vex.register_specifier = i.op[nds].regs;
     }
   else
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 46139b7..07455e4 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2010-02-10  Quentin Neill  <quentin.neill@amd.com>
+	    Sebastian Pop  <sebastian.pop@amd.com>
+
+	* gas/i386/x86-64-xop.d: Add vpermil2p[sd] tests.
+	* gas/i386/x86-64-xop.s: Likewise.
+	* gas/i386/xop.d: Likewise.
+	* gas/i386/xop.s: Likewise.
+
 2010-02-08  Christophe Lyon  <christophe.lyon@st.com>
 
 	* gas/arm/branch-reloc.s, gas/arm/branch-reloc.d,
diff --git a/gas/testsuite/gas/i386/x86-64-xop.d b/gas/testsuite/gas/i386/x86-64-xop.d
index 339fc61..33ff89d 100644
--- a/gas/testsuite/gas/i386/x86-64-xop.d
+++ b/gas/testsuite/gas/i386/x86-64-xop.d
@@ -294,6 +294,70 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	8f 68 78 cd f8 03[ 	]+vpcomw \$0x3,%xmm0,%xmm0,%xmm15
 [ 	]*[a-f0-9]+:	8f e8 20 cd 01 ff[ 	]+vpcomw \$0xff,\(%rcx\),%xmm11,%xmm0
 [ 	]*[a-f0-9]+:	8f e8 00 cd 0e 03[ 	]+vpcomw \$0x3,\(%rsi\),%xmm15,%xmm1
+[ 	]*[a-f0-9]+:	c4 43 21 49 d5 e3[ 	]+vpermil2pd \$0x3,%xmm14,%xmm13,%xmm11,%xmm10
+[ 	]*[a-f0-9]+:	c4 a3 71 49 04 07 f2[ 	]+vpermil2pd \$0x2,%xmm15,\(%rdi,%r8,1\),%xmm1,%xmm0
+[ 	]*[a-f0-9]+:	c4 83 79 49 54 e4 23 01[ 	]+vpermil2pd \$0x1,%xmm0,0x23\(%r12,%r12,8\),%xmm0,%xmm2
+[ 	]*[a-f0-9]+:	c4 c3 11 49 d7 30[ 	]+vpermil2pd \$0x0,%xmm3,%xmm15,%xmm13,%xmm2
+[ 	]*[a-f0-9]+:	c4 c3 21 49 c6 32[ 	]+vpermil2pd \$0x2,%xmm3,%xmm14,%xmm11,%xmm0
+[ 	]*[a-f0-9]+:	c4 e3 71 49 02 01[ 	]+vpermil2pd \$0x1,%xmm0,\(%rdx\),%xmm1,%xmm0
+[ 	]*[a-f0-9]+:	c4 63 79 49 c8 33[ 	]+vpermil2pd \$0x3,%xmm3,%xmm0,%xmm0,%xmm9
+[ 	]*[a-f0-9]+:	c4 83 79 49 5c e4 23 20[ 	]+vpermil2pd \$0x0,%xmm2,0x23\(%r12,%r12,8\),%xmm0,%xmm3
+[ 	]*[a-f0-9]+:	c4 e3 21 49 c7 00[ 	]+vpermil2pd \$0x0,%xmm0,%xmm7,%xmm11,%xmm0
+[ 	]*[a-f0-9]+:	c4 e3 01 49 c5 41[ 	]+vpermil2pd \$0x1,%xmm4,%xmm5,%xmm15,%xmm0
+[ 	]*[a-f0-9]+:	c4 43 f9 49 54 9c 04 83[ 	]+vpermil2pd \$0x3,0x4\(%r12,%rbx,4\),%xmm8,%xmm0,%xmm10
+[ 	]*[a-f0-9]+:	c4 e3 41 49 f0 12[ 	]+vpermil2pd \$0x2,%xmm1,%xmm0,%xmm7,%xmm6
+[ 	]*[a-f0-9]+:	c4 43 c9 49 54 1d 00 c1[ 	]+vpermil2pd \$0x1,0x0\(%r13,%rbx,1\),%xmm12,%xmm6,%xmm10
+[ 	]*[a-f0-9]+:	c4 63 79 49 ce 42[ 	]+vpermil2pd \$0x2,%xmm4,%xmm6,%xmm0,%xmm9
+[ 	]*[a-f0-9]+:	c4 63 c9 49 1c db 80[ 	]+vpermil2pd \$0x0,\(%rbx,%rbx,8\),%xmm8,%xmm6,%xmm11
+[ 	]*[a-f0-9]+:	c4 c3 49 49 c5 53[ 	]+vpermil2pd \$0x3,%xmm5,%xmm13,%xmm6,%xmm0
+[ 	]*[a-f0-9]+:	c4 63 7d 49 ed 71[ 	]+vpermil2pd \$0x1,%ymm7,%ymm5,%ymm0,%ymm13
+[ 	]*[a-f0-9]+:	c4 23 5d 49 24 49 70[ 	]+vpermil2pd \$0x0,%ymm7,\(%rcx,%r9,2\),%ymm4,%ymm12
+[ 	]*[a-f0-9]+:	c4 03 7d 49 04 1e 33[ 	]+vpermil2pd \$0x3,%ymm3,\(%r14,%r11,1\),%ymm0,%ymm8
+[ 	]*[a-f0-9]+:	c4 43 7d 49 8c 81 07 01 00 00 72[ 	]+vpermil2pd \$0x2,%ymm7,0x107\(%r9,%rax,4\),%ymm0,%ymm9
+[ 	]*[a-f0-9]+:	c4 03 7d 49 04 1e 72[ 	]+vpermil2pd \$0x2,%ymm7,\(%r14,%r11,1\),%ymm0,%ymm8
+[ 	]*[a-f0-9]+:	c4 a3 5d 49 04 49 03[ 	]+vpermil2pd \$0x3,%ymm0,\(%rcx,%r9,2\),%ymm4,%ymm0
+[ 	]*[a-f0-9]+:	c4 83 25 49 2c 1e 81[ 	]+vpermil2pd \$0x1,%ymm8,\(%r14,%r11,1\),%ymm11,%ymm5
+[ 	]*[a-f0-9]+:	c4 63 7d 49 2e 20[ 	]+vpermil2pd \$0x0,%ymm2,\(%rsi\),%ymm0,%ymm13
+[ 	]*[a-f0-9]+:	c4 63 ad 49 3c 31 01[ 	]+vpermil2pd \$0x1,\(%rcx,%rsi,1\),%ymm0,%ymm10,%ymm15
+[ 	]*[a-f0-9]+:	c4 c3 fd 49 01 c2[ 	]+vpermil2pd \$0x2,\(%r9\),%ymm12,%ymm0,%ymm0
+[ 	]*[a-f0-9]+:	c4 a3 a5 49 a4 31 d9 d8 15 00 80[ 	]+vpermil2pd \$0x0,0x15d8d9\(%rcx,%r14,1\),%ymm8,%ymm11,%ymm4
+[ 	]*[a-f0-9]+:	c4 c3 7d 49 c4 93[ 	]+vpermil2pd \$0x3,%ymm9,%ymm12,%ymm0,%ymm0
+[ 	]*[a-f0-9]+:	c4 03 8d 49 44 1d 00 13[ 	]+vpermil2pd \$0x3,0x0\(%r13,%r11,1\),%ymm1,%ymm14,%ymm8
+[ 	]*[a-f0-9]+:	c4 23 fd 49 9c 31 d9 d8 15 00 00[ 	]+vpermil2pd \$0x0,0x15d8d9\(%rcx,%r14,1\),%ymm0,%ymm0,%ymm11
+[ 	]*[a-f0-9]+:	c4 83 85 49 44 1d 00 11[ 	]+vpermil2pd \$0x1,0x0\(%r13,%r11,1\),%ymm1,%ymm15,%ymm0
+[ 	]*[a-f0-9]+:	c4 c3 25 49 ed 92[ 	]+vpermil2pd \$0x2,%ymm9,%ymm13,%ymm11,%ymm5
+[ 	]*[a-f0-9]+:	c4 03 79 48 7c e4 23 02[ 	]+vpermil2ps \$0x2,%xmm0,0x23\(%r12,%r12,8\),%xmm0,%xmm15
+[ 	]*[a-f0-9]+:	c4 03 61 48 4c e4 23 00[ 	]+vpermil2ps \$0x0,%xmm0,0x23\(%r12,%r12,8\),%xmm3,%xmm9
+[ 	]*[a-f0-9]+:	c4 43 41 48 dc 03[ 	]+vpermil2ps \$0x3,%xmm0,%xmm12,%xmm7,%xmm11
+[ 	]*[a-f0-9]+:	c4 e3 79 48 02 31[ 	]+vpermil2ps \$0x1,%xmm3,\(%rdx\),%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	c4 83 79 48 04 0e 32[ 	]+vpermil2ps \$0x2,%xmm3,\(%r14,%r9,1\),%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	c4 e3 71 48 02 31[ 	]+vpermil2ps \$0x1,%xmm3,\(%rdx\),%xmm1,%xmm0
+[ 	]*[a-f0-9]+:	c4 43 79 48 e0 30[ 	]+vpermil2ps \$0x0,%xmm3,%xmm8,%xmm0,%xmm12
+[ 	]*[a-f0-9]+:	c4 83 71 48 14 0e 33[ 	]+vpermil2ps \$0x3,%xmm3,\(%r14,%r9,1\),%xmm1,%xmm2
+[ 	]*[a-f0-9]+:	c4 43 f9 48 5c 05 00 01[ 	]+vpermil2ps \$0x1,0x0\(%r13,%rax,1\),%xmm0,%xmm0,%xmm11
+[ 	]*[a-f0-9]+:	c4 63 c9 48 17 f3[ 	]+vpermil2ps \$0x3,\(%rdi\),%xmm15,%xmm6,%xmm10
+[ 	]*[a-f0-9]+:	c4 c3 79 48 c5 02[ 	]+vpermil2ps \$0x2,%xmm0,%xmm13,%xmm0,%xmm0
+[ 	]*[a-f0-9]+:	c4 63 09 48 d0 40[ 	]+vpermil2ps \$0x0,%xmm4,%xmm0,%xmm14,%xmm10
+[ 	]*[a-f0-9]+:	c4 63 61 48 d8 01[ 	]+vpermil2ps \$0x1,%xmm0,%xmm0,%xmm3,%xmm11
+[ 	]*[a-f0-9]+:	c4 63 c9 48 14 db b2[ 	]+vpermil2ps \$0x2,\(%rbx,%rbx,8\),%xmm11,%xmm6,%xmm10
+[ 	]*[a-f0-9]+:	c4 63 49 48 fd 43[ 	]+vpermil2ps \$0x3,%xmm4,%xmm5,%xmm6,%xmm15
+[ 	]*[a-f0-9]+:	c4 43 f9 48 54 9c 04 00[ 	]+vpermil2ps \$0x0,0x4\(%r12,%rbx,4\),%xmm0,%xmm0,%xmm10
+[ 	]*[a-f0-9]+:	c4 e3 7d 48 06 01[ 	]+vpermil2ps \$0x1,%ymm0,\(%rsi\),%ymm0,%ymm0
+[ 	]*[a-f0-9]+:	c4 c3 25 48 84 81 07 01 00 00 f2[ 	]+vpermil2ps \$0x2,%ymm15,0x107\(%r9,%rax,4\),%ymm11,%ymm0
+[ 	]*[a-f0-9]+:	c4 e3 5d 48 c0 70[ 	]+vpermil2ps \$0x0,%ymm7,%ymm0,%ymm4,%ymm0
+[ 	]*[a-f0-9]+:	c4 23 5d 48 3c 49 73[ 	]+vpermil2ps \$0x3,%ymm7,\(%rcx,%r9,2\),%ymm4,%ymm15
+[ 	]*[a-f0-9]+:	c4 63 5d 48 f8 02[ 	]+vpermil2ps \$0x2,%ymm0,%ymm0,%ymm4,%ymm15
+[ 	]*[a-f0-9]+:	c4 43 05 48 ac 81 07 01 00 00 03[ 	]+vpermil2ps \$0x3,%ymm0,0x107\(%r9,%rax,4\),%ymm15,%ymm13
+[ 	]*[a-f0-9]+:	c4 43 0d 48 e8 70[ 	]+vpermil2ps \$0x0,%ymm7,%ymm8,%ymm14,%ymm13
+[ 	]*[a-f0-9]+:	c4 43 5d 48 ef 71[ 	]+vpermil2ps \$0x1,%ymm7,%ymm15,%ymm4,%ymm13
+[ 	]*[a-f0-9]+:	c4 23 fd 48 bc 31 d9 d8 15 00 00[ 	]+vpermil2ps \$0x0,0x15d8d9\(%rcx,%r14,1\),%ymm0,%ymm0,%ymm15
+[ 	]*[a-f0-9]+:	c4 83 85 48 64 1d 00 c3[ 	]+vpermil2ps \$0x3,0x0\(%r13,%r11,1\),%ymm12,%ymm15,%ymm4
+[ 	]*[a-f0-9]+:	c4 a3 fd 48 84 31 d9 d8 15 00 02[ 	]+vpermil2ps \$0x2,0x15d8d9\(%rcx,%r14,1\),%ymm0,%ymm0,%ymm0
+[ 	]*[a-f0-9]+:	c4 e3 65 48 e2 01[ 	]+vpermil2ps \$0x1,%ymm0,%ymm2,%ymm3,%ymm4
+[ 	]*[a-f0-9]+:	c4 e3 fd 48 24 31 c3[ 	]+vpermil2ps \$0x3,\(%rcx,%rsi,1\),%ymm12,%ymm0,%ymm4
+[ 	]*[a-f0-9]+:	c4 e3 fd 48 24 31 12[ 	]+vpermil2ps \$0x2,\(%rcx,%rsi,1\),%ymm1,%ymm0,%ymm4
+[ 	]*[a-f0-9]+:	c4 83 fd 48 64 1d 00 00[ 	]+vpermil2ps \$0x0,0x0\(%r13,%r11,1\),%ymm0,%ymm0,%ymm4
+[ 	]*[a-f0-9]+:	c4 e3 5d 48 c7 81[ 	]+vpermil2ps \$0x1,%ymm8,%ymm7,%ymm4,%ymm0
 [ 	]*[a-f0-9]+:	8f 69 78 c2 fa[ 	]+vphaddbd %xmm2,%xmm15
 [ 	]*[a-f0-9]+:	8f 69 78 c2 e0[ 	]+vphaddbd %xmm0,%xmm12
 [ 	]*[a-f0-9]+:	8f c9 78 c2 04 24[ 	]+vphaddbd \(%r12\),%xmm0
diff --git a/gas/testsuite/gas/i386/x86-64-xop.s b/gas/testsuite/gas/i386/x86-64-xop.s
index 9f878ea..98f3c46 100644
--- a/gas/testsuite/gas/i386/x86-64-xop.s
+++ b/gas/testsuite/gas/i386/x86-64-xop.s
@@ -310,6 +310,78 @@ _start:
     VPCOMW         $0x3,%xmm0,%xmm0,%xmm15
     VPCOMW         $0xFF,(%rcx),%xmm11,%xmm0
     VPCOMW         $0x3,(%rsi),%xmm15,%xmm1
+# Testing VPERMIL2PD imm8, xmm4, xmm3/mem128, xmm2, xmm1 (at&t syntax)
+    VPERMIL2PD     $0x3,%xmm14,%xmm13,%xmm11,%xmm10
+    VPERMIL2PD     $0x2,%xmm15,(%rdi,%r8),%xmm1,%xmm0
+    VPERMIL2PD     $0x1,%xmm0,0x23(%r12,%r12,8),%xmm0,%xmm2
+    VPERMIL2PD     $0x0,%xmm3,%xmm15,%xmm13,%xmm2
+    VPERMIL2PD     $0x2,%xmm3,%xmm14,%xmm11,%xmm0
+    VPERMIL2PD     $0x1,%xmm0,(%rdx),%xmm1,%xmm0
+    VPERMIL2PD     $0x3,%xmm3,%xmm0,%xmm0,%xmm9
+    VPERMIL2PD     $0x0,%xmm2,0x23(%r12,%r12,8),%xmm0,%xmm3
+# Testing VPERMIL2PD imm8, xmm4/mem128, xmm3, xmm2, xmm1 (at&t syntax)
+    VPERMIL2PD     $0x0,%xmm0,%xmm7,%xmm11,%xmm0
+    VPERMIL2PD     $0x1,%xmm4,%xmm5,%xmm15,%xmm0
+    VPERMIL2PD     $0x3,0x4(%r12,%rbx,4),%xmm8,%xmm0,%xmm10
+    VPERMIL2PD     $0x2,%xmm1,%xmm0,%xmm7,%xmm6
+    VPERMIL2PD     $0x1,(%r13,%rbx),%xmm12,%xmm6,%xmm10
+    VPERMIL2PD     $0x2,%xmm4,%xmm6,%xmm0,%xmm9
+    VPERMIL2PD     $0x0,(%rbx,%rbx,8),%xmm8,%xmm6,%xmm11
+    VPERMIL2PD     $0x3,%xmm5,%xmm13,%xmm6,%xmm0
+# Testing VPERMIL2PD imm8, ymm4, ymm3/mem256, ymm2, ymm1 (at&t syntax)
+    VPERMIL2PD     $0x1,%ymm7,%ymm5,%ymm0,%ymm13
+    VPERMIL2PD     $0x0,%ymm7,(%rcx,%r9,2),%ymm4,%ymm12
+    VPERMIL2PD     $0x3,%ymm3,(%r14,%r11),%ymm0,%ymm8
+    VPERMIL2PD     $0x2,%ymm7,0x107(%r9,%rax,4),%ymm0,%ymm9
+    VPERMIL2PD     $0x2,%ymm7,(%r14,%r11),%ymm0,%ymm8
+    VPERMIL2PD     $0x3,%ymm0,(%rcx,%r9,2),%ymm4,%ymm0
+    VPERMIL2PD     $0x1,%ymm8,(%r14,%r11),%ymm11,%ymm5
+    VPERMIL2PD     $0x0,%ymm2,(%rsi),%ymm0,%ymm13
+# Testing VPERMIL2PD imm8, ymm4/mem256, ymm3, ymm2, ymm1 (at&t syntax)
+    VPERMIL2PD     $0x1,(%rcx,%rsi),%ymm0,%ymm10,%ymm15
+    VPERMIL2PD     $0x2,(%r9),%ymm12,%ymm0,%ymm0
+    VPERMIL2PD     $0x0,0x15D8D9(%rcx,%r14,1),%ymm8,%ymm11,%ymm4
+    VPERMIL2PD     $0x3,%ymm9,%ymm12,%ymm0,%ymm0
+    VPERMIL2PD     $0x3,(%r13,%r11,1),%ymm1,%ymm14,%ymm8
+    VPERMIL2PD     $0x0,0x15D8D9(%rcx,%r14,1),%ymm0,%ymm0,%ymm11
+    VPERMIL2PD     $0x1,(%r13,%r11,1),%ymm1,%ymm15,%ymm0
+    VPERMIL2PD     $0x2,%ymm9,%ymm13,%ymm11,%ymm5
+# Testing VPERMIL2PS imm8, xmm4, xmm3/mem128, xmm2, xmm1 (at&t syntax)
+    VPERMIL2PS     $0x2,%xmm0,0x23(%r12,%r12,8),%xmm0,%xmm15
+    VPERMIL2PS     $0x0,%xmm0,0x23(%r12,%r12,8),%xmm3,%xmm9
+    VPERMIL2PS     $0x3,%xmm0,%xmm12,%xmm7,%xmm11
+    VPERMIL2PS     $0x1,%xmm3,(%rdx),%xmm0,%xmm0
+    VPERMIL2PS     $0x2,%xmm3,(%r14,%r9,1),%xmm0,%xmm0
+    VPERMIL2PS     $0x1,%xmm3,(%rdx),%xmm1,%xmm0
+    VPERMIL2PS     $0x0,%xmm3,%xmm8,%xmm0,%xmm12
+    VPERMIL2PS     $0x3,%xmm3,(%r14,%r9,1),%xmm1,%xmm2
+# Testing VPERMIL2PS imm8, xmm4/mem128, xmm3, xmm2, xmm1 (at&t syntax)
+    VPERMIL2PS     $0x1,(%r13,%rax),%xmm0,%xmm0,%xmm11
+    VPERMIL2PS     $0x3,(%rdi),%xmm15,%xmm6,%xmm10
+    VPERMIL2PS     $0x2,%xmm0,%xmm13,%xmm0,%xmm0
+    VPERMIL2PS     $0x0,%xmm4,%xmm0,%xmm14,%xmm10
+    VPERMIL2PS     $0x1,%xmm0,%xmm0,%xmm3,%xmm11
+    VPERMIL2PS     $0x2,(%rbx,%rbx,8),%xmm11,%xmm6,%xmm10
+    VPERMIL2PS     $0x3,%xmm4,%xmm5,%xmm6,%xmm15
+    VPERMIL2PS     $0x0,0x4(%r12,%rbx,4),%xmm0,%xmm0,%xmm10
+# Testing VPERMIL2PS imm8, ymm4, ymm3/mem256, ymm2, ymm1 (at&t syntax)
+    VPERMIL2PS     $0x1,%ymm0,(%rsi),%ymm0,%ymm0
+    VPERMIL2PS     $0x2,%ymm15,0x107(%r9,%rax,4),%ymm11,%ymm0
+    VPERMIL2PS     $0x0,%ymm7,%ymm0,%ymm4,%ymm0
+    VPERMIL2PS     $0x3,%ymm7,(%rcx,%r9,2),%ymm4,%ymm15
+    VPERMIL2PS     $0x2,%ymm0,%ymm0,%ymm4,%ymm15
+    VPERMIL2PS     $0x3,%ymm0,0x107(%r9,%rax,4),%ymm15,%ymm13
+    VPERMIL2PS     $0x0,%ymm7,%ymm8,%ymm14,%ymm13
+    VPERMIL2PS     $0x1,%ymm7,%ymm15,%ymm4,%ymm13
+# Testing VPERMIL2PS imm8, ymm4/mem256, ymm3, ymm2, ymm1 (at&t syntax)
+    VPERMIL2PS     $0x0,0x15D8D9(%rcx,%r14,1),%ymm0,%ymm0,%ymm15
+    VPERMIL2PS     $0x3,(%r13,%r11,1),%ymm12,%ymm15,%ymm4
+    VPERMIL2PS     $0x2,0x15D8D9(%rcx,%r14,1),%ymm0,%ymm0,%ymm0
+    VPERMIL2PS     $0x1,%ymm0,%ymm2,%ymm3,%ymm4
+    VPERMIL2PS     $0x3,(%rcx,%rsi),%ymm12,%ymm0,%ymm4
+    VPERMIL2PS     $0x2,(%rcx,%rsi),%ymm1,%ymm0,%ymm4
+    VPERMIL2PS     $0x0,(%r13,%r11,1),%ymm0,%ymm0,%ymm4
+    VPERMIL2PS     $0x1,%ymm8,%ymm7,%ymm4,%ymm0
 # Tests for op VPHADDBD xmm2/mem128, xmm1  (at&t syntax)
     VPHADDBD       %xmm2,%xmm15
     VPHADDBD       %xmm0,%xmm12
diff --git a/gas/testsuite/gas/i386/xop.d b/gas/testsuite/gas/i386/xop.d
index 70f001f..2358ee1 100644
--- a/gas/testsuite/gas/i386/xop.d
+++ b/gas/testsuite/gas/i386/xop.d
@@ -294,6 +294,70 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	8f e8 50 cd 08 03[ 	]+vpcomw \$0x3,\(%eax\),%xmm5,%xmm1
 [ 	]*[a-f0-9]+:	8f e8 78 cd f8 03[ 	]+vpcomw \$0x3,%xmm0,%xmm0,%xmm7
 [ 	]*[a-f0-9]+:	8f e8 50 cd c7 ff[ 	]+vpcomw \$0xff,%xmm7,%xmm5,%xmm0
+[ 	]*[a-f0-9]+:	c4 e3 41 49 00 50[ 	]+vpermil2pd \$0x0,%xmm5,\(%eax\),%xmm7,%xmm0
+[ 	]*[a-f0-9]+:	c4 e3 59 49 c2 11[ 	]+vpermil2pd \$0x1,%xmm1,%xmm2,%xmm4,%xmm0
+[ 	]*[a-f0-9]+:	c4 e3 41 49 10 42[ 	]+vpermil2pd \$0x2,%xmm4,\(%eax\),%xmm7,%xmm2
+[ 	]*[a-f0-9]+:	c4 e3 59 49 3c 83 33[ 	]+vpermil2pd \$0x3,%xmm3,\(%ebx,%eax,4\),%xmm4,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 79 49 f7 30[ 	]+vpermil2pd \$0x0,%xmm3,%xmm7,%xmm0,%xmm6
+[ 	]*[a-f0-9]+:	c4 e3 79 49 14 16 71[ 	]+vpermil2pd \$0x1,%xmm7,\(%esi,%edx,1\),%xmm0,%xmm2
+[ 	]*[a-f0-9]+:	c4 e3 59 49 fd 32[ 	]+vpermil2pd \$0x2,%xmm3,%xmm5,%xmm4,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 71 49 d0 33[ 	]+vpermil2pd \$0x3,%xmm3,%xmm0,%xmm1,%xmm2
+[ 	]*[a-f0-9]+:	c4 e3 69 49 f1 72[ 	]+vpermil2pd \$0x2,%xmm7,%xmm1,%xmm2,%xmm6
+[ 	]*[a-f0-9]+:	c4 e3 e9 49 bc 19 88 07 00 00 01[ 	]+vpermil2pd \$0x1,0x788\(%ecx,%ebx,1\),%xmm0,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 79 49 f9 40[ 	]+vpermil2pd \$0x0,%xmm4,%xmm1,%xmm0,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 59 49 c7 33[ 	]+vpermil2pd \$0x3,%xmm3,%xmm7,%xmm4,%xmm0
+[ 	]*[a-f0-9]+:	c4 e3 f9 49 b4 59 88 07 00 00 73[ 	]+vpermil2pd \$0x3,0x788\(%ecx,%ebx,2\),%xmm7,%xmm0,%xmm6
+[ 	]*[a-f0-9]+:	c4 e3 51 49 c7 31[ 	]+vpermil2pd \$0x1,%xmm3,%xmm7,%xmm5,%xmm0
+[ 	]*[a-f0-9]+:	c4 e3 59 49 f1 22[ 	]+vpermil2pd \$0x2,%xmm2,%xmm1,%xmm4,%xmm6
+[ 	]*[a-f0-9]+:	c4 e3 69 49 fb 03[ 	]+vpermil2pd \$0x3,%xmm0,%xmm3,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 75 49 d7 63[ 	]+vpermil2pd \$0x3,%ymm6,%ymm7,%ymm1,%ymm2
+[ 	]*[a-f0-9]+:	c4 e3 75 49 e7 61[ 	]+vpermil2pd \$0x1,%ymm6,%ymm7,%ymm1,%ymm4
+[ 	]*[a-f0-9]+:	c4 e3 55 49 7c 87 05 02[ 	]+vpermil2pd \$0x2,%ymm0,0x5\(%edi,%eax,4\),%ymm5,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 7d 49 d6 50[ 	]+vpermil2pd \$0x0,%ymm5,%ymm6,%ymm0,%ymm2
+[ 	]*[a-f0-9]+:	c4 e3 65 49 c7 43[ 	]+vpermil2pd \$0x3,%ymm4,%ymm7,%ymm3,%ymm0
+[ 	]*[a-f0-9]+:	c4 e3 6d 49 c6 70[ 	]+vpermil2pd \$0x0,%ymm7,%ymm6,%ymm2,%ymm0
+[ 	]*[a-f0-9]+:	c4 e3 75 49 3e 42[ 	]+vpermil2pd \$0x2,%ymm4,\(%esi\),%ymm1,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 75 49 f8 61[ 	]+vpermil2pd \$0x1,%ymm6,%ymm0,%ymm1,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 c5 49 01 51[ 	]+vpermil2pd \$0x1,\(%ecx\),%ymm5,%ymm7,%ymm0
+[ 	]*[a-f0-9]+:	c4 e3 c5 49 04 46 43[ 	]+vpermil2pd \$0x3,\(%esi,%eax,2\),%ymm4,%ymm7,%ymm0
+[ 	]*[a-f0-9]+:	c4 e3 e5 49 39 00[ 	]+vpermil2pd \$0x0,\(%ecx\),%ymm0,%ymm3,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 cd 49 3c 06 22[ 	]+vpermil2pd \$0x2,\(%esi,%eax,1\),%ymm2,%ymm6,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 cd 49 09 00[ 	]+vpermil2pd \$0x0,\(%ecx\),%ymm0,%ymm6,%ymm1
+[ 	]*[a-f0-9]+:	c4 e3 45 49 c3 22[ 	]+vpermil2pd \$0x2,%ymm2,%ymm3,%ymm7,%ymm0
+[ 	]*[a-f0-9]+:	c4 e3 45 49 ca 03[ 	]+vpermil2pd \$0x3,%ymm0,%ymm2,%ymm7,%ymm1
+[ 	]*[a-f0-9]+:	c4 e3 5d 49 f8 51[ 	]+vpermil2pd \$0x1,%ymm5,%ymm0,%ymm4,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 79 48 fc 33[ 	]+vpermil2ps \$0x3,%xmm3,%xmm4,%xmm0,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 59 48 38 01[ 	]+vpermil2ps \$0x1,%xmm0,\(%eax\),%xmm4,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 41 48 38 32[ 	]+vpermil2ps \$0x2,%xmm3,\(%eax\),%xmm7,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 41 48 14 c3 73[ 	]+vpermil2ps \$0x3,%xmm7,\(%ebx,%eax,8\),%xmm7,%xmm2
+[ 	]*[a-f0-9]+:	c4 e3 41 48 f8 72[ 	]+vpermil2ps \$0x2,%xmm7,%xmm0,%xmm7,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 79 48 3c 16 73[ 	]+vpermil2ps \$0x3,%xmm7,\(%esi,%edx,1\),%xmm0,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 41 48 fc 71[ 	]+vpermil2ps \$0x1,%xmm7,%xmm4,%xmm7,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 41 48 10 30[ 	]+vpermil2ps \$0x0,%xmm3,\(%eax\),%xmm7,%xmm2
+[ 	]*[a-f0-9]+:	c4 e3 c1 48 33 72[ 	]+vpermil2ps \$0x2,\(%ebx\),%xmm7,%xmm7,%xmm6
+[ 	]*[a-f0-9]+:	c4 e3 d1 48 04 1b 73[ 	]+vpermil2ps \$0x3,\(%ebx,%ebx,1\),%xmm7,%xmm5,%xmm0
+[ 	]*[a-f0-9]+:	c4 e3 c1 48 34 1b 10[ 	]+vpermil2ps \$0x0,\(%ebx,%ebx,1\),%xmm1,%xmm7,%xmm6
+[ 	]*[a-f0-9]+:	c4 e3 69 48 f9 02[ 	]+vpermil2ps \$0x2,%xmm0,%xmm1,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 e9 48 34 1b 72[ 	]+vpermil2ps \$0x2,\(%ebx,%ebx,1\),%xmm7,%xmm2,%xmm6
+[ 	]*[a-f0-9]+:	c4 e3 c1 48 34 1b 13[ 	]+vpermil2ps \$0x3,\(%ebx,%ebx,1\),%xmm1,%xmm7,%xmm6
+[ 	]*[a-f0-9]+:	c4 e3 e9 48 3c 1b 70[ 	]+vpermil2ps \$0x0,\(%ebx,%ebx,1\),%xmm7,%xmm2,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 41 48 f9 71[ 	]+vpermil2ps \$0x1,%xmm7,%xmm1,%xmm7,%xmm7
+[ 	]*[a-f0-9]+:	c4 e3 75 48 d7 61[ 	]+vpermil2ps \$0x1,%ymm6,%ymm7,%ymm1,%ymm2
+[ 	]*[a-f0-9]+:	c4 e3 45 48 c6 73[ 	]+vpermil2ps \$0x3,%ymm7,%ymm6,%ymm7,%ymm0
+[ 	]*[a-f0-9]+:	c4 e3 45 48 d6 52[ 	]+vpermil2ps \$0x2,%ymm5,%ymm6,%ymm7,%ymm2
+[ 	]*[a-f0-9]+:	c4 e3 45 48 f8 20[ 	]+vpermil2ps \$0x0,%ymm2,%ymm0,%ymm7,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 45 48 04 cf 63[ 	]+vpermil2ps \$0x3,%ymm6,\(%edi,%ecx,8\),%ymm7,%ymm0
+[ 	]*[a-f0-9]+:	c4 e3 45 48 c7 62[ 	]+vpermil2ps \$0x2,%ymm6,%ymm7,%ymm7,%ymm0
+[ 	]*[a-f0-9]+:	c4 e3 75 48 d6 70[ 	]+vpermil2ps \$0x0,%ymm7,%ymm6,%ymm1,%ymm2
+[ 	]*[a-f0-9]+:	c4 e3 75 48 06 61[ 	]+vpermil2ps \$0x1,%ymm6,\(%esi\),%ymm1,%ymm0
+[ 	]*[a-f0-9]+:	c4 e3 fd 48 7c 43 0c 42[ 	]+vpermil2ps \$0x2,0xc\(%ebx,%eax,2\),%ymm4,%ymm0,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 6d 48 c6 51[ 	]+vpermil2ps \$0x1,%ymm5,%ymm6,%ymm2,%ymm0
+[ 	]*[a-f0-9]+:	c4 e3 cd 48 3c 06 43[ 	]+vpermil2ps \$0x3,\(%esi,%eax,1\),%ymm4,%ymm6,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 cd 48 04 de 31[ 	]+vpermil2ps \$0x1,\(%esi,%ebx,8\),%ymm3,%ymm6,%ymm0
+[ 	]*[a-f0-9]+:	c4 e3 fd 48 0c 48 70[ 	]+vpermil2ps \$0x0,\(%eax,%ecx,2\),%ymm7,%ymm0,%ymm1
+[ 	]*[a-f0-9]+:	c4 e3 45 48 ff 62[ 	]+vpermil2ps \$0x2,%ymm6,%ymm7,%ymm7,%ymm7
+[ 	]*[a-f0-9]+:	c4 e3 6d 48 c3 43[ 	]+vpermil2ps \$0x3,%ymm4,%ymm3,%ymm2,%ymm0
+[ 	]*[a-f0-9]+:	c4 e3 45 48 fe 00[ 	]+vpermil2ps \$0x0,%ymm0,%ymm6,%ymm7,%ymm7
 [ 	]*[a-f0-9]+:	8f e9 78 c2 ff[ 	]+vphaddbd %xmm7,%xmm7
 [ 	]*[a-f0-9]+:	8f e9 78 c2 f0[ 	]+vphaddbd %xmm0,%xmm6
 [ 	]*[a-f0-9]+:	8f e9 78 c2 03[ 	]+vphaddbd \(%ebx\),%xmm0
diff --git a/gas/testsuite/gas/i386/xop.s b/gas/testsuite/gas/i386/xop.s
index fc161c2..5b7697a 100644
--- a/gas/testsuite/gas/i386/xop.s
+++ b/gas/testsuite/gas/i386/xop.s
@@ -310,6 +310,78 @@ _start:
     VPCOMW         $0x3,(%eax),%xmm5,%xmm1
     VPCOMW         $0x3,%xmm0,%xmm0,%xmm7
     VPCOMW         $0xFF,%xmm7,%xmm5,%xmm0
+# Testing VPERMIL2PD imm8, xmm4, xmm3/mem128, xmm2, xmm1 (at&t syntax)
+    VPERMIL2PD     $0x0,%xmm5,(%eax),%xmm7,%xmm0
+    VPERMIL2PD     $0x1,%xmm1,%xmm2,%xmm4,%xmm0
+    VPERMIL2PD     $0x2,%xmm4,(%eax),%xmm7,%xmm2
+    VPERMIL2PD     $0x3,%xmm3,(%ebx,%eax,4),%xmm4,%xmm7
+    VPERMIL2PD     $0x0,%xmm3,%xmm7,%xmm0,%xmm6
+    VPERMIL2PD     $0x1,%xmm7,(%esi,%edx),%xmm0,%xmm2
+    VPERMIL2PD     $0x2,%xmm3,%xmm5,%xmm4,%xmm7
+    VPERMIL2PD     $0x3,%xmm3,%xmm0,%xmm1,%xmm2
+# Testing VPERMIL2PD imm8, xmm4/mem128, xmm3, xmm2, xmm1 (at&t syntax)
+    VPERMIL2PD     $0x2,%xmm7,%xmm1,%xmm2,%xmm6
+    VPERMIL2PD     $0x1,0x788(%ecx,%ebx,1),%xmm0,%xmm2,%xmm7
+    VPERMIL2PD     $0x0,%xmm4,%xmm1,%xmm0,%xmm7
+    VPERMIL2PD     $0x3,%xmm3,%xmm7,%xmm4,%xmm0
+    VPERMIL2PD     $0x3,0x788(%ecx,%ebx,2),%xmm7,%xmm0,%xmm6
+    VPERMIL2PD     $0x1,%xmm3,%xmm7,%xmm5,%xmm0
+    VPERMIL2PD     $0x2,%xmm2,%xmm1,%xmm4,%xmm6
+    VPERMIL2PD     $0x3,%xmm0,%xmm3,%xmm2,%xmm7
+# Testing VPERMIL2PD imm8, ymm4, ymm3/mem256, ymm2, ymm1 (at&t syntax)
+    VPERMIL2PD     $0x3,%ymm6,%ymm7,%ymm1,%ymm2
+    VPERMIL2PD     $0x1,%ymm6,%ymm7,%ymm1,%ymm4
+    VPERMIL2PD     $0x2,%ymm0,0x5(%edi,%eax,4),%ymm5,%ymm7
+    VPERMIL2PD     $0x0,%ymm5,%ymm6,%ymm0,%ymm2
+    VPERMIL2PD     $0x3,%ymm4,%ymm7,%ymm3,%ymm0
+    VPERMIL2PD     $0x0,%ymm7,%ymm6,%ymm2,%ymm0
+    VPERMIL2PD     $0x2,%ymm4,(%esi),%ymm1,%ymm7
+    VPERMIL2PD     $0x1,%ymm6,%ymm0,%ymm1,%ymm7
+# Testing VPERMIL2PD imm8, ymm4/mem256, ymm3, ymm2, ymm1 (at&t syntax)
+    VPERMIL2PD     $0x1,(%ecx),%ymm5,%ymm7,%ymm0
+    VPERMIL2PD     $0x3,(%esi,%eax,2),%ymm4,%ymm7,%ymm0
+    VPERMIL2PD     $0x0,(%ecx),%ymm0,%ymm3,%ymm7
+    VPERMIL2PD     $0x2,(%esi,%eax,1),%ymm2,%ymm6,%ymm7
+    VPERMIL2PD     $0x0,(%ecx),%ymm0,%ymm6,%ymm1
+    VPERMIL2PD     $0x2,%ymm2,%ymm3,%ymm7,%ymm0
+    VPERMIL2PD     $0x3,%ymm0,%ymm2,%ymm7,%ymm1
+    VPERMIL2PD     $0x1,%ymm5,%ymm0,%ymm4,%ymm7
+# Testing VPERMIL2PS imm8, xmm4, xmm3/mem128, xmm2, xmm1 (at&t syntax)
+    VPERMIL2PS     $0x3,%xmm3,%xmm4,%xmm0,%xmm7
+    VPERMIL2PS     $0x1,%xmm0,(%eax),%xmm4,%xmm7
+    VPERMIL2PS     $0x2,%xmm3,(%eax),%xmm7,%xmm7
+    VPERMIL2PS     $0x3,%xmm7,(%ebx,%eax,8),%xmm7,%xmm2
+    VPERMIL2PS     $0x2,%xmm7,%xmm0,%xmm7,%xmm7
+    VPERMIL2PS     $0x3,%xmm7,(%esi,%edx),%xmm0,%xmm7
+    VPERMIL2PS     $0x1,%xmm7,%xmm4,%xmm7,%xmm7
+    VPERMIL2PS     $0x0,%xmm3,(%eax),%xmm7,%xmm2
+# Testing VPERMIL2PS imm8, xmm4/mem128, xmm3, xmm2, xmm1 (at&t syntax)
+    VPERMIL2PS     $0x2,(%ebx),%xmm7,%xmm7,%xmm6
+    VPERMIL2PS     $0x3,(%ebx,%ebx),%xmm7,%xmm5,%xmm0
+    VPERMIL2PS     $0x0,(%ebx,%ebx),%xmm1,%xmm7,%xmm6
+    VPERMIL2PS     $0x2,%xmm0,%xmm1,%xmm2,%xmm7
+    VPERMIL2PS     $0x2,(%ebx,%ebx),%xmm7,%xmm2,%xmm6
+    VPERMIL2PS     $0x3,(%ebx,%ebx),%xmm1,%xmm7,%xmm6
+    VPERMIL2PS     $0x0,(%ebx,%ebx),%xmm7,%xmm2,%xmm7
+    VPERMIL2PS     $0x1,%xmm7,%xmm1,%xmm7,%xmm7
+# Testing VPERMIL2PS imm8, ymm4, ymm3/mem256, ymm2, ymm1 (at&t syntax)
+    VPERMIL2PS     $0x1,%ymm6,%ymm7,%ymm1,%ymm2
+    VPERMIL2PS     $0x3,%ymm7,%ymm6,%ymm7,%ymm0
+    VPERMIL2PS     $0x2,%ymm5,%ymm6,%ymm7,%ymm2
+    VPERMIL2PS     $0x0,%ymm2,%ymm0,%ymm7,%ymm7
+    VPERMIL2PS     $0x3,%ymm6,(%edi,%ecx,8),%ymm7,%ymm0
+    VPERMIL2PS     $0x2,%ymm6,%ymm7,%ymm7,%ymm0
+    VPERMIL2PS     $0x0,%ymm7,%ymm6,%ymm1,%ymm2
+    VPERMIL2PS     $0x1,%ymm6,(%esi),%ymm1,%ymm0
+# Testing VPERMIL2PS imm8, ymm4/mem256, ymm3, ymm2, ymm1 (at&t syntax)
+    VPERMIL2PS     $0x2,0xC(%ebx,%eax,2),%ymm4,%ymm0,%ymm7
+    VPERMIL2PS     $0x1,%ymm5,%ymm6,%ymm2,%ymm0
+    VPERMIL2PS     $0x3,(%esi,%eax,1),%ymm4,%ymm6,%ymm7
+    VPERMIL2PS     $0x1,(%esi,%ebx,8),%ymm3,%ymm6,%ymm0
+    VPERMIL2PS     $0x0,(%eax,%ecx,2),%ymm7,%ymm0,%ymm1
+    VPERMIL2PS     $0x2,%ymm6,%ymm7,%ymm7,%ymm7
+    VPERMIL2PS     $0x3,%ymm4,%ymm3,%ymm2,%ymm0
+    VPERMIL2PS     $0x0,%ymm0,%ymm6,%ymm7,%ymm7
 # Tests for op VPHADDBD xmm2/mem128, xmm1  (at&t syntax)
     VPHADDBD       %xmm7,%xmm7
     VPHADDBD       %xmm0,%xmm6