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authorSudakshina Das <sudi.das@arm.com>2018-10-05 10:49:53 +0100
committerRichard Earnshaw <Richard.Earnshaw@arm.com>2018-10-05 11:31:19 +0100
commit7fadb25d6faf2665305016ceb4aeaeeb86015569 (patch)
tree77cdab957104d20d892ee3b8c5e14c837f9b9fa9 /gas
parent23f233a595dc7d8b9a6ababe7c4527f743c0cec1 (diff)
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[Arm, 2/3] Add instruction SB for AArch32
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools) This patch adds the instruction SB. This instruction is retrospectively made optional for all versions of the architecture from ARMv8.0 to ARMv8.4 and is mandatory from ARMv8.5. Hence adding a new "+sb" for older archtectures. *** include/ChangeLog *** 2018-10-05 Sudakshina Das <sudi.das@arm.com> * opcode/arm.h (ARM_EXT2_SB): New. (ARM_ARCH_V8_5A): Add ARM_EXT2_SB by default. *** opcodes/ChangeLog *** 2018-10-05 Sudakshina Das <sudi.das@arm.com> * arm-dis.c (arm_opcodes): Add sb. (thumb32_opcodes): Likewise. *** gas/ChangeLog *** 2018-10-05 Sudakshina Das <sudi.das@arm.com> * config/tc-arm.c (arm_ext_sb): New. (insns): Add new sb instruction. (arm_extensions): Add "sb". * doc/c-arm.texi: Document the above. * testsuite/gas/arm/sb-bad.d: New test. * testsuite/gas/arm/sb-bad.l: New test. * testsuite/gas/arm/sb-thumb1.d: New test. * testsuite/gas/arm/sb-thumb2.d: New test. * testsuite/gas/arm/sb.s: New test. * testsuite/gas/arm/sb1.d: New test. * testsuite/gas/arm/sb2.d: New test.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog14
-rw-r--r--gas/config/tc-arm.c12
-rw-r--r--gas/doc/c-arm.texi2
-rw-r--r--gas/testsuite/gas/arm/sb-bad.d5
-rw-r--r--gas/testsuite/gas/arm/sb-bad.l2
-rw-r--r--gas/testsuite/gas/arm/sb-thumb1.d11
-rw-r--r--gas/testsuite/gas/arm/sb-thumb2.d11
-rw-r--r--gas/testsuite/gas/arm/sb.s4
-rw-r--r--gas/testsuite/gas/arm/sb1.d11
-rw-r--r--gas/testsuite/gas/arm/sb2.d11
10 files changed, 83 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index a04d90d..9bdeb22 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,19 @@
2018-10-05 Sudakshina Das <sudi.das@arm.com>
+ * config/tc-arm.c (arm_ext_sb): New.
+ (insns): Add new sb instruction.
+ (arm_extensions): Add "sb".
+ * doc/c-arm.texi: Document the above.
+ * testsuite/gas/arm/sb-bad.d: New test.
+ * testsuite/gas/arm/sb-bad.l: New test.
+ * testsuite/gas/arm/sb-thumb1.d: New test.
+ * testsuite/gas/arm/sb-thumb2.d: New test.
+ * testsuite/gas/arm/sb.s: New test.
+ * testsuite/gas/arm/sb1.d: New test.
+ * testsuite/gas/arm/sb2.d: New test.
+
+2018-10-05 Sudakshina Das <sudi.das@arm.com>
+
* config/tc-arm.c (arm_archs): New entry for armv8.5-a.
(cpu_arch_ver): Likewise.
* doc/c-arm.texi: Add documentation for the same.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index ef3af3a..1ecaa45 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -256,6 +256,8 @@ static const arm_feature_set arm_ext_v8_2 =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
static const arm_feature_set arm_ext_v8_3 =
ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
+static const arm_feature_set arm_ext_sb =
+ ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB);
static const arm_feature_set arm_arch_any = ARM_ANY;
#ifdef OBJ_ELF
@@ -21516,6 +21518,13 @@ static const struct asm_opcode insns[] =
cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
+ /* ARMv8.5-A instructions. */
+#undef ARM_VARIANT
+#define ARM_VARIANT & arm_ext_sb
+#undef THUMB_VARIANT
+#define THUMB_VARIANT & arm_ext_sb
+ TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
+
/* ARMv8-M instructions. */
#undef ARM_VARIANT
#define ARM_VARIANT NULL
@@ -26418,6 +26427,9 @@ static const struct arm_option_extension_value_table arm_extensions[] =
ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
+ ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
+ ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
+ ARM_ARCH_V8A),
ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 522a1db..18008c4 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -189,6 +189,8 @@ The following extensions are currently supported:
@code{mp} (Multiprocessing Extensions for v7-A and v7-R
architectures),
@code{os} (Operating System for v6M architecture),
+@code{sb} (Speculation Barrier Instruction for v8-A architectures, added by
+default from v8.5-A),
@code{sec} (Security Extensions for v6K and v7-A architectures),
@code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
@code{virt} (Virtualization Extensions for v7-A architecture, implies
diff --git a/gas/testsuite/gas/arm/sb-bad.d b/gas/testsuite/gas/arm/sb-bad.d
new file mode 100644
index 0000000..9367dc1
--- /dev/null
+++ b/gas/testsuite/gas/arm/sb-bad.d
@@ -0,0 +1,5 @@
+# Check sb without +sb
+#name: invalid sb instruction without +sb
+#source: sb.s
+#as: -march=armv8.2-a
+#error_output: sb-bad.l
diff --git a/gas/testsuite/gas/arm/sb-bad.l b/gas/testsuite/gas/arm/sb-bad.l
new file mode 100644
index 0000000..f27253e
--- /dev/null
+++ b/gas/testsuite/gas/arm/sb-bad.l
@@ -0,0 +1,2 @@
+[^:]*: Assembler messages:
+[^:]*:4: Error: selected processor does not support `sb' in ARM mode
diff --git a/gas/testsuite/gas/arm/sb-thumb1.d b/gas/testsuite/gas/arm/sb-thumb1.d
new file mode 100644
index 0000000..dc3bc49
--- /dev/null
+++ b/gas/testsuite/gas/arm/sb-thumb1.d
@@ -0,0 +1,11 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: SB instruction (Thumb)
+#source: sb.s
+#as: -march=armv8.5-a -mthumb
+
+# Test SB Instructio
+
+.*: *file format .*arm.*
+
+Disassembly of section .text:
+.*> f3bf 8f70 sb
diff --git a/gas/testsuite/gas/arm/sb-thumb2.d b/gas/testsuite/gas/arm/sb-thumb2.d
new file mode 100644
index 0000000..892ca8f
--- /dev/null
+++ b/gas/testsuite/gas/arm/sb-thumb2.d
@@ -0,0 +1,11 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: SB instruction (Thumb) with +sb
+#source: sb.s
+#as: -march=armv8-a+sb -mthumb
+
+# Test SB Instructio
+
+.*: *file format .*arm.*
+
+Disassembly of section .text:
+.*> f3bf 8f70 sb
diff --git a/gas/testsuite/gas/arm/sb.s b/gas/testsuite/gas/arm/sb.s
new file mode 100644
index 0000000..9d88753
--- /dev/null
+++ b/gas/testsuite/gas/arm/sb.s
@@ -0,0 +1,4 @@
+@ Test case to validate SB
+.section .text
+.syntax unified
+ sb
diff --git a/gas/testsuite/gas/arm/sb1.d b/gas/testsuite/gas/arm/sb1.d
new file mode 100644
index 0000000..c263d79
--- /dev/null
+++ b/gas/testsuite/gas/arm/sb1.d
@@ -0,0 +1,11 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: SB instruction
+#source: sb.s
+#as: -march=armv8.5-a
+
+# Test SB Instructio
+
+.*: *file format .*arm.*
+
+Disassembly of section .text:
+.*> f57ff070 sb
diff --git a/gas/testsuite/gas/arm/sb2.d b/gas/testsuite/gas/arm/sb2.d
new file mode 100644
index 0000000..cb41e09
--- /dev/null
+++ b/gas/testsuite/gas/arm/sb2.d
@@ -0,0 +1,11 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: SB instruction with +sb
+#source: sb.s
+#as: -march=armv8-a+sb
+
+# Test SB Instructio
+
+.*: *file format .*arm.*
+
+Disassembly of section .text:
+.*> f57ff070 sb