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author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-06-28 17:43:57 +0200 |
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committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-09-22 18:06:09 +0200 |
commit | 547c18d9bb95571261dbd17f4767194037eb82bd (patch) | |
tree | ba5189db19567b97acc4c916c7d864f7c1c6356d /gas | |
parent | a9ba8bc2d396fb8ae2b892f3bc6be8cdfe4b555c (diff) | |
download | gdb-547c18d9bb95571261dbd17f4767194037eb82bd.zip gdb-547c18d9bb95571261dbd17f4767194037eb82bd.tar.gz gdb-547c18d9bb95571261dbd17f4767194037eb82bd.tar.bz2 |
RISC-V: Add T-Head SYNC vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadSync extension, a collection of
T-Head-specific multi-processor synchronization instructions.
The 'th' prefix and the "XTheadSync" extension are documented in a PR
for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'gas')
-rw-r--r-- | gas/doc/c-riscv.texi | 5 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/x-thead-sync-fail.d | 3 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/x-thead-sync-fail.l | 6 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/x-thead-sync-fail.s | 6 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/x-thead-sync.d | 14 | ||||
-rw-r--r-- | gas/testsuite/gas/riscv/x-thead-sync.s | 6 |
6 files changed, 40 insertions, 0 deletions
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 10e9429..c55dd0b 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -709,4 +709,9 @@ The XTheadCmo extension provides instructions for cache management. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadSync +The XTheadSync extension provides instructions for multi-processor synchronization. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. + @end table diff --git a/gas/testsuite/gas/riscv/x-thead-sync-fail.d b/gas/testsuite/gas/riscv/x-thead-sync-fail.d new file mode 100644 index 0000000..1d3fdbd --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-sync-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_xtheadsync +#source: x-thead-sync-fail.s +#error_output: x-thead-sync-fail.l diff --git a/gas/testsuite/gas/riscv/x-thead-sync-fail.l b/gas/testsuite/gas/riscv/x-thead-sync-fail.l new file mode 100644 index 0000000..5242000 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-sync-fail.l @@ -0,0 +1,6 @@ +.*: Assembler messages: +.*: Error: illegal operands `th.sfence.vmas' +.*: Error: illegal operands `th.sync a0' +.*: Error: illegal operands `th.sync.i a0' +.*: Error: illegal operands `th.sync.is a0' +.*: Error: illegal operands `th.sync.s a0' diff --git a/gas/testsuite/gas/riscv/x-thead-sync-fail.s b/gas/testsuite/gas/riscv/x-thead-sync-fail.s new file mode 100644 index 0000000..722a6da --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-sync-fail.s @@ -0,0 +1,6 @@ +target: + th.sfence.vmas + th.sync a0 + th.sync.i a0 + th.sync.is a0 + th.sync.s a0 diff --git a/gas/testsuite/gas/riscv/x-thead-sync.d b/gas/testsuite/gas/riscv/x-thead-sync.d new file mode 100644 index 0000000..3c5e9ea --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-sync.d @@ -0,0 +1,14 @@ +#as: -march=rv64i_xtheadsync +#source: x-thead-sync.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+04b5000b[ ]+th.sfence.vmas[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+0180000b[ ]+th.sync +[ ]+[0-9a-f]+:[ ]+01a0000b[ ]+th.sync.i +[ ]+[0-9a-f]+:[ ]+01b0000b[ ]+th.sync.is +[ ]+[0-9a-f]+:[ ]+0190000b[ ]+th.sync.s diff --git a/gas/testsuite/gas/riscv/x-thead-sync.s b/gas/testsuite/gas/riscv/x-thead-sync.s new file mode 100644 index 0000000..85b4856 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-sync.s @@ -0,0 +1,6 @@ +target: + th.sfence.vmas a0, a1 + th.sync + th.sync.i + th.sync.is + th.sync.s |