aarch64: Add new SVE saturating conversion instructions

This patch adds the SVE SQCVTN, SQCVTUN and UQCVTN instructions,
which are available when FEAT_SME2 is implemented.

7 files changed, 93 insertions, 0 deletions

diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-5-invalid.d b/gas/testsuite/gas/aarch64/sve2-sme2-5-invalid.d
new file mode 100644
index 0000000..190f2c8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-5-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme2
+#source: sve2-sme2-5-invalid.s
+#error_output: sve2-sme2-5-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-5-invalid.l b/gas/testsuite/gas/aarch64/sve2-sme2-5-invalid.l
new file mode 100644
index 0000000..e08001c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-5-invalid.l
@@ -0,0 +1,27 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqcvtn 0,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqcvtn z0\.h,0'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.h,{z1\.s-z2\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `sqcvtun z0\.h,{z0\.s-z2\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `sqcvtn z0\.h,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvtun z0\.s,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqcvtun z0\.b, {z0\.s-z3\.s}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqcvtun z0\.h, {z0\.d-z3\.d}
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvtn z0\.s,{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqcvtn z0\.b, {z0\.s-z3\.s}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqcvtn z0\.h, {z0\.d-z3\.d}
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvtun z0\.b,{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqcvtun z0\.b, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqcvtun z0\.h, {z0\.d-z1\.d}
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvtn z0\.s,{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqcvtn z0\.h, {z0\.d-z1\.d}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqcvtn z0\.b, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqcvtn z0\.h,{z2\.s-z3\.s}'
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-5-invalid.s b/gas/testsuite/gas/aarch64/sve2-sme2-5-invalid.s
new file mode 100644
index 0000000..d2d6e3c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-5-invalid.s
@@ -0,0 +1,12 @@
+	sqcvtn	0, { z0.s - z1.s }
+	sqcvtn	z0.h, 0
+
+	sqcvtn	z0.h, { z1.s - z2.s }
+	sqcvtun	z0.h, { z0.s - z2.s }
+	sqcvtn	z0.h, { z0.s - z3.s }
+	sqcvtun	z0.s, { z0.s - z3.s }
+	sqcvtn	z0.s, { z0.h - z3.h }
+	sqcvtun	z0.b, { z0.h - z1.h }
+	sqcvtn	z0.s, { z0.d - z1.d }
+
+	movprfx z0, z4; sqcvtn z0.h, { z2.s - z3.s }
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-5-noarch.d b/gas/testsuite/gas/aarch64/sve2-sme2-5-noarch.d
new file mode 100644
index 0000000..3d09a37
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-5-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sve2-sme2-5.s
+#error_output: sve2-sme2-5-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-5-noarch.l b/gas/testsuite/gas/aarch64/sve2-sme2-5-noarch.l
new file mode 100644
index 0000000..de50d04
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-5-noarch.l
@@ -0,0 +1,13 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z31\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.h,{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z14\.h,{z20\.s-z21\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z31\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.h,{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z26\.h,{z14\.s-z15\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z31\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.h,{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z29\.h,{z6\.s-z7\.s}'
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-5.d b/gas/testsuite/gas/aarch64/sve2-sme2-5.d
new file mode 100644
index 0000000..a1e5dc1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-5.d
@@ -0,0 +1,21 @@
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+:	45314000 	sqcvtn	z0\.h, {z0\.s-z1\.s}
+[^:]+:	4531401f 	sqcvtn	z31\.h, {z0\.s-z1\.s}
+[^:]+:	453143c0 	sqcvtn	z0\.h, {z30\.s-z31\.s}
+[^:]+:	4531428e 	sqcvtn	z14\.h, {z20\.s-z21\.s}
+[^:]+:	45315000 	sqcvtun	z0\.h, {z0\.s-z1\.s}
+[^:]+:	4531501f 	sqcvtun	z31\.h, {z0\.s-z1\.s}
+[^:]+:	453153c0 	sqcvtun	z0\.h, {z30\.s-z31\.s}
+[^:]+:	453151da 	sqcvtun	z26\.h, {z14\.s-z15\.s}
+[^:]+:	45314800 	uqcvtn	z0\.h, {z0\.s-z1\.s}
+[^:]+:	4531481f 	uqcvtn	z31\.h, {z0\.s-z1\.s}
+[^:]+:	45314bc0 	uqcvtn	z0\.h, {z30\.s-z31\.s}
+[^:]+:	453148dd 	uqcvtn	z29\.h, {z6\.s-z7\.s}
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-5.s b/gas/testsuite/gas/aarch64/sve2-sme2-5.s
new file mode 100644
index 0000000..a42f5a2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-5.s
@@ -0,0 +1,14 @@
+	sqcvtn	z0.h, { z0.s - z1.s }
+	sqcvtn	z31.h, { z0.s - z1.s }
+	sqcvtn	z0.h, { z30.s - z31.s }
+	sqcvtn	z14.h, { z20.s - z21.s }
+
+	sqcvtun	z0.h, { z0.s - z1.s }
+	sqcvtun	z31.h, { z0.s - z1.s }
+	sqcvtun	z0.h, { z30.s - z31.s }
+	sqcvtun	z26.h, { z14.s - z15.s }
+
+	uqcvtn	z0.h, { z0.s - z1.s }
+	uqcvtn	z31.h, { z0.s - z1.s }
+	uqcvtn	z0.h, { z30.s - z31.s }
+	uqcvtn	z29.h, { z6.s - z7.s }