Fix spelling typos.

11 files changed, 73 insertions, 59 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 94fc3c0..bd3333b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,19 @@
 2017-07-18  Nick Clifton  <nickc@redhat.com>
 
+	PR 21775
+	* config/tc-arm.c: Fix spelling typos.
+	* config/tc-mips.c: Likewise.
+	* config/tc-msp430.c: Likewise.
+	* config/tc-sh64.c: Likewise.
+	* config/tc-tic4x.c: Likewise.
+	* ecoff.c: Likewise.
+	* testsuite/gas/arm/ldr-bad.l: Likewise.
+	* testsuite/gas/arm/ldr-t-bad.l: Likewise.
+	* testsuite/gas/tic54x/opcodes.s: Likewise.
+	* testsuite/gas/msp340/errata_warns.l: Likewise.
+
+2017-07-18  Nick Clifton  <nickc@redhat.com>
+
 	* po/uk.po: Updated Ukranian translation.
 
 2017-07-17  Georg-Johann Lay  <avr@gjlay.de>
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 08ce141..a036b1a 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -8979,7 +8979,7 @@ check_ldr_r15_aligned (void)
 	      && (inst.operands[0].reg == REG_PC
 	      && inst.operands[1].reg == REG_PC
 	      && (inst.reloc.exp.X_add_number & 0x3)),
-	      _("ldr to register 15 must be 4-byte alligned"));
+	      _("ldr to register 15 must be 4-byte aligned"));
 }
 
 static void
@@ -23542,7 +23542,7 @@ md_apply_fix (fixS *	fixP,
       /* We are going to store value (shifted right by two) in the
 	 instruction, in a 24 bit, signed field.  Bits 26 through 32 either
 	 all clear or all set and bit 0 must be clear.  For B/BL bit 1 must
-	 also be be clear.  */
+	 also be clear.  */
       if (value & temp)
 	as_bad_where (fixP->fx_file, fixP->fx_line,
 		      _("misaligned branch destination"));
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 4eeb5ee..3804df2 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -4897,7 +4897,7 @@ match_expression (struct mips_arg_info *arg, expressionS *value,
 }
 
 /* Try to get a constant expression from the next tokens in ARG.  Consume
-   the tokens and return return true on success, storing the constant value
+   the tokens and return true on success, storing the constant value
    in *VALUE.  */
 
 static bfd_boolean
@@ -15314,7 +15314,7 @@ fix_bad_misaligned_jump_p (fixS *fixP, int shift)
    We accept BFD_RELOC_16_PCREL_S2 relocations against MIPS16 and microMIPS
    symbols or BFD_RELOC_MICROMIPS_16_PCREL_S1 relocations against regular
    MIPS symbols and associated with BAL instructions as these instructions
-   may be be converted to JALX by the linker.  */
+   may be converted to JALX by the linker.  */
 
 static bfd_boolean
 fix_bad_cross_mode_branch_p (fixS *fixP)
diff --git a/gas/config/tc-msp430.c b/gas/config/tc-msp430.c
index 0430f2e..91e0a73 100644
--- a/gas/config/tc-msp430.c
+++ b/gas/config/tc-msp430.c
@@ -2631,7 +2631,7 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
 
 		case NOP_CHECK_CPU12:
 		  if (silicon_errata_warn & SILICON_ERRATA_CPU12)
-		    as_warn (_("CPU12: CMP/BIT with PC destinstion ignores next instruction"));
+		    as_warn (_("CPU12: CMP/BIT with PC destination ignores next instruction"));
 
 		  if (silicon_errata_fix & SILICON_ERRATA_CPU12)
 		    doit = TRUE;
@@ -2724,9 +2724,9 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
 		   || is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
 	    {
 	      if (silicon_errata_fix & SILICON_ERRATA_CPU11)
-		as_bad (_("CPU11: PC is destinstion of SR altering instruction"));
+		as_bad (_("CPU11: PC is destination of SR altering instruction"));
 	      else if (silicon_errata_warn & SILICON_ERRATA_CPU11)
-		as_warn (_("CPU11: PC is destinstion of SR altering instruction"));
+		as_warn (_("CPU11: PC is destination of SR altering instruction"));
 	    }
 	  
 	  /* If the status register is the destination...  */
@@ -2741,9 +2741,9 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
 		  ))
 	    {
 	      if (silicon_errata_fix & SILICON_ERRATA_CPU13)
-		as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+		as_bad (_("CPU13: SR is destination of SR altering instruction"));
 	      else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
-		as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+		as_warn (_("CPU13: SR is destination of SR altering instruction"));
 	    }
 	  
 	  if (is_opcode ("clr") && bin == 0x4302 /* CLR R2*/)
@@ -2849,9 +2849,9 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
 		  ))
 	    {
 	      if (silicon_errata_fix & SILICON_ERRATA_CPU13)
-		as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+		as_bad (_("CPU13: SR is destination of SR altering instruction"));
 	      else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
-		as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+		as_warn (_("CPU13: SR is destination of SR altering instruction"));
 	    }
 	  
 	  if (extended_op)
@@ -3410,9 +3410,9 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
 	       || is_opcode ("bicx") || is_opcode ("bisx") || is_opcode ("movx")))
 	{
 	  if (silicon_errata_fix & SILICON_ERRATA_CPU11)
-	    as_bad (_("CPU11: PC is destinstion of SR altering instruction"));
+	    as_bad (_("CPU11: PC is destination of SR altering instruction"));
 	  else if (silicon_errata_warn & SILICON_ERRATA_CPU11)
-	    as_warn (_("CPU11: PC is destinstion of SR altering instruction"));
+	    as_warn (_("CPU11: PC is destination of SR altering instruction"));
 	}
 	  
       /* If the status register is the destination...  */
@@ -3427,9 +3427,9 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
 	      ))
 	{
 	  if (silicon_errata_fix & SILICON_ERRATA_CPU13)
-	    as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+	    as_bad (_("CPU13: SR is destination of SR altering instruction"));
 	  else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
-	    as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+	    as_warn (_("CPU13: SR is destination of SR altering instruction"));
 	}
 	  
       if (   (is_opcode ("bic") && bin == 0xc232)
@@ -3605,9 +3605,9 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
 	  && (is_opcode ("rra") || is_opcode ("rrc") || is_opcode ("sxt")))
 	{
 	  if (silicon_errata_fix & SILICON_ERRATA_CPU13)
-	    as_bad (_("CPU13: SR is destinstion of SR altering instruction"));
+	    as_bad (_("CPU13: SR is destination of SR altering instruction"));
 	  else if (silicon_errata_warn & SILICON_ERRATA_CPU13)
-	    as_warn (_("CPU13: SR is destinstion of SR altering instruction"));
+	    as_warn (_("CPU13: SR is destination of SR altering instruction"));
 	}
 	  
       insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2);
diff --git a/gas/config/tc-sh64.c b/gas/config/tc-sh64.c
index 4ba5d80..6f39c37 100644
--- a/gas/config/tc-sh64.c
+++ b/gas/config/tc-sh64.c
@@ -3030,7 +3030,7 @@ sh64_target_mach (void)
   return (sh64_abi == sh64_abi_64) ? bfd_mach_sh5 : 0;
 }
 
-/* This is MD_PCREL_FROM_SECTION, we we define so it is called instead of
+/* This is MD_PCREL_FROM_SECTION, we define so it is called instead of
    md_pcrel_from (in tc-sh.c).  */
 
 valueT
diff --git a/gas/config/tc-tic4x.c b/gas/config/tc-tic4x.c
index 50db237..0953815 100644
--- a/gas/config/tc-tic4x.c
+++ b/gas/config/tc-tic4x.c
@@ -2353,7 +2353,7 @@ tic4x_insn_check (tic4x_insn_t *tinsn)
       if (tinsn->operands[1].mode == M_REGISTER
 	  && tinsn->operands[tinsn->num_operands-1].mode == M_REGISTER
 	  && tinsn->operands[1].expr.X_add_number == tinsn->operands[tinsn->num_operands-1].expr.X_add_number )
-        as_warn (_("Equal parallell destination registers, one result will be discarded"));
+        as_warn (_("Equal parallel destination registers, one result will be discarded"));
     }
 }
 
diff --git a/gas/ecoff.c b/gas/ecoff.c
index 608d72b..325c3de 100644
--- a/gas/ecoff.c
+++ b/gas/ecoff.c
@@ -618,7 +618,7 @@
     #26             48  0x00000030  struct no name { ifd = -1, index = 1048575 }
 */
 
-/* Redefinition of of storage classes as an enumeration for better
+/* Redefinition of storage classes as an enumeration for better
    debugging.  */
 
 typedef enum sc {
diff --git a/gas/testsuite/gas/arm/ldr-bad.l b/gas/testsuite/gas/arm/ldr-bad.l
index 554b4a3..6fc2071 100644
--- a/gas/testsuite/gas/arm/ldr-bad.l
+++ b/gas/testsuite/gas/arm/ldr-bad.l
@@ -1,7 +1,7 @@
 [^:]*: Assembler messages:
 [^:]*:5: Warning: destination register same as write-back base
-[^:]*:9: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,\[r15,#5\]'
-[^:]*:12: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,.-0xab7'
+[^:]*:9: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,\[r15,#5\]'
+[^:]*:12: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,.-0xab7'
 [^:]*:15: Warning: destination register same as write-back base
 [^:]*:16: Error: cannot use register index with PC-relative addressing -- `ldr r2,\[r15,r2\]!'
 [^:]*:19: Error: cannot use register index with PC-relative addressing -- `ldr r1,\[r1,r15\]'
diff --git a/gas/testsuite/gas/arm/ldr-t-bad.l b/gas/testsuite/gas/arm/ldr-t-bad.l
index 95f420a..d83648b 100644
--- a/gas/testsuite/gas/arm/ldr-t-bad.l
+++ b/gas/testsuite/gas/arm/ldr-t-bad.l
@@ -1,9 +1,9 @@
 [^:]*: Assembler messages:
 [^:]*:8: Error: registers may not be the same -- `ldr r1,\[r1,#5\]!'
-[^:]*:12: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,\[r15,#5\]'
+[^:]*:12: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,\[r15,#5\]'
 [^:]*:16: Error: branch must be last instruction in IT block -- `ldrge r15,\[r15,#4\]'
 [^:]*:25: Error: branch must be last instruction in IT block -- `ldrge r15,.0x4'
-[^:]*:30: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,.-0xab7'
+[^:]*:30: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,.-0xab7'
 [^:]*:36: Error: branch must be last instruction in IT block -- `ldrge r15,\[r15,r1\]'
 [^:]*:41: Error: r13 not allowed here -- `ldr r1,\[r2,r13\]'
 [^:]*:42: Error: r15 not allowed here -- `ldr r2,\[r2,r15\]'
diff --git a/gas/testsuite/gas/msp430/errata_warns.l b/gas/testsuite/gas/msp430/errata_warns.l
index 52df6b9..699274b 100644
--- a/gas/testsuite/gas/msp430/errata_warns.l
+++ b/gas/testsuite/gas/msp430/errata_warns.l
@@ -6,39 +6,39 @@
 [^:]*:13: Warning: CPU8: Stack pointer accessed with an odd offset
 [^:]*:14: Warning: CPU8: Stack pointer accessed with an odd offset
 [^:]*:15: Warning: CPU8: Stack pointer accessed with an odd offset
-[^:]*:18: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:19: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:20: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:21: Warning: CPU12: CMP/BIT with PC destinstion ignores next instruction
-[^:]*:21: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:22: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:23: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:24: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:25: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:26: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:30: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:31: Warning: CPU12: CMP/BIT with PC destinstion ignores next instruction
-[^:]*:31: Warning: CPU11: PC is destinstion of SR altering instruction
-[^:]*:34: Warning: CPU12: CMP/BIT with PC destinstion ignores next instruction
-[^:]*:34: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:35: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:36: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:37: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:38: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:39: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:40: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:41: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:42: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:43: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:44: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:45: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:46: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:47: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:48: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:49: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:50: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:51: Warning: CPU13: SR is destinstion of SR altering instruction
-[^:]*:52: Warning: CPU13: SR is destinstion of SR altering instruction
+[^:]*:18: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:19: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:20: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:21: Warning: CPU12: CMP/BIT with PC destination ignores next instruction
+[^:]*:21: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:22: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:23: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:24: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:25: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:26: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:30: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:31: Warning: CPU12: CMP/BIT with PC destination ignores next instruction
+[^:]*:31: Warning: CPU11: PC is destination of SR altering instruction
+[^:]*:34: Warning: CPU12: CMP/BIT with PC destination ignores next instruction
+[^:]*:34: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:35: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:36: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:37: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:38: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:39: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:40: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:41: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:42: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:43: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:44: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:45: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:46: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:47: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:48: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:49: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:50: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:51: Warning: CPU13: SR is destination of SR altering instruction
+[^:]*:52: Warning: CPU13: SR is destination of SR altering instruction
 [^:]*:56: Warning: CPU19: Instruction setting CPUOFF must be followed by a NOP
 [^:]*:57: Warning: CPU19: Instruction setting CPUOFF must be followed by a NOP
-[^:]*:57: Warning: CPU13: SR is destinstion of SR altering instruction
+[^:]*:57: Warning: CPU13: SR is destination of SR altering instruction
diff --git a/gas/testsuite/gas/tic54x/opcodes.s b/gas/testsuite/gas/tic54x/opcodes.s
index 3e1e84b..99b358d 100644
--- a/gas/testsuite/gas/tic54x/opcodes.s
+++ b/gas/testsuite/gas/tic54x/opcodes.s
@@ -119,7 +119,7 @@ _opcodes:
 	ld	#7,arp		

 	ld	*ar2+,asm	

 	ldm	ar3,a		

-	ld	*ar2+,a || mac	*ar3+,b	; single-line parallell

+	ld	*ar2+,a || mac	*ar3+,b	; single-line parallel

 	ld	*ar4+,b	|| macr	*ar5+,a	; with optional DST_ specified

 	ld	*ar2+,a			; double-line parallel

 	|| mas	*ar3+