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authorAlan Modra <amodra@gmail.com>2017-02-14 20:30:27 +1030
committerAlan Modra <amodra@gmail.com>2017-02-14 21:12:07 +1030
commit606a935e3a9066ab11308b8c934c9bdec7f128d3 (patch)
tree971ec6f0d5cc56af6701c4d55890ac54f3de3883 /gas
parente278ae05839ccffa234e0bfb4286b9f9a9dfbd28 (diff)
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Fix powerpc testsuite source errors
PR 21118 work exposed these errors in the testsuite. * testsuite/gas/ppc/cell.s: Correct invalid registers. * testsuite/gas/ppc/vle-simple-1.s: Likewise. * testsuite/gas/ppc/vle-simple-2.s: Likewise.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog6
-rw-r--r--gas/testsuite/gas/ppc/cell.s32
-rw-r--r--gas/testsuite/gas/ppc/vle-simple-1.s4
-rw-r--r--gas/testsuite/gas/ppc/vle-simple-2.s8
4 files changed, 28 insertions, 22 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 27e5885..c3ae0a5 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2017-02-14 Alan Modra <amodra@gmail.com>
+
+ * testsuite/gas/ppc/cell.s: Correct invalid registers.
+ * testsuite/gas/ppc/vle-simple-1.s: Likewise.
+ * testsuite/gas/ppc/vle-simple-2.s: Likewise.
+
2017-02-13 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (parse_ifimm_zero): Make prefix optional in unified
diff --git a/gas/testsuite/gas/ppc/cell.s b/gas/testsuite/gas/ppc/cell.s
index b294299..dd6e15f 100644
--- a/gas/testsuite/gas/ppc/cell.s
+++ b/gas/testsuite/gas/ppc/cell.s
@@ -1,21 +1,21 @@
.text
- lvlx %r0, %r1, %r2
- lvlx %r0, 0, %r2
- lvlxl %r0, %r1, %r2
- lvlxl %r0, 0, %r2
- lvrx %r0, %r1, %r2
- lvrx %r0, 0, %r2
- lvrxl %r0, %r1, %r2
- lvrxl %r0, 0, %r2
+ lvlx %v0, %r1, %r2
+ lvlx %v0, 0, %r2
+ lvlxl %v0, %r1, %r2
+ lvlxl %v0, 0, %r2
+ lvrx %v0, %r1, %r2
+ lvrx %v0, 0, %r2
+ lvrxl %v0, %r1, %r2
+ lvrxl %v0, 0, %r2
- stvlx %r0, %r1, %r2
- stvlx %r0, 0, %r2
- stvlxl %r0, %r1, %r2
- stvlxl %r0, 0, %r2
- stvrx %r0, %r1, %r2
- stvrx %r0, 0, %r2
- stvrxl %r0, %r1, %r2
- stvrxl %r0, 0, %r2
+ stvlx %v0, %r1, %r2
+ stvlx %v0, 0, %r2
+ stvlxl %v0, %r1, %r2
+ stvlxl %v0, 0, %r2
+ stvrx %v0, %r1, %r2
+ stvrx %v0, 0, %r2
+ stvrxl %v0, %r1, %r2
+ stvrxl %v0, 0, %r2
ldbrx %r0, 0, %r1
ldbrx %r0, %r1, %r2
diff --git a/gas/testsuite/gas/ppc/vle-simple-1.s b/gas/testsuite/gas/ppc/vle-simple-1.s
index 074cc0f..713fb90 100644
--- a/gas/testsuite/gas/ppc/vle-simple-1.s
+++ b/gas/testsuite/gas/ppc/vle-simple-1.s
@@ -4,7 +4,7 @@ target0:
se_beq target3
target1:
- se_bf cr1, target4
+ se_bf gt, target4
target2:
se_bge target2
@@ -29,6 +29,6 @@ target8:
se_bso target8
target9:
- se_bt cr2, target6
+ se_bt eq, target6
se_bun target9
diff --git a/gas/testsuite/gas/ppc/vle-simple-2.s b/gas/testsuite/gas/ppc/vle-simple-2.s
index 8f95dc2..cad3ca5 100644
--- a/gas/testsuite/gas/ppc/vle-simple-2.s
+++ b/gas/testsuite/gas/ppc/vle-simple-2.s
@@ -13,10 +13,10 @@ target1:
target2:
e_beql cr0, target1
e_beql target6
- e_bf cr1, target3
+ e_bf 4*cr0+gt, target3
target3:
- e_bfl cr3, target0
+ e_bfl cr0*4+un, target0
e_bge cr1, target1
e_bge target5
@@ -69,8 +69,8 @@ target8:
target9:
e_bsol cr0, target8
e_bsol target8
- e_bt cr1, target7
- e_btl cr0, target5
+ e_bt gt+cr0*4, target7
+ e_btl lt+4*cr0, target5
e_bun cr1, target4
e_bun target4
e_bunl cr2, target0