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author | Sudi Das <sudi.das@arm.com> | 2019-01-25 14:28:07 +0000 |
---|---|---|
committer | Tamar Christina <tamar.christina@arm.com> | 2019-01-25 14:49:53 +0000 |
commit | 69105ce4c42e5644ab92cb9b2765ff5ce6bf7b1b (patch) | |
tree | 03e21bc1d88aa8a4cb469aa6d5ab4c7dc6ae3491 /gas | |
parent | 20a4ca5524b9bde2f5dfb19661570c25a3b05e5d (diff) | |
download | gdb-69105ce4c42e5644ab92cb9b2765ff5ce6bf7b1b.zip gdb-69105ce4c42e5644ab92cb9b2765ff5ce6bf7b1b.tar.gz gdb-69105ce4c42e5644ab92cb9b2765ff5ce6bf7b1b.tar.bz2 |
AArch64: Update encodings for stg, st2g, stzg and st2zg.
This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch updates the st*g instructions
to use a previously reserved field for a new register operand. Thus the
new versions of the instructions are as follows:
- STG Xt, [<Xn|SP>, #<simm>]
- STG Xt, [<Xn|SP>, #<simm>]!
- STG Xt, [<Xn|SP>], #<simm>
- STZG Xt, [<Xn|SP>, #<simm>]
- STZG Xt, [<Xn|SP>, #<simm>]!
- STZG Xt, [<Xn|SP>], #<simm>
- ST2G Xt, [<Xn|SP>, #<simm>]
- ST2G Xt, [<Xn|SP>, #<simm>]!
- ST2G Xt, [<Xn|SP>], #<simm>
- STZ2G Xt, [<Xn|SP>, #<simm>]
- STZ2G Xt, [<Xn|SP>, #<simm>]!
- STZ2G Xt, [<Xn|SP>], #<simm>
Committed on behalf of Sudakshina Das.
*** gas/ChangeLog ***
* config/tc-aarch64.c (warn_unpredictable_ldst): Exempt
stg, st2g, stzg and stz2g from Xt == Xn with writeback warning.
* testsuite/gas/aarch64/armv8_5-a-memtag.d: Change tests for
stg, stzg, st2g and stz2g.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** opcodes/ChangeLog ***
* aarch64-tbl.h (QL_LDST_AT): Update macro.
(aarch64_opcode): Change encoding for stg, stzg
st2g and st2zg.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Diffstat (limited to 'gas')
-rw-r--r-- | gas/config/tc-aarch64.c | 2 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/armv8_5-a-memtag.d | 104 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/armv8_5-a-memtag.s | 26 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/illegal-memtag.l | 18 | ||||
-rw-r--r-- | gas/testsuite/gas/aarch64/illegal-memtag.s | 21 |
5 files changed, 102 insertions, 69 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 537f00c..1acf6f6 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6772,6 +6772,8 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str) == AARCH64_OPND_CLASS_INT_REG) && opnds[0].reg.regno == opnds[1].addr.base_regno && opnds[1].addr.base_regno != REG_SP + /* Exempt STG/STZG/ST2G/STZ2G. */ + && !(opnds[1].type == AARCH64_OPND_ADDR_SIMM13) && opnds[1].addr.writeback) as_warn (_("unpredictable transfer with writeback -- `%s'"), str); break; diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d index 678fefc..53a95fb 100644 --- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d +++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d @@ -55,50 +55,66 @@ Disassembly of section \.text: .*: badb037f cmpp x27, x27 .*: bac003ff cmpp sp, x0 .*: badf001f cmpp x0, sp -.*: d920081f stg \[x0\] -.*: d9200b7f stg \[x27\] -.*: d93fb81f stg \[x0, #-80\] -.*: d9200c1f stg \[x0, #0\]! -.*: d920ac1f stg \[x0, #160\]! -.*: d920041f stg \[x0\], #0 -.*: d93a641f stg \[x0\], #-1440 -.*: d92ffbff stg \[sp, #4080\] -.*: d9300bff stg \[sp, #-4096\] -.*: d92fffff stg \[sp, #4080\]! -.*: d93007ff stg \[sp\], #-4096 -.*: d960081f stzg \[x0\] -.*: d9600b7f stzg \[x27\] -.*: d97fb81f stzg \[x0, #-80\] -.*: d9600c1f stzg \[x0, #0\]! -.*: d960ac1f stzg \[x0, #160\]! -.*: d960041f stzg \[x0\], #0 -.*: d97a641f stzg \[x0\], #-1440 -.*: d96ffbff stzg \[sp, #4080\] -.*: d9700bff stzg \[sp, #-4096\] -.*: d96fffff stzg \[sp, #4080\]! -.*: d97007ff stzg \[sp\], #-4096 -.*: d9a0081f st2g \[x0\] -.*: d9a00b7f st2g \[x27\] -.*: d9bfb81f st2g \[x0, #-80\] -.*: d9a00c1f st2g \[x0, #0\]! -.*: d9a0ac1f st2g \[x0, #160\]! -.*: d9a0041f st2g \[x0\], #0 -.*: d9ba641f st2g \[x0\], #-1440 -.*: d9affbff st2g \[sp, #4080\] -.*: d9b00bff st2g \[sp, #-4096\] -.*: d9afffff st2g \[sp, #4080\]! -.*: d9b007ff st2g \[sp\], #-4096 -.*: d9e0081f stz2g \[x0\] -.*: d9e00b7f stz2g \[x27\] -.*: d9ffb81f stz2g \[x0, #-80\] -.*: d9e00c1f stz2g \[x0, #0\]! -.*: d9e0ac1f stz2g \[x0, #160\]! -.*: d9e0041f stz2g \[x0\], #0 -.*: d9fa641f stz2g \[x0\], #-1440 -.*: d9effbff stz2g \[sp, #4080\] -.*: d9f00bff stz2g \[sp, #-4096\] -.*: d9efffff stz2g \[sp, #4080\]! -.*: d9f007ff stz2g \[sp\], #-4096 +.*: d9200800 stg x0, \[x0\] +.*: d9200b60 stg x0, \[x27\] +.*: d920081f stg xzr, \[x0\] +.*: d93fb81b stg x27, \[x0, #-80\] +.*: d9200c00 stg x0, \[x0, #0\]! +.*: d9200c1f stg xzr, \[x0, #0\]! +.*: d920ac1b stg x27, \[x0, #160\]! +.*: d9200400 stg x0, \[x0\], #0 +.*: d920041f stg xzr, \[x0\], #0 +.*: d93a641b stg x27, \[x0\], #-1440 +.*: d92ffbe0 stg x0, \[sp, #4080\] +.*: d92ffbff stg xzr, \[sp, #4080\] +.*: d9300bfb stg x27, \[sp, #-4096\] +.*: d92fffe0 stg x0, \[sp, #4080\]! +.*: d93007ff stg xzr, \[sp\], #-4096 +.*: d9600800 stzg x0, \[x0\] +.*: d9600b60 stzg x0, \[x27\] +.*: d960081f stzg xzr, \[x0\] +.*: d97fb81b stzg x27, \[x0, #-80\] +.*: d9600c00 stzg x0, \[x0, #0\]! +.*: d9600c1f stzg xzr, \[x0, #0\]! +.*: d960ac1b stzg x27, \[x0, #160\]! +.*: d9600400 stzg x0, \[x0\], #0 +.*: d960041f stzg xzr, \[x0\], #0 +.*: d97a641b stzg x27, \[x0\], #-1440 +.*: d96ffbe0 stzg x0, \[sp, #4080\] +.*: d96ffbff stzg xzr, \[sp, #4080\] +.*: d9700bfb stzg x27, \[sp, #-4096\] +.*: d96fffe0 stzg x0, \[sp, #4080\]! +.*: d97007ff stzg xzr, \[sp\], #-4096 +.*: d9a00800 st2g x0, \[x0\] +.*: d9a00b60 st2g x0, \[x27\] +.*: d9a0081f st2g xzr, \[x0\] +.*: d9bfb81b st2g x27, \[x0, #-80\] +.*: d9a00c00 st2g x0, \[x0, #0\]! +.*: d9a00c1f st2g xzr, \[x0, #0\]! +.*: d9a0ac1b st2g x27, \[x0, #160\]! +.*: d9a00400 st2g x0, \[x0\], #0 +.*: d9a0041f st2g xzr, \[x0\], #0 +.*: d9ba641b st2g x27, \[x0\], #-1440 +.*: d9affbe0 st2g x0, \[sp, #4080\] +.*: d9affbff st2g xzr, \[sp, #4080\] +.*: d9b00bfb st2g x27, \[sp, #-4096\] +.*: d9afffe0 st2g x0, \[sp, #4080\]! +.*: d9b007ff st2g xzr, \[sp\], #-4096 +.*: d9e00800 stz2g x0, \[x0\] +.*: d9e00b60 stz2g x0, \[x27\] +.*: d9e0081f stz2g xzr, \[x0\] +.*: d9ffb81b stz2g x27, \[x0, #-80\] +.*: d9e00c00 stz2g x0, \[x0, #0\]! +.*: d9e00c1f stz2g xzr, \[x0, #0\]! +.*: d9e0ac1b stz2g x27, \[x0, #160\]! +.*: d9e00400 stz2g x0, \[x0\], #0 +.*: d9e0041f stz2g xzr, \[x0\], #0 +.*: d9fa641b stz2g x27, \[x0\], #-1440 +.*: d9effbe0 stz2g x0, \[sp, #4080\] +.*: d9effbff stz2g xzr, \[sp, #4080\] +.*: d9f00bfb stz2g x27, \[sp, #-4096\] +.*: d9efffe0 stz2g x0, \[sp, #4080\]! +.*: d9f007ff stz2g xzr, \[sp\], #-4096 .*: 69000000 stgp x0, x0, \[x0\] .*: 69006c00 stgp x0, x27, \[x0\] .*: 6900001b stgp x27, x0, \[x0\] diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s index b8cab9f..2ca1a68 100644 --- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s +++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s @@ -17,17 +17,21 @@ func: .endm .macro expand_stg op - \op [x0, #0] - \op [x27, #0] - \op [x0, #-80] - \op [x0, #0]! - \op [x0, #160]! - \op [x0], #0 - \op [x0], #-1440 - \op [sp, #4080] - \op [sp, #-4096] - \op [sp, #4080]! - \op [sp], #-4096 + \op x0, [x0, #0] + \op x0, [x27, #0] + \op xzr, [x0, #0] + \op x27, [x0, #-80] + \op x0, [x0, #0]! + \op xzr, [x0, #0]! + \op x27, [x0, #160]! + \op x0, [x0], #0 + \op xzr, [x0], #0 + \op x27, [x0], #-1440 + \op x0, [sp, #4080] + \op xzr, [sp, #4080] + \op x27, [sp, #-4096] + \op x0, [sp, #4080]! + \op xzr, [sp], #-4096 .endm .macro expand_ldg_bulk op diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l index 2505ffe..aa79aac 100644 --- a/gas/testsuite/gas/aarch64/illegal-memtag.l +++ b/gas/testsuite/gas/aarch64/illegal-memtag.l @@ -4,9 +4,9 @@ [^:]*:[0-9]+: Error: immediate value out of range 0 to 1008 at operand 3 -- `subg x1,x2,-16,#0x3' [^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `addg x1,x2,#0x3f0,#0x10' [^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `subg x1,x2,#0x3f0,-4' -[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 1 -- `stg \[x1,#15\]' -[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 1 -- `stzg \[x1,#-4097]!' -[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 1 -- `st2g \[x1],#4096' +[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 2 -- `stg x2,\[x1,#15\]' +[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 2 -- `stzg x2,\[x1,#-4097\]!' +[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 2 -- `st2g x2,\[x1\],#4096' [^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 2 -- `ldg x1,\[x2,#33\]' [^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 2 -- `ldg x1,\[x2,#4112\]' [^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]' @@ -30,10 +30,14 @@ [^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subps x1,x2,xzr' [^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `cmpp xzr,x2' [^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `cmpp x2,xzr' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stg \[xzr,#0\]' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `st2g \[xzr,#0]!' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stzg \[xzr],#0' -[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stz2g \[xzr,#0\]' +[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stg x2,\[xzr,#0\]' +[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `st2g x2,\[xzr,#0\]!' +[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stzg x2,\[xzr\],#0' +[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `stz2g x2,\[xzr,#0\]' +[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stg sp,\[x2,#0\]' +[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `st2g sp,\[x2,#0\]!' +[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stzg sp,\[x2\],#0' +[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stz2g sp,\[x2,#0\]' [^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]' [^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]' [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]' diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.s b/gas/testsuite/gas/aarch64/illegal-memtag.s index 2a45e16..9c9c48b 100644 --- a/gas/testsuite/gas/aarch64/illegal-memtag.s +++ b/gas/testsuite/gas/aarch64/illegal-memtag.s @@ -9,9 +9,9 @@ func: subg x1, x2, #0x3f0, -4 # STG/STZG/ST2G/LDG : Fail imm - stg [x1, #15] - stzg [x1, #-4097]! - st2g [x1], #4096 + stg x2, [x1, #15] + stzg x2, [x1, #-4097]! + st2g x2, [x1], #4096 ldg x1, [x2, #33] ldg x1, [x2, #4112] @@ -41,10 +41,14 @@ func: subps x1, x2, xzr cmpp xzr, x2 cmpp x2, xzr - stg [xzr, #0] - st2g [xzr, #0]! - stzg [xzr], #0 - stz2g [xzr, #0] + stg x2, [xzr, #0] + st2g x2, [xzr, #0]! + stzg x2, [xzr], #0 + stz2g x2, [xzr, #0] + stg sp, [x2, #0] + st2g sp, [x2, #0]! + stzg sp, [x2], #0 + stz2g sp, [x2, #0] stgp sp, x2, [x3] stgp x1, sp, [x3] stgp x0, x0, [xzr] @@ -52,3 +56,6 @@ func: ldg x0, [xzr, #16] stzgm x0, [xzr] stzgm sp, [x3] + # Xt == Xn with writeback should not complain + st2g x2, [x2, #0]! + stzg x2, [x2], #0 |