[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions

This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)

This patch adds the prediction restriction instructions (that is, cfp,
dvp, cpp). These instructions are retrospectively made optional for
all versions of the architecture from ARMv8.0 to ARMv8.4 and is
mandatory from ARMv8.5. Hence adding a new +predres which can be used
by the older architectures.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
	(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
	(aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
	(aarch64_sys_regs_sr): Declare new table.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-dis.c (aarch64_ext_sysins_op): Add case for
	AARCH64_OPND_SYSREG_SR.
	* aarch64-opc.c (aarch64_print_operand): Likewise.
	(aarch64_sys_regs_sr): Define table.
	(aarch64_sys_ins_reg_supported_p): Check for RCTX with
	AARCH64_FEATURE_PREDRES.
	* aarch64-tbl.h (aarch64_feature_predres): New.
	(PREDRES, PREDRES_INSN): New.
	(aarch64_opcode_table): Add entries for cfp, dvp and cpp.
	(AARCH64_OPERANDS): Add new description for SYSREG_SR.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.
	(parse_operands): Add entry for AARCH64_OPND_SYSREG_SR.
	(md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh
	with aarch64_sys_regs_sr.
	(aarch64_features): Add new "predres" option for older
	architectures.
	* doc/c-aarch64.texi: Document the same.
	* testsuite/gas/aarch64/sysreg-4.s: New.
	* testsuite/gas/aarch64/sysreg-4.d: New.
	* testsuite/gas/aarch64/illegal-sysreg-4.d: New.
	* testsuite/gas/aarch64/illegal-sysreg-4.l: New.
	* testsuite/gas/aarch64/predres.s: New.
	* testsuite/gas/aarch64/predres.d: New.

9 files changed, 78 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9a83fad..6fa3e72 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,21 @@
 2018-10-09  Sudakshina Das  <sudi.das@arm.com>
 
+	* config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.
+	(parse_operands): Add entry for AARCH64_OPND_SYSREG_SR.
+	(md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh
+	with aarch64_sys_regs_sr.
+	(aarch64_features): Add new "predres" option for older
+	architectures.
+	* doc/c-aarch64.texi: Document the same.
+	* testsuite/gas/aarch64/sysreg-4.s: New.
+	* testsuite/gas/aarch64/sysreg-4.d: New.
+	* testsuite/gas/aarch64/illegal-sysreg-4.d: New.
+	* testsuite/gas/aarch64/illegal-sysreg-4.l: New.
+	* testsuite/gas/aarch64/predres.s: New.
+	* testsuite/gas/aarch64/predres.d: New.
+
+2018-10-09  Sudakshina Das  <sudi.das@arm.com>
+
 	* config/tc-aarch64.c (aarch64_features): Add new "sb" option
 	for older architectures.
 	* doc/c-aarch64.texi: Document the same.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 045ad52..8621a33 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -462,6 +462,7 @@ static struct hash_control *aarch64_sys_regs_ic_hsh;
 static struct hash_control *aarch64_sys_regs_dc_hsh;
 static struct hash_control *aarch64_sys_regs_at_hsh;
 static struct hash_control *aarch64_sys_regs_tlbi_hsh;
+static struct hash_control *aarch64_sys_regs_sr_hsh;
 static struct hash_control *aarch64_reg_hsh;
 static struct hash_control *aarch64_barrier_opt_hsh;
 static struct hash_control *aarch64_nzcv_hsh;
@@ -6422,14 +6423,22 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	  inst.base.operands[i].sysins_op =
 	    parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
 	  goto sys_reg_ins;
+
 	case AARCH64_OPND_SYSREG_DC:
 	  inst.base.operands[i].sysins_op =
 	    parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
 	  goto sys_reg_ins;
+
 	case AARCH64_OPND_SYSREG_AT:
 	  inst.base.operands[i].sysins_op =
 	    parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
 	  goto sys_reg_ins;
+
+	case AARCH64_OPND_SYSREG_SR:
+	  inst.base.operands[i].sysins_op =
+	    parse_sys_ins_reg (&str, aarch64_sys_regs_sr_hsh);
+	  goto sys_reg_ins;
+
 	case AARCH64_OPND_SYSREG_TLBI:
 	  inst.base.operands[i].sysins_op =
 	    parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
@@ -8439,6 +8448,7 @@ md_begin (void)
       || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
       || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
       || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
+      || (aarch64_sys_regs_sr_hsh = hash_new ()) == NULL
       || (aarch64_reg_hsh = hash_new ()) == NULL
       || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
       || (aarch64_nzcv_hsh = hash_new ()) == NULL
@@ -8477,6 +8487,11 @@ md_begin (void)
 			 aarch64_sys_regs_tlbi[i].name,
 			 (void *) (aarch64_sys_regs_tlbi + i));
 
+  for (i = 0; aarch64_sys_regs_sr[i].name != NULL; i++)
+    checked_hash_insert (aarch64_sys_regs_sr_hsh,
+			 aarch64_sys_regs_sr[i].name,
+			 (void *) (aarch64_sys_regs_sr + i));
+
   for (i = 0; i < ARRAY_SIZE (reg_names); i++)
     checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
 			 (void *) (reg_names + i));
@@ -8749,6 +8764,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_ARCH_NONE},
   {"sb",		AARCH64_FEATURE (AARCH64_FEATURE_SB, 0),
 			AARCH64_ARCH_NONE},
+  {"predres",		AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0),
+			AARCH64_ARCH_NONE},
   {"aes",		AARCH64_FEATURE (AARCH64_FEATURE_AES, 0),
 			AARCH64_ARCH_NONE},
   {"sm4",		AARCH64_FEATURE (AARCH64_FEATURE_SM4, 0),
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 8a116a4..dd5fbf4 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -183,6 +183,8 @@ automatically cause those extensions to be disabled.
  This implies @code{fp16}.
 @item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
  @tab Enable the speculation barrier instruction sb.
+@item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
+ @tab Enable the Execution and Data and Prediction instructions.
 @end multitable
 
 @node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-4.d b/gas/testsuite/gas/aarch64/illegal-sysreg-4.d
new file mode 100644
index 0000000..e181566
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-4.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sysreg-4.s
+#error_output: illegal-sysreg-4.l
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
new file mode 100644
index 0000000..68471a1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
@@ -0,0 +1,7 @@
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `cfp rctx,x1'
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `dvp rctx,x2'
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `cpp rctx,x3'
diff --git a/gas/testsuite/gas/aarch64/predres.d b/gas/testsuite/gas/aarch64/predres.d
new file mode 100644
index 0000000..e4f13a0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/predres.d
@@ -0,0 +1,11 @@
+#as: -march=armv8-a+predres
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d50b7381 	cfp	rctx, x1
+.*:	d50b73a2 	dvp	rctx, x2
+.*:	d50b73e3 	cpp	rctx, x3
diff --git a/gas/testsuite/gas/aarch64/predres.s b/gas/testsuite/gas/aarch64/predres.s
new file mode 100644
index 0000000..55ad909
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/predres.s
@@ -0,0 +1,5 @@
+/* File to test the +predres option.  */
+func:
+	cfp rctx, x1
+	dvp rctx, x2
+	cpp rctx, x3
diff --git a/gas/testsuite/gas/aarch64/sysreg-4.d b/gas/testsuite/gas/aarch64/sysreg-4.d
new file mode 100644
index 0000000..f3ea5d1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg-4.d
@@ -0,0 +1,12 @@
+#source: sysreg-4.s
+#as: -march=armv8.5-a
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d50b7381 	cfp	rctx, x1
+.*:	d50b73a2 	dvp	rctx, x2
+.*:	d50b73e3 	cpp	rctx, x3
diff --git a/gas/testsuite/gas/aarch64/sysreg-4.s b/gas/testsuite/gas/aarch64/sysreg-4.s
new file mode 100644
index 0000000..6ec069a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg-4.s
@@ -0,0 +1,5 @@
+/* sysreg-4.s Test file for ARMv8.5 system registers.  */
+func:
+	cfp rctx, x1
+	dvp rctx, x2
+	cpp rctx, x3