bfd/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* archures.c (bfd_architecture): Add bfd_arch_l1om.
	(bfd_l1om_arch): New.
	(bfd_archures_list): Add &bfd_l1om_arch.
	* bfd-in2.h: Regenerated.

	* config.bfd (targ64_selvecs): Add bfd_elf64_l1om_vec if
	bfd_elf64_x86_64_vec is supported.  Add bfd_elf64_l1om_freebsd_vec
	if bfd_elf64_x86_64_freebsd_vec is supported.
	(targ_selvecs): Likewise.

	* configure.in: Support bfd_elf64_l1om_vec and
	bfd_elf64_l1om_freebsd_vec.
	* configure: Regenerated.

	* cpu-l1om.c: New.

	* elf64-x86-64.c (elf64_l1om_elf_object_p): New.
	(bfd_elf64_l1om_vec): Likewise.
	(bfd_elf64_l1om_freebsd_vec): Likewise.

	* Makefile.am (ALL_MACHINES): Add cpu-l1om.lo.
	(ALL_MACHINES_CFILES): Add cpu-l1om.c.
	* Makefile.in: Regenerated.

	* targets.c (bfd_elf64_l1om_vec): New.
	(bfd_elf64_l1om_freebsd_vec): Likewise.
	(_bfd_target_vector): Add bfd_elf64_l1om_vec and
	bfd_elf64_l1om_freebsd_vec.

binutils/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* readelf.c (guess_is_rela): Handle EM_L1OM.
	(dump_relocations): Likewise.
	(get_machine_name): Likewise.
	(get_section_type_name): Likewise.
	(get_elf_section_flags): Likewise.
	(get_symbol_index_type): Likewise.
	(is_32bit_abs_reloc): Likewise.
	(is_32bit_pcrel_reloc): Likewise.
	(is_64bit_abs_reloc): Likewise.
	(is_64bit_pcrel_reloc): Likewise.
	(is_none_reloc): Likewise.

gas/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (cpu_arch): Add l1om.
	(check_cpu_arch_compatible): New.
	(set_cpu_arch): Use it.
	(i386_arch): New.
	(i386_mach): Return bfd_mach_l1om for Intel L1OM.
	(md_show_usage): Display l1om.
	(i386_target_format): Return ELF_TARGET_L1OM_FORMAT if
	cpu_arch_isa_flags.bitfield.cpul1om is set.

	* config/tc-i386.h (TARGET_ARCH): Use (i386_arch ()).
	(i386_arch): New.
	(ELF_TARGET_L1OM_FORMAT): Likewise.

	* doc/c-i386.texi: Document l1om.

gas/testsuite/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/l1om.d: New.
	* gas/i386/l1om-inval.l: Likewise.
	* gas/i386/l1om-inval.s: Likewise.

	* gas/i386/i386.exp: Run l1om-inval and l1om.

include/elf/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* common.h (EM_L1OM): New.

ld/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.tgt (targ64_extra_emuls): Add elf_l1om if elf_x86_64
	is supported.  Add elf_l1om_fbsd if elf_x86_64_fbsd is supported.
	(targ_extra_emuls): Likewise.

	* Makefile.am (ALL_64_EMULATIONS): Add eelf_l1om.o and
	eelf_l1om_fbsd.o
	(eelf_l1om.c): New.
	(eelf_l1om_fbsd.c): Likewise.
	* Makefile.in: Regenerated.

	* emulparams/elf_l1om.sh: New.
	* emulparams/elf_l1om_fbsd.sh: Likewise.

ld/testsuite/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* ld-x86-64/abs-l1om.d: New.
	* ld-x86-64/protected2-l1om.d: Likewise.
	* ld-x86-64/protected3-l1om.d: Likewise.

	* ld-x86-64/x86-64.exp: Run abs-l1om, protected2-l1om and
	protected3-l1om.

opcodes/

2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.in: Handle bfd_l1om_arch.
	* disassemble.c (disassembler): Likewise.

	* configure: Regenerated.

	* i386-dis.c (print_insn): Handle bfd_mach_l1om and
	bfd_mach_l1om_intel_syntax.  Use 8 bytes per line for Intel L1OM.

	* i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~CpuL1OM.
	Add CPU_L1OM_FLAGS.
	(cpu_flags): Add CpuL1OM.
	(set_bitfield): Take an argument to set the value field.
	(process_i386_cpu_flag): Support ~CpuXXX and ~(CpuXXX|CpuYYY).
	(process_i386_opcode_modifier): Updated.
	(process_i386_operand_type): Likewise.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

	* i386-opc.h (CpuL1OM): New.
	(CpuXsave): Updated.
	(i386_cpu_flags): Add cpul1om.

9 files changed, 367 insertions, 8 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index cbcf2cd..3aec588 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,20 @@
+2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (cpu_arch): Add l1om.
+	(check_cpu_arch_compatible): New.
+	(set_cpu_arch): Use it.
+	(i386_arch): New.
+	(i386_mach): Return bfd_mach_l1om for Intel L1OM.
+	(md_show_usage): Display l1om.
+	(i386_target_format): Return ELF_TARGET_L1OM_FORMAT if
+	cpu_arch_isa_flags.bitfield.cpul1om is set.
+
+	* config/tc-i386.h (TARGET_ARCH): Use (i386_arch ()).
+	(i386_arch): New.
+	(ELF_TARGET_L1OM_FORMAT): Likewise.
+
+	* doc/c-i386.texi: Document l1om.
+
 2009-07-24  Roland McGrath  <roland@redhat.com>
 	    Mark Wielaard  <mjw@redhat.com>
 
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 62486ec..c90cadc 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -577,6 +577,8 @@ static const arch_entry cpu_arch[] =
     CPU_CORE2_FLAGS },
   { "corei7", PROCESSOR_COREI7,
     CPU_COREI7_FLAGS },
+  { "l1om", PROCESSOR_GENERIC64,
+    CPU_L1OM_FLAGS },
   { "k6", PROCESSOR_K6,
     CPU_K6_FLAGS },
   { "k6_2", PROCESSOR_K6,
@@ -1956,6 +1958,35 @@ set_sse_check (int dummy ATTRIBUTE_UNUSED)
 }
 
 static void
+check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
+			   i386_cpu_flags new ATTRIBUTE_UNUSED)
+{
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+  static const char *arch;
+
+  /* Intel LIOM is only supported on ELF.  */
+  if (!IS_ELF)
+    return;
+
+  if (!arch)
+    {
+      /* Use cpu_arch_name if it is set in md_parse_option.  Otherwise
+	 use default_arch.  */
+      arch = cpu_arch_name;
+      if (!arch)
+	arch = default_arch;
+    }
+
+  /* If we are targeting Intel L1OM, wm must enable it.  */
+  if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
+      || new.bitfield.cpul1om)
+    return;
+  
+  as_bad (_("`%s' is not supported on `%s'"), name, arch);
+#endif
+}
+
+static void
 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
 {
   SKIP_WHITESPACE ();
@@ -1971,6 +2002,8 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
 	{
 	  if (strcmp (string, cpu_arch[i].name) == 0)
 	    {
+	      check_cpu_arch_compatible (string, cpu_arch[i].flags);
+
 	      if (*string != '.')
 		{
 		  cpu_arch_name = cpu_arch[i].name;
@@ -2049,11 +2082,34 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
   demand_empty_rest_of_line ();
 }
 
+enum bfd_architecture
+i386_arch (void)
+{
+  if (cpu_arch_isa_flags.bitfield.cpul1om)
+    {
+      if (OUTPUT_FLAVOR != bfd_target_elf_flavour
+	  || flag_code != CODE_64BIT)
+	as_fatal (_("Intel L1OM is 64bit ELF only"));
+      return bfd_arch_l1om;
+    }
+  else
+    return bfd_arch_i386;
+}
+
 unsigned long
 i386_mach ()
 {
   if (!strcmp (default_arch, "x86_64"))
-    return bfd_mach_x86_64;
+    {
+      if (cpu_arch_isa_flags.bitfield.cpul1om)
+	{
+	  if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+	    as_fatal (_("Intel L1OM is 64bit ELF only"));
+	  return bfd_mach_l1om;
+	}
+      else
+	return bfd_mach_x86_64;
+    }
   else if (!strcmp (default_arch, "i386"))
     return bfd_mach_i386_i386;
   else
@@ -7936,8 +7992,8 @@ md_show_usage (stream)
                           generate code for CPU and EXTENSION, CPU is one of:\n\
                            i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
                            pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
-                           core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
-                           generic32, generic64\n\
+                           core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
+                           amdfam10, generic32, generic64\n\
                           EXTENSION is combination of:\n\
                            8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
                            ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
@@ -7948,8 +8004,8 @@ md_show_usage (stream)
   -mtune=CPU              optimize for CPU, CPU is one of:\n\
                            i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
                            pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
-                           core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
-                           generic32, generic64\n"));
+                           core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
+                           amdfam10, generic32, generic64\n"));
   fprintf (stream, _("\
   -msse2avx               encode SSE instructions with VEX prefix\n"));
   fprintf (stream, _("\
@@ -8047,7 +8103,15 @@ i386_target_format (void)
 	    object_64bit = 1;
 	    use_rela_relocations = 1;
 	  }
-	return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
+	if (cpu_arch_isa_flags.bitfield.cpul1om)
+	  {
+	    if (flag_code != CODE_64BIT)
+	      as_fatal (_("Intel L1OM is 64bit only"));
+	    return ELF_TARGET_L1OM_FORMAT;
+	  }
+	else
+	  return (flag_code == CODE_64BIT
+		  ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
       }
 #endif
 #if defined (OBJ_MACH_O)
diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h
index 33275bd..1666563 100644
--- a/gas/config/tc-i386.h
+++ b/gas/config/tc-i386.h
@@ -29,8 +29,9 @@ struct fix;
 
 #define TARGET_BYTES_BIG_ENDIAN	0
 
-#define TARGET_ARCH		bfd_arch_i386
+#define TARGET_ARCH		(i386_arch ())
 #define TARGET_MACH		(i386_mach ())
+extern enum bfd_architecture i386_arch (void);
 extern unsigned long i386_mach (void);
 
 #ifdef TE_FreeBSD
@@ -70,6 +71,10 @@ extern unsigned long i386_mach (void);
 #define ELF_TARGET_FORMAT64	"elf64-x86-64"
 #endif
 
+#ifndef ELF_TARGET_L1OM_FORMAT
+#define ELF_TARGET_L1OM_FORMAT	"elf64-l1om"
+#endif
+
 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
      || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
      || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index dc276b8..c58a011 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -101,6 +101,7 @@ processor names are recognized:
 @code{core},
 @code{core2},
 @code{corei7},
+@code{l1om},
 @code{k6},
 @code{k6_2},
 @code{athlon},
@@ -885,7 +886,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
-@item @samp{corei7}
+@item @samp{corei7} @tab @samp{l1om}
 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
 @item @samp{amdfam10}
 @item @samp{generic32} @tab @samp{generic64}
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 636cf48..2769e04 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2009-07-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/l1om.d: New.
+	* gas/i386/l1om-inval.l: Likewise.
+	* gas/i386/l1om-inval.s: Likewise.
+
+	* gas/i386/i386.exp: Run l1om-inval and l1om.
+
 2009-07-24  Jan Beulich  <jbeulich@novell.com>
 
 	* gas/i386/8087.[ds]: New.
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index b0fda93..b1d71c1 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -189,6 +189,7 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
 	run_list_test "inval-equ-1" "-al"
 	run_list_test "inval-equ-2" "-al"
 	run_dump_test "ifunc"
+	run_list_test "l1om-inval" "-march=l1om --32"
     }
 
     # This is a PE specific test.
@@ -346,6 +347,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
 	run_list_test "reloc64" "--defsym _bad_=1"
 	run_dump_test "mixed-mode-reloc64"
 	run_dump_test "x86-64-ifunc"
+	run_dump_test "l1om"
     }
 
     set ASFLAGS "$old_ASFLAGS"
diff --git a/gas/testsuite/gas/i386/l1om-inval.l b/gas/testsuite/gas/i386/l1om-inval.l
new file mode 100644
index 0000000..6ec82cf
--- /dev/null
+++ b/gas/testsuite/gas/i386/l1om-inval.l
@@ -0,0 +1,2 @@
+Assembler messages:
+Fatal error: Intel L1OM is 64bit only
diff --git a/gas/testsuite/gas/i386/l1om-inval.s b/gas/testsuite/gas/i386/l1om-inval.s
new file mode 100644
index 0000000..1ff7c29
--- /dev/null
+++ b/gas/testsuite/gas/i386/l1om-inval.s
@@ -0,0 +1,2 @@
+	.text
+	nop
diff --git a/gas/testsuite/gas/i386/l1om.d b/gas/testsuite/gas/i386/l1om.d
new file mode 100644
index 0000000..6c000b7
--- /dev/null
+++ b/gas/testsuite/gas/i386/l1om.d
@@ -0,0 +1,258 @@
+#source: x86_64.s
+#as: -J -march=l1om
+#objdump: -dw --insn-width=7
+#name: l1om
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <.*>:
+[ 	]*[a-f0-9]+:	01 ca                	add    %ecx,%edx
+[ 	]*[a-f0-9]+:	44 01 ca             	add    %r9d,%edx
+[ 	]*[a-f0-9]+:	41 01 ca             	add    %ecx,%r10d
+[ 	]*[a-f0-9]+:	48 01 ca             	add    %rcx,%rdx
+[ 	]*[a-f0-9]+:	4d 01 ca             	add    %r9,%r10
+[ 	]*[a-f0-9]+:	41 01 c0             	add    %eax,%r8d
+[ 	]*[a-f0-9]+:	66 41 01 c0          	add    %ax,%r8w
+[ 	]*[a-f0-9]+:	49 01 c0             	add    %rax,%r8
+[ 	]*[a-f0-9]+:	05 11 22 33 44       	add    \$0x44332211,%eax
+[ 	]*[a-f0-9]+:	48 05 11 22 33 f4    	add    \$0xfffffffff4332211,%rax
+[ 	]*[a-f0-9]+:	66 05 33 44          	add    \$0x4433,%ax
+[ 	]*[a-f0-9]+:	48 05 11 22 33 44    	add    \$0x44332211,%rax
+[ 	]*[a-f0-9]+:	00 ca                	add    %cl,%dl
+[ 	]*[a-f0-9]+:	00 f7                	add    %dh,%bh
+[ 	]*[a-f0-9]+:	40 00 f7             	add    %sil,%dil
+[ 	]*[a-f0-9]+:	41 00 f7             	add    %sil,%r15b
+[ 	]*[a-f0-9]+:	44 00 f7             	add    %r14b,%dil
+[ 	]*[a-f0-9]+:	45 00 f7             	add    %r14b,%r15b
+[ 	]*[a-f0-9]+:	50                   	push   %rax
+[ 	]*[a-f0-9]+:	41 50                	push   %r8
+[ 	]*[a-f0-9]+:	41 59                	pop    %r9
+[ 	]*[a-f0-9]+:	04 11                	add    \$0x11,%al
+[ 	]*[a-f0-9]+:	80 c4 11             	add    \$0x11,%ah
+[ 	]*[a-f0-9]+:	40 80 c4 11          	add    \$0x11,%spl
+[ 	]*[a-f0-9]+:	41 80 c0 11          	add    \$0x11,%r8b
+[ 	]*[a-f0-9]+:	41 80 c4 11          	add    \$0x11,%r12b
+[ 	]*[a-f0-9]+:	0f 20 c0             	mov    %cr0,%rax
+[ 	]*[a-f0-9]+:	41 0f 20 c0          	mov    %cr0,%r8
+[ 	]*[a-f0-9]+:	44 0f 20 c0          	mov    %cr8,%rax
+[ 	]*[a-f0-9]+:	44 0f 22 c0          	mov    %rax,%cr8
+[ 	]*[a-f0-9]+:	f3 48 a5             	rep movsq %ds:\(%rsi\),%es:\(%rdi\)
+[ 	]*[a-f0-9]+:	66 f3 a5             	rep movsw %ds:\(%rsi\),%es:\(%rdi\)
+[ 	]*[a-f0-9]+:	f3 48 a5             	rep movsq %ds:\(%rsi\),%es:\(%rdi\)
+[ 	]*[a-f0-9]+:	b0 11                	mov    \$0x11,%al
+[ 	]*[a-f0-9]+:	b4 11                	mov    \$0x11,%ah
+[ 	]*[a-f0-9]+:	40 b4 11             	mov    \$0x11,%spl
+[ 	]*[a-f0-9]+:	41 b4 11             	mov    \$0x11,%r12b
+[ 	]*[a-f0-9]+:	b8 44 33 22 11       	mov    \$0x11223344,%eax
+[ 	]*[a-f0-9]+:	41 b8 44 33 22 11    	mov    \$0x11223344,%r8d
+[ 	]*[a-f0-9]+:	48 b8 88 77 66 55 44 33 22 11 	mov    \$0x1122334455667788,%rax
+[ 	]*[a-f0-9]+:	49 b8 88 77 66 55 44 33 22 11 	mov    \$0x1122334455667788,%r8
+[ 	]*[a-f0-9]+:	03 00                	add    \(%rax\),%eax
+[ 	]*[a-f0-9]+:	41 03 00             	add    \(%r8\),%eax
+[ 	]*[a-f0-9]+:	45 03 00             	add    \(%r8\),%r8d
+[ 	]*[a-f0-9]+:	49 03 00             	add    \(%r8\),%rax
+[ 	]*[a-f0-9]+:	03 05 22 22 22 22    	add    0x22222222\(%rip\),%eax        # 222222c7 <foo\+0x222220c4>
+[ 	]*[a-f0-9]+:	03 45 00             	add    0x0\(%rbp\),%eax
+[ 	]*[a-f0-9]+:	03 04 25 22 22 22 22 	add    0x22222222,%eax
+[ 	]*[a-f0-9]+:	41 03 45 00          	add    0x0\(%r13\),%eax
+[ 	]*[a-f0-9]+:	03 04 80             	add    \(%rax,%rax,4\),%eax
+[ 	]*[a-f0-9]+:	41 03 04 80          	add    \(%r8,%rax,4\),%eax
+[ 	]*[a-f0-9]+:	45 03 04 80          	add    \(%r8,%rax,4\),%r8d
+[ 	]*[a-f0-9]+:	43 03 04 80          	add    \(%r8,%r8,4\),%eax
+[ 	]*[a-f0-9]+:	46 01 04 81          	add    %r8d,\(%rcx,%r8,4\)
+[ 	]*[a-f0-9]+:	03 14 c0             	add    \(%rax,%rax,8\),%edx
+[ 	]*[a-f0-9]+:	03 14 c8             	add    \(%rax,%rcx,8\),%edx
+[ 	]*[a-f0-9]+:	03 14 d0             	add    \(%rax,%rdx,8\),%edx
+[ 	]*[a-f0-9]+:	03 14 d8             	add    \(%rax,%rbx,8\),%edx
+[ 	]*[a-f0-9]+:	03 10                	add    \(%rax\),%edx
+[ 	]*[a-f0-9]+:	03 14 e8             	add    \(%rax,%rbp,8\),%edx
+[ 	]*[a-f0-9]+:	03 14 f0             	add    \(%rax,%rsi,8\),%edx
+[ 	]*[a-f0-9]+:	03 14 f8             	add    \(%rax,%rdi,8\),%edx
+[ 	]*[a-f0-9]+:	42 03 14 c0          	add    \(%rax,%r8,8\),%edx
+[ 	]*[a-f0-9]+:	42 03 14 c8          	add    \(%rax,%r9,8\),%edx
+[ 	]*[a-f0-9]+:	42 03 14 d0          	add    \(%rax,%r10,8\),%edx
+[ 	]*[a-f0-9]+:	42 03 14 d8          	add    \(%rax,%r11,8\),%edx
+[ 	]*[a-f0-9]+:	42 03 14 e0          	add    \(%rax,%r12,8\),%edx
+[ 	]*[a-f0-9]+:	42 03 14 e8          	add    \(%rax,%r13,8\),%edx
+[ 	]*[a-f0-9]+:	42 03 14 f0          	add    \(%rax,%r14,8\),%edx
+[ 	]*[a-f0-9]+:	42 03 14 f8          	add    \(%rax,%r15,8\),%edx
+[ 	]*[a-f0-9]+:	83 c1 11             	add    \$0x11,%ecx
+[ 	]*[a-f0-9]+:	83 00 11             	addl   \$0x11,\(%rax\)
+[ 	]*[a-f0-9]+:	48 83 00 11          	addq   \$0x11,\(%rax\)
+[ 	]*[a-f0-9]+:	41 83 00 11          	addl   \$0x11,\(%r8\)
+[ 	]*[a-f0-9]+:	83 04 81 11          	addl   \$0x11,\(%rcx,%rax,4\)
+[ 	]*[a-f0-9]+:	41 83 04 81 11       	addl   \$0x11,\(%r9,%rax,4\)
+[ 	]*[a-f0-9]+:	42 83 04 81 11       	addl   \$0x11,\(%rcx,%r8,4\)
+[ 	]*[a-f0-9]+:	83 05 22 22 22 22 33 	addl   \$0x33,0x22222222\(%rip\)        # 22222342 <foo\+0x2222213f>
+[ 	]*[a-f0-9]+:	48 83 05 22 22 22 22 33 	addq   \$0x33,0x22222222\(%rip\)        # 2222234a <foo\+0x22222147>
+[ 	]*[a-f0-9]+:	81 05 22 22 22 22 33 33 33 33 	addl   \$0x33333333,0x22222222\(%rip\)        # 22222354 <foo\+0x22222151>
+[ 	]*[a-f0-9]+:	48 81 05 22 22 22 22 33 33 33 33 	addq   \$0x33333333,0x22222222\(%rip\)        # 2222235f <foo\+0x2222215c>
+[ 	]*[a-f0-9]+:	83 04 c5 22 22 22 22 33 	addl   \$0x33,0x22222222\(,%rax,8\)
+[ 	]*[a-f0-9]+:	83 80 22 22 22 22 33 	addl   \$0x33,0x22222222\(%rax\)
+[ 	]*[a-f0-9]+:	83 80 22 22 22 22 33 	addl   \$0x33,0x22222222\(%rax\)
+[ 	]*[a-f0-9]+:	41 83 04 e8 33       	addl   \$0x33,\(%r8,%rbp,8\)
+[ 	]*[a-f0-9]+:	83 04 25 22 22 22 22 33 	addl   \$0x33,0x22222222
+[ 	]*[a-f0-9]+:	a0 11 22 33 44 55 66 77 88 	mov    0x8877665544332211,%al
+[ 	]*[a-f0-9]+:	a1 11 22 33 44 55 66 77 88 	mov    0x8877665544332211,%eax
+[ 	]*[a-f0-9]+:	a2 11 22 33 44 55 66 77 88 	mov    %al,0x8877665544332211
+[ 	]*[a-f0-9]+:	a3 11 22 33 44 55 66 77 88 	mov    %eax,0x8877665544332211
+[ 	]*[a-f0-9]+:	48 a1 11 22 33 44 55 66 77 88 	mov    0x8877665544332211,%rax
+[ 	]*[a-f0-9]+:	48 a3 11 22 33 44 55 66 77 88 	mov    %rax,0x8877665544332211
+[ 	]*[a-f0-9]+:	48 99                	cqto   
+[ 	]*[a-f0-9]+:	48 98                	cltq   
+[ 	]*[a-f0-9]+:	48 63 c0             	movslq %eax,%rax
+[ 	]*[a-f0-9]+:	48 0f bf c0          	movswq %ax,%rax
+[ 	]*[a-f0-9]+:	48 0f be c0          	movsbq %al,%rax
+
+0+1a7 <bar>:
+[ 	]*[a-f0-9]+:	b0 00                	mov    \$0x0,%al
+[ 	]*[a-f0-9]+:	66 b8 00 00          	mov    \$0x0,%ax
+[ 	]*[a-f0-9]+:	b8 00 00 00 00       	mov    \$0x0,%eax
+[ 	]*[a-f0-9]+:	48 c7 c0 00 00 00 00 	mov    \$0x0,%rax
+[ 	]*[a-f0-9]+:	a1 00 00 00 00 00 00 00 00 	mov    0x0,%eax
+[ 	]*[a-f0-9]+:	8b 04 25 00 00 00 00 	mov    0x0,%eax
+[ 	]*[a-f0-9]+:	8b 80 00 00 00 00    	mov    0x0\(%rax\),%eax
+[ 	]*[a-f0-9]+:	8b 05 00 00 00 00    	mov    0x0\(%rip\),%eax        # 1d5 <bar\+0x2e>
+[ 	]*[a-f0-9]+:	b0 00                	mov    \$0x0,%al
+[ 	]*[a-f0-9]+:	66 b8 00 00          	mov    \$0x0,%ax
+[ 	]*[a-f0-9]+:	b8 00 00 00 00       	mov    \$0x0,%eax
+[ 	]*[a-f0-9]+:	48 c7 c0 00 00 00 00 	mov    \$0x0,%rax
+[ 	]*[a-f0-9]+:	a1 00 00 00 00 00 00 00 00 	mov    0x0,%eax
+[ 	]*[a-f0-9]+:	8b 04 25 00 00 00 00 	mov    0x0,%eax
+[ 	]*[a-f0-9]+:	8b 80 00 00 00 00    	mov    0x0\(%rax\),%eax
+[ 	]*[a-f0-9]+:	8b 05 00 00 00 00    	mov    0x0\(%rip\),%eax        # 203 <foo>
+
+0+203 <foo>:
+[ 	]*[a-f0-9]+:	a0 11 22 33 44 55 66 77 88 	mov    0x8877665544332211,%al
+[ 	]*[a-f0-9]+:	66 a1 11 22 33 44 55 66 77 88 	mov    0x8877665544332211,%ax
+[ 	]*[a-f0-9]+:	a1 11 22 33 44 55 66 77 88 	mov    0x8877665544332211,%eax
+[ 	]*[a-f0-9]+:	48 a1 11 22 33 44 55 66 77 88 	mov    0x8877665544332211,%rax
+[ 	]*[a-f0-9]+:	a2 11 22 33 44 55 66 77 88 	mov    %al,0x8877665544332211
+[ 	]*[a-f0-9]+:	66 a3 11 22 33 44 55 66 77 88 	mov    %ax,0x8877665544332211
+[ 	]*[a-f0-9]+:	a3 11 22 33 44 55 66 77 88 	mov    %eax,0x8877665544332211
+[ 	]*[a-f0-9]+:	48 a3 11 22 33 44 55 66 77 88 	mov    %rax,0x8877665544332211
+[ 	]*[a-f0-9]+:	a0 11 22 33 44 55 66 77 88 	mov    0x8877665544332211,%al
+[ 	]*[a-f0-9]+:	66 a1 11 22 33 44 55 66 77 88 	mov    0x8877665544332211,%ax
+[ 	]*[a-f0-9]+:	a1 11 22 33 44 55 66 77 88 	mov    0x8877665544332211,%eax
+[ 	]*[a-f0-9]+:	48 a1 11 22 33 44 55 66 77 88 	mov    0x8877665544332211,%rax
+[ 	]*[a-f0-9]+:	a2 11 22 33 44 55 66 77 88 	mov    %al,0x8877665544332211
+[ 	]*[a-f0-9]+:	66 a3 11 22 33 44 55 66 77 88 	mov    %ax,0x8877665544332211
+[ 	]*[a-f0-9]+:	a3 11 22 33 44 55 66 77 88 	mov    %eax,0x8877665544332211
+[ 	]*[a-f0-9]+:	48 a3 11 22 33 44 55 66 77 88 	mov    %rax,0x8877665544332211
+[ 	]*[a-f0-9]+:	8a 04 25 11 22 33 ff 	mov    0xffffffffff332211,%al
+[ 	]*[a-f0-9]+:	66 8b 04 25 11 22 33 ff 	mov    0xffffffffff332211,%ax
+[ 	]*[a-f0-9]+:	8b 04 25 11 22 33 ff 	mov    0xffffffffff332211,%eax
+[ 	]*[a-f0-9]+:	48 8b 04 25 11 22 33 ff 	mov    0xffffffffff332211,%rax
+[ 	]*[a-f0-9]+:	88 04 25 11 22 33 ff 	mov    %al,0xffffffffff332211
+[ 	]*[a-f0-9]+:	66 89 04 25 11 22 33 ff 	mov    %ax,0xffffffffff332211
+[ 	]*[a-f0-9]+:	89 04 25 11 22 33 ff 	mov    %eax,0xffffffffff332211
+[ 	]*[a-f0-9]+:	48 89 04 25 11 22 33 ff 	mov    %rax,0xffffffffff332211
+[ 	]*[a-f0-9]+:	8a 04 25 11 22 33 ff 	mov    0xffffffffff332211,%al
+[ 	]*[a-f0-9]+:	66 8b 04 25 11 22 33 ff 	mov    0xffffffffff332211,%ax
+[ 	]*[a-f0-9]+:	8b 04 25 11 22 33 ff 	mov    0xffffffffff332211,%eax
+[ 	]*[a-f0-9]+:	48 8b 04 25 11 22 33 ff 	mov    0xffffffffff332211,%rax
+[ 	]*[a-f0-9]+:	88 04 25 11 22 33 ff 	mov    %al,0xffffffffff332211
+[ 	]*[a-f0-9]+:	66 89 04 25 11 22 33 ff 	mov    %ax,0xffffffffff332211
+[ 	]*[a-f0-9]+:	89 04 25 11 22 33 ff 	mov    %eax,0xffffffffff332211
+[ 	]*[a-f0-9]+:	48 89 04 25 11 22 33 ff 	mov    %rax,0xffffffffff332211
+[ 	]*[a-f0-9]+:	48 0f c7 08          	cmpxchg16b \(%rax\)
+[ 	]*[a-f0-9]+:	48 0f c7 08          	cmpxchg16b \(%rax\)
+[ 	]*[a-f0-9]+:	66 0f be f0          	movsbw %al,%si
+[ 	]*[a-f0-9]+:	0f be f0             	movsbl %al,%esi
+[ 	]*[a-f0-9]+:	48 0f be f0          	movsbq %al,%rsi
+[ 	]*[a-f0-9]+:	0f bf f0             	movswl %ax,%esi
+[ 	]*[a-f0-9]+:	48 0f bf f0          	movswq %ax,%rsi
+[ 	]*[a-f0-9]+:	48 63 f0             	movslq %eax,%rsi
+[ 	]*[a-f0-9]+:	0f be 10             	movsbl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f be 10          	movsbq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	66 0f be 10          	movsbw \(%rax\),%dx
+[ 	]*[a-f0-9]+:	0f be 10             	movsbl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f be 10          	movsbq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	66 0f be 10          	movsbw \(%rax\),%dx
+[ 	]*[a-f0-9]+:	0f bf 10             	movswl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f bf 10          	movswq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	66 0f b6 f0          	movzbw %al,%si
+[ 	]*[a-f0-9]+:	0f b6 f0             	movzbl %al,%esi
+[ 	]*[a-f0-9]+:	48 0f b6 f0          	movzbq %al,%rsi
+[ 	]*[a-f0-9]+:	0f b7 f0             	movzwl %ax,%esi
+[ 	]*[a-f0-9]+:	48 0f b7 f0          	movzwq %ax,%rsi
+[ 	]*[a-f0-9]+:	0f b6 10             	movzbl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f b6 10          	movzbq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	66 0f b6 10          	movzbw \(%rax\),%dx
+[ 	]*[a-f0-9]+:	0f b6 10             	movzbl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f b6 10          	movzbq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	66 0f b6 10          	movzbw \(%rax\),%dx
+[ 	]*[a-f0-9]+:	0f b6 10             	movzbl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f b6 10          	movzbq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	66 0f b6 10          	movzbw \(%rax\),%dx
+[ 	]*[a-f0-9]+:	0f b7 10             	movzwl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f b7 10          	movzwq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	66 0f be f0          	movsbw %al,%si
+[ 	]*[a-f0-9]+:	0f be f0             	movsbl %al,%esi
+[ 	]*[a-f0-9]+:	48 0f be f0          	movsbq %al,%rsi
+[ 	]*[a-f0-9]+:	0f bf f0             	movswl %ax,%esi
+[ 	]*[a-f0-9]+:	48 0f bf f0          	movswq %ax,%rsi
+[ 	]*[a-f0-9]+:	48 63 f0             	movslq %eax,%rsi
+[ 	]*[a-f0-9]+:	0f be 10             	movsbl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f be 10          	movsbq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	66 0f be 10          	movsbw \(%rax\),%dx
+[ 	]*[a-f0-9]+:	0f bf 10             	movswl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f bf 10          	movswq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	66 0f b6 f0          	movzbw %al,%si
+[ 	]*[a-f0-9]+:	0f b6 f0             	movzbl %al,%esi
+[ 	]*[a-f0-9]+:	48 0f b6 f0          	movzbq %al,%rsi
+[ 	]*[a-f0-9]+:	0f b7 f0             	movzwl %ax,%esi
+[ 	]*[a-f0-9]+:	48 0f b7 f0          	movzwq %ax,%rsi
+[ 	]*[a-f0-9]+:	0f b6 10             	movzbl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f b6 10          	movzbq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	66 0f b6 10          	movzbw \(%rax\),%dx
+[ 	]*[a-f0-9]+:	0f b7 10             	movzwl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f b7 10          	movzwq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	f3 0f 7e 0c 24       	movq   \(%rsp\),%xmm1
+[ 	]*[a-f0-9]+:	f3 0f 7e 0c 24       	movq   \(%rsp\),%xmm1
+[ 	]*[a-f0-9]+:	66 0f d6 0c 24       	movq   %xmm1,\(%rsp\)
+[ 	]*[a-f0-9]+:	66 0f d6 0c 24       	movq   %xmm1,\(%rsp\)
+[ 	]*[a-f0-9]+:	df e0                	fnstsw %ax
+[ 	]*[a-f0-9]+:	df e0                	fnstsw %ax
+[ 	]*[a-f0-9]+:	9b df e0             	fstsw  %ax
+[ 	]*[a-f0-9]+:	9b df e0             	fstsw  %ax
+[ 	]*[a-f0-9]+:	df e0                	fnstsw %ax
+[ 	]*[a-f0-9]+:	df e0                	fnstsw %ax
+[ 	]*[a-f0-9]+:	9b df e0             	fstsw  %ax
+[ 	]*[a-f0-9]+:	9b df e0             	fstsw  %ax
+[ 	]*[a-f0-9]+:	66 0f be 00          	movsbw \(%rax\),%ax
+[ 	]*[a-f0-9]+:	0f be 00             	movsbl \(%rax\),%eax
+[ 	]*[a-f0-9]+:	48 0f be 00          	movsbq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	66 0f be 10          	movsbw \(%rax\),%dx
+[ 	]*[a-f0-9]+:	0f be 10             	movsbl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f be 10          	movsbq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	0f bf 10             	movswl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f bf 10          	movswq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	48 63 10             	movslq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	48 63 00             	movslq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	66 0f b6 00          	movzbw \(%rax\),%ax
+[ 	]*[a-f0-9]+:	0f b6 00             	movzbl \(%rax\),%eax
+[ 	]*[a-f0-9]+:	48 0f b6 00          	movzbq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	66 0f b6 10          	movzbw \(%rax\),%dx
+[ 	]*[a-f0-9]+:	0f b6 10             	movzbl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f b6 10          	movzbq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	0f b7 10             	movzwl \(%rax\),%edx
+[ 	]*[a-f0-9]+:	48 0f b7 10          	movzwq \(%rax\),%rdx
+[ 	]*[a-f0-9]+:	0f c3 00             	movnti %eax,\(%rax\)
+[ 	]*[a-f0-9]+:	0f c3 00             	movnti %eax,\(%rax\)
+[ 	]*[a-f0-9]+:	48 0f c3 00          	movnti %rax,\(%rax\)
+[ 	]*[a-f0-9]+:	48 0f c3 00          	movnti %rax,\(%rax\)
+[ 	]*[a-f0-9]+:	66 0f be 00          	movsbw \(%rax\),%ax
+[ 	]*[a-f0-9]+:	0f be 00             	movsbl \(%rax\),%eax
+[ 	]*[a-f0-9]+:	0f bf 00             	movswl \(%rax\),%eax
+[ 	]*[a-f0-9]+:	48 0f bf 00          	movswq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	48 63 00             	movslq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	48 63 00             	movslq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	66 0f b6 00          	movzbw \(%rax\),%ax
+[ 	]*[a-f0-9]+:	0f b6 00             	movzbl \(%rax\),%eax
+[ 	]*[a-f0-9]+:	0f b7 00             	movzwl \(%rax\),%eax
+[ 	]*[a-f0-9]+:	48 0f b7 00          	movzwq \(%rax\),%rax
+[ 	]*[a-f0-9]+:	0f c3 00             	movnti %eax,\(%rax\)
+[ 	]*[a-f0-9]+:	48 0f c3 00          	movnti %rax,\(%rax\)
+#pass