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| author | Sudakshina Das <sudi.das@arm.com> | 2018-09-26 10:54:07 +0100 |
|---|---|---|
| committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2018-10-09 15:39:29 +0100 |
| commit | 3fd229a447cd28a70bfd921f617bc6c3553b8fdd (patch) | |
| tree | 2cd068813b2afc460cb15b8cc774eaa187374939 /gas | |
| parent | 2ac435d46608be7ef90f80aaf9ff48443aea571e (diff) | |
| download | gdb-3fd229a447cd28a70bfd921f617bc6c3553b8fdd.zip gdb-3fd229a447cd28a70bfd921f617bc6c3553b8fdd.tar.gz gdb-3fd229a447cd28a70bfd921f617bc6c3553b8fdd.tar.bz2 | |
[PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys)
This patch adds the DC CVADP instruction. Since this has a separate
identification mechanism a new feature bit is added.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_CVADP): New.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
(aarch64_sys_ins_reg_supported_p): New check for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test instruction.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/illegal-sysreg-4.l | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-4.d | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/sysreg-4.s | 1 |
4 files changed, 9 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 6fa3e72..f958277 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,11 @@ 2018-10-09 Sudakshina Das <sudi.das@arm.com> + * testsuite/gas/aarch64/sysreg-4.s: Test instruction. + * testsuite/gas/aarch64/sysreg-4.d: Likewise. + * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise. + +2018-10-09 Sudakshina Das <sudi.das@arm.com> + * config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New. (parse_operands): Add entry for AARCH64_OPND_SYSREG_SR. (md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l index 68471a1..f3167e3 100644 --- a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l @@ -5,3 +5,4 @@ [^:]*:[0-9]+: Error: selected processor does not support `dvp rctx,x2' [^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx' [^:]*:[0-9]+: Error: selected processor does not support `cpp rctx,x3' +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cvadp' diff --git a/gas/testsuite/gas/aarch64/sysreg-4.d b/gas/testsuite/gas/aarch64/sysreg-4.d index f3ea5d1..1c14016 100644 --- a/gas/testsuite/gas/aarch64/sysreg-4.d +++ b/gas/testsuite/gas/aarch64/sysreg-4.d @@ -10,3 +10,4 @@ Disassembly of section \.text: .*: d50b7381 cfp rctx, x1 .*: d50b73a2 dvp rctx, x2 .*: d50b73e3 cpp rctx, x3 +.*: d50b7d24 dc cvadp, x4 diff --git a/gas/testsuite/gas/aarch64/sysreg-4.s b/gas/testsuite/gas/aarch64/sysreg-4.s index 6ec069a..49907c0 100644 --- a/gas/testsuite/gas/aarch64/sysreg-4.s +++ b/gas/testsuite/gas/aarch64/sysreg-4.s @@ -3,3 +3,4 @@ func: cfp rctx, x1 dvp rctx, x2 cpp rctx, x3 + dc cvadp, x4 |