Add support for m32r-linux target, including a RELA ABI and PIC.

18 files changed, 341 insertions, 36 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index c4cfa68..bfb7343 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,18 @@
+2003-12-19  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+        Add m32r-linux and PIC support.  Add new ABI that uses RELA.
+        * configure.in: Add m32r-linux targets.
+	* configure: Regenerate.
+        * config/tc-m32r.c (md_parse_option): Add -KPIC option.
+        (tc_gen_reloc): Added.
+        (debug_sym, md_estimate_size_before_relax, md_convert_frag,
+        md_pcrel_from_section, m32r_fix_adjustable): Changed for PIC.
+        * config/tc-m32r.h (tc_gen_reloc, EXTERN_FORCE_RELOC): Undefined.
+        (TC_HANDLES_FX_DONE, TC_FIX_ADJUSTABLE, TC_RELOC_RTSYM_LOC_FIXUP):
+	Defined.
+	* doc/c-m32r.texi: Document -KPIC option.
+	* NEWS: Mention the support m32r Linux and PIC.
+
 2003-12-18  Nick Clifton  <nickc@redhat.com>
 
 	* input-file.c (input_file_open): Remove call to stat().
diff --git a/gas/NEWS b/gas/NEWS
index 66c15c9..cff6862 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Added PIC m32r Linux (ELF) and support to M32R assembler.
+
 * Added support for ARM V6.
 
 * Added support for sh4a and variants.
diff --git a/gas/config/tc-m32r.c b/gas/config/tc-m32r.c
index 90fb28d..fb1c613 100644
--- a/gas/config/tc-m32r.c
+++ b/gas/config/tc-m32r.c
@@ -70,6 +70,9 @@ static m32r_insn prev_insn;
    alignment request.  */
 static int seen_relaxable_p = 0;
 
+/* Non-zero if we are generating PIC code.  */
+int pic_code;
+
 /* Non-zero if -relax specified, in which case sufficient relocs are output
    for the linker to do relaxing.
    We do simple forms of relaxing internally, but they are always done.
@@ -194,7 +197,7 @@ allow_m32rx (int on)
     gas_cgen_cpu_desc->machs = mach_table[on].mach_flags;
 }
 
-#define M32R_SHORTOPTS "O"
+#define M32R_SHORTOPTS "O::K:"
 
 const char *md_shortopts = M32R_SHORTOPTS;
 
@@ -362,6 +365,13 @@ md_parse_option (c, arg)
       warn_unmatched_high = 0;
       break;
 
+    case 'K':
+      if (strcmp (arg, "PIC") != 0)
+        as_warn (_("Unrecognized option following -K"));
+      else
+        pic_code = 1;
+      break;
+
 #if 0
     /* Not supported yet.  */
     case OPTION_RELAX:
@@ -436,6 +446,9 @@ md_show_usage (stream)
   fprintf (stream, _("\
   -Wnuh                   synonym for -no-warn-unmatched-high\n"));
 
+  fprintf (stream, _("\
+  -KPIC                   generate PIC\n"));
+
 #if 0
   fprintf (stream, _("\
   -relax                 create linker relaxable code\n"));
@@ -558,7 +571,9 @@ debug_sym (ignore)
     }
 
   symbol_table_insert (symbolP);
-  if (S_IS_DEFINED (symbolP) && S_GET_SEGMENT (symbolP) != reg_section)
+  if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section
+                                 || S_IS_EXTERNAL (symbolP)
+                                 || S_IS_WEAK (symbolP)))
     /* xgettext:c-format */
     as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
 
@@ -1710,7 +1725,9 @@ md_estimate_size_before_relax (fragP, segment)
      However, we can't finish the fragment here and emit the reloc as insn
      alignment requirements may move the insn about.  */
 
-  if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
+  if (S_GET_SEGMENT (fragP->fr_symbol) != segment
+      || S_IS_EXTERNAL (fragP->fr_symbol)
+      || S_IS_WEAK (fragP->fr_symbol))
     {
 #if 0
       int old_fr_fix = fragP->fr_fix;
@@ -1816,12 +1833,18 @@ md_convert_frag (abfd, sec, fragP)
       abort ();
     }
 
-  if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
+  if (S_GET_SEGMENT (fragP->fr_symbol) != sec
+      || S_IS_EXTERNAL (fragP->fr_symbol)
+      || S_IS_WEAK (fragP->fr_symbol))
     {
       /* Symbol must be resolved by linker.  */
       if (fragP->fr_offset & 3)
 	as_warn (_("Addend to unresolved symbol not on word boundary."));
-      addend = fragP->fr_offset >> 2;
+#ifdef USE_M32R_OLD_RELOC
+      addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */
+#else
+      addend = 0;
+#endif
     }
   else
     {
@@ -1833,7 +1856,9 @@ md_convert_frag (abfd, sec, fragP)
   /* Create a relocation for symbols that must be resolved by the linker.
      Otherwise output the completed insn.  */
 
-  if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
+  if (S_GET_SEGMENT (fragP->fr_symbol) != sec
+      || S_IS_EXTERNAL (fragP->fr_symbol)
+      || S_IS_WEAK (fragP->fr_symbol))
     {
       assert (fragP->fr_subtype != 1);
       assert (fragP->fr_cgen.insn != 0);
@@ -1874,7 +1899,9 @@ md_pcrel_from_section (fixP, sec)
 {
   if (fixP->fx_addsy != (symbolS *) NULL
       && (! S_IS_DEFINED (fixP->fx_addsy)
-	  || S_GET_SEGMENT (fixP->fx_addsy) != sec))
+	  || S_GET_SEGMENT (fixP->fx_addsy) != sec
+          || S_IS_EXTERNAL (fixP->fx_addsy)
+          || S_IS_WEAK (fixP->fx_addsy)))
     {
       /* The symbol is undefined (or is defined but not in this section).
 	 Let the linker figure it out.  */
@@ -2189,6 +2216,23 @@ m32r_fix_adjustable (fixP)
   else
     reloc_type = fixP->fx_r_type;
 
+  if (fixP->fx_addsy == NULL)
+    return 1;
+
+  /* Prevent all adjustments to global symbols.  */
+  if (S_IS_EXTERN (fixP->fx_addsy))
+    return 0;
+  if (S_IS_WEAK (fixP->fx_addsy))
+    return 0;
+
+  if (pic_code
+      && (reloc_type == BFD_RELOC_M32R_24
+          || reloc_type == BFD_RELOC_M32R_26_PCREL
+          || reloc_type == BFD_RELOC_M32R_HI16_SLO
+          || reloc_type == BFD_RELOC_M32R_HI16_ULO
+          || reloc_type == BFD_RELOC_M32R_LO16))
+    return 0;
+
   /* We need the symbol name for the VTABLE entries.  */
   if (reloc_type == BFD_RELOC_VTABLE_INHERIT
       || reloc_type == BFD_RELOC_VTABLE_ENTRY)
@@ -2204,3 +2248,99 @@ m32r_elf_final_processing ()
     m32r_flags |= E_M32R_HAS_PARALLEL;
   elf_elfheader (stdoutput)->e_flags |= m32r_flags;
 }
+
+#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
+ 
+/* Translate internal representation of relocation info to BFD target
+   format. */
+arelent *
+tc_gen_reloc (section, fixP)
+     asection * section;
+     fixS *     fixP;
+{
+  arelent * reloc;
+  bfd_reloc_code_real_type code;
+ 
+  reloc = (arelent *) xmalloc (sizeof (arelent));
+ 
+  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
+  reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
+ 
+  code = fixP->fx_r_type;
+  if (pic_code)
+    {
+#ifdef DEBUG_PIC
+printf("%s",bfd_get_reloc_code_name(code));
+#endif
+      switch (code)
+        {
+        case BFD_RELOC_M32R_26_PCREL:
+            code = BFD_RELOC_M32R_26_PLTREL;
+          break;
+        case BFD_RELOC_M32R_24:
+          if (fixP->fx_addsy != NULL
+              && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
+            code = BFD_RELOC_M32R_GOTPC24;
+          else
+            code = BFD_RELOC_M32R_GOT24;
+          break;
+        case BFD_RELOC_M32R_HI16_ULO:
+          if (fixP->fx_addsy != NULL
+              && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
+            code = BFD_RELOC_M32R_GOTPC_HI_ULO;
+          else
+            code = BFD_RELOC_M32R_GOT16_HI_ULO;
+          break;
+        case BFD_RELOC_M32R_HI16_SLO:
+          if (fixP->fx_addsy != NULL
+              && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
+            code = BFD_RELOC_M32R_GOTPC_HI_SLO;
+          else
+            code = BFD_RELOC_M32R_GOT16_HI_SLO;
+          break;
+        case BFD_RELOC_M32R_LO16:
+          if (fixP->fx_addsy != NULL
+              && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
+            code = BFD_RELOC_M32R_GOTPC_LO;
+          else
+            code = BFD_RELOC_M32R_GOT16_LO;
+          break;
+        default:
+          break;
+        }
+#ifdef DEBUG_PIC
+printf(" => %s",bfd_get_reloc_code_name(code));
+#endif
+    }
+ 
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
+#ifdef DEBUG_PIC
+printf(" => %s\n",reloc->howto->name);
+#endif
+  if (reloc->howto == (reloc_howto_type *) NULL)
+    {
+      as_bad_where (fixP->fx_file, fixP->fx_line,
+            _("internal error: can't export reloc type %d (`%s')"),
+            fixP->fx_r_type, bfd_get_reloc_code_name (code));
+      return NULL;
+    }
+ 
+  /* Use fx_offset for these cases */
+  if (   fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
+      || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT)
+    reloc->addend  = fixP->fx_offset;
+  else if (!pic_code
+           && fixP->fx_pcrel
+           && fixP->fx_addsy != NULL
+           && (S_GET_SEGMENT(fixP->fx_addsy) != section)
+           && S_IS_DEFINED (fixP->fx_addsy)
+           && ! S_IS_EXTERNAL(fixP->fx_addsy)
+           && ! S_IS_WEAK(fixP->fx_addsy))
+    /* already used fx_offset in the opcode field itseld. */
+    reloc->addend  = 0;
+  else
+    reloc->addend  = fixP->fx_addnumber;
+ 
+  return reloc;
+}
diff --git a/gas/config/tc-m32r.h b/gas/config/tc-m32r.h
index 1a8e655..4769214 100644
--- a/gas/config/tc-m32r.h
+++ b/gas/config/tc-m32r.h
@@ -87,14 +87,31 @@ bfd_boolean m32r_fix_adjustable PARAMS ((struct fix *));
    HI16 relocs and queue them up for later sorting.  */
 #define md_cgen_record_fixup_exp m32r_cgen_record_fixup_exp
 
-#define tc_gen_reloc gas_cgen_tc_gen_reloc
+/* #define tc_gen_reloc gas_cgen_tc_gen_reloc */
+
+#define TC_HANDLES_FX_DONE
+
+extern int pic_code;
+
+extern bfd_boolean m32r_fix_adjustable PARAMS ((struct fix *));
+
+/* This arranges for gas/write.c to not apply a relocation if
+   obj_fix_adjustable() says it is not adjustable.  */
+#define TC_FIX_ADJUSTABLE(fixP) obj_fix_adjustable (fixP)
+
+#define TC_RELOC_RTSYM_LOC_FIXUP(FIX)                           \
+   ((FIX)->fx_addsy == NULL                                     \
+    || (! S_IS_EXTERNAL ((FIX)->fx_addsy)                       \
+        && ! S_IS_WEAK ((FIX)->fx_addsy)                        \
+        && S_IS_DEFINED ((FIX)->fx_addsy)                       \
+        && ! S_IS_COMMON ((FIX)->fx_addsy)))
 
 #define tc_frob_file_before_fix() m32r_frob_file ()
 extern void m32r_frob_file PARAMS ((void));
 
 /* No shared lib support, so we don't need to ensure externally
-   visible symbols can be overridden.  */
-#define EXTERN_FORCE_RELOC 0
+   visible symbols can be overridden.
+#define EXTERN_FORCE_RELOC 0 */
 
 /* When relaxing, we need to emit various relocs we otherwise wouldn't.  */
 #define TC_FORCE_RELOCATION(fix) m32r_force_relocation (fix)
diff --git a/gas/configure b/gas/configure
index 5c08fc6..37926bc 100755
--- a/gas/configure
+++ b/gas/configure
@@ -4000,6 +4000,8 @@ for this_target in $target $canon_targets ; do
       sparc*)		cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c.
       v850*)		cpu_type=v850 ;;
       xtensa*)		cpu_type=xtensa arch=xtensa ;;
+      m32r)             cpu_type=m32r target_cpu=m32r endian=big ;;
+      m32rle)           cpu_type=m32r target_cpu=m32r endian=little ;;
       *)		cpu_type=${cpu} ;;
     esac
 
@@ -4180,7 +4182,8 @@ echo "$as_me: WARNING: GAS support for ${generic_target} is preliminary and a wo
 
       iq2000-*-elf)         		fmt=elf bfd_gas=yes ;;
 
-      m32r-*-*)				fmt=elf ;;
+      m32r-*-elf*)			fmt=elf ;;
+      m32r-*-linux*)			fmt=elf em=linux;;
 
       m68hc11-*-* | m6811-*-*)		fmt=elf ;;
       m68hc12-*-* | m6812-*-*)		fmt=elf ;;
diff --git a/gas/configure.in b/gas/configure.in
index 6c266bb..514fee4 100644
--- a/gas/configure.in
+++ b/gas/configure.in
@@ -164,6 +164,8 @@ changequote([,])dnl
       sparc*)		cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c.
       v850*)		cpu_type=v850 ;;
       xtensa*)		cpu_type=xtensa arch=xtensa ;;
+      m32r)             cpu_type=m32r target_cpu=m32r endian=big ;;
+      m32rle)           cpu_type=m32r target_cpu=m32r endian=little ;;
       *)		cpu_type=${cpu} ;;
     esac
 
@@ -337,7 +339,8 @@ changequote([,])dnl
 
       iq2000-*-elf)         		fmt=elf bfd_gas=yes ;;
 
-      m32r-*-*)				fmt=elf ;;
+      m32r-*-elf*)			fmt=elf ;;
+      m32r-*-linux*)			fmt=elf em=linux;;
 
       m68hc11-*-* | m6811-*-*)		fmt=elf ;;
       m68hc12-*-* | m6812-*-*)		fmt=elf ;;
diff --git a/gas/doc/c-m32r.texi b/gas/doc/c-m32r.texi
index 8159090..4360ee6 100644
--- a/gas/doc/c-m32r.texi
+++ b/gas/doc/c-m32r.texi
@@ -75,6 +75,12 @@ data.
 @cindex @code{-EB} option, M32R
 This is a synonum for @emph{-big}.
 
+@item -KPIC
+@cindex @code{-KPIC} option, M32R
+@cindex PIC code generation for M32R
+This option specifies that the output of the assembler should be
+marked as position-independent code (PIC).
+
 @item -parallel
 @cindex @code{-parallel} option, M32RX
 This option tells the assembler to attempts to combine two sequential
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 829fb75..b0f00eb 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,16 @@
+2003-12-19  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* gas/m32r/m32rx.s: Changed pattern bncl to bncl.s.
+	* gas/m32r/allinsn.d: Update for New RELA-ABI.
+	* gas/m32r/high-1.d: Likewise.
+	* gas/m32r/relax-1.d: Likewise.
+	* gas/m32r/uppercase.d: Likewise.
+	* gas/m32r/m32rx.d: Likewise.
+	* gas/vtable/vtable.exp: Likewise.
+	* gas/m32r/pic.exp: New file for PIC.
+	* gas/m32r/pic.s: Likewise.
+	* gas/m32r/pic.d: Likewise.
+
 2003-12-18  Richard Sandiford  <rsandifo@redhat.com>
 
 	* gas/mips/mips16-jalx.d: Use -mabi=o64.
diff --git a/gas/testsuite/gas/m32r/allinsn.d b/gas/testsuite/gas/m32r/allinsn.d
index 55965e6..18c80c3 100644
--- a/gas/testsuite/gas/m32r/allinsn.d
+++ b/gas/testsuite/gas/m32r/allinsn.d
@@ -209,7 +209,7 @@ Disassembly of section .text:
 
 0+010c <ld24>:
  10c:	ed 00 00 00 	ld24 fp,[#]*0 <add>
-			10c: R_M32R_24	.data
+			10c: R_M32R_24_RELA	.data
 
 0+0110 <ldi8>:
  110:	6d 00 f0 00 	ldi fp,[#]*0 \|\| nop
diff --git a/gas/testsuite/gas/m32r/high-1.d b/gas/testsuite/gas/m32r/high-1.d
index b5ccb8c..7c3d22a 100644
--- a/gas/testsuite/gas/m32r/high-1.d
+++ b/gas/testsuite/gas/m32r/high-1.d
@@ -7,10 +7,10 @@
 Disassembly of section .text:
 
 0* <foo>:
- *0:	d4 c0 00 01 	seth r4,[#]*0x1
-[ 	]*0: R_M32R_HI16_ULO	.text
+ *0:	d4 c0 00 00 	seth r4,[#]*0x0
+[ 	]*0: R_M32R_HI16_ULO_RELA	.text\+0x10000
  *4:	84 e4 00 00 	or3 r4,r4,[#]*0x0
-[ 	]*4: R_M32R_LO16	.text
+[ 	]*4: R_M32R_LO16_RELA	.text\+0x10000
  *8:	d4 c0 12 34 	seth r4,[#]*0x1234
  *c:	84 e4 87 65 	or3 r4,r4,[#]*0x8765
  *10:	d4 c0 12 35 	seth r4,[#]*0x1235
diff --git a/gas/testsuite/gas/m32r/m32rx.d b/gas/testsuite/gas/m32r/m32rx.d
index 6713dd2..89b618b 100644
--- a/gas/testsuite/gas/m32r/m32rx.d
+++ b/gas/testsuite/gas/m32r/m32rx.d
@@ -85,28 +85,40 @@ Disassembly of section .text:
   64:	54 81 f0 00 	rach a1,a0,#0x2 \|\| nop
 
 0+0068 <bc__add>:
-  68:	7c e6 8d ad 	bc 0 <bcl> \|\| add fp,fp
-  6c:	7c e5 0d ad 	bc 0 <bcl> -> add fp,fp
+  68:	7c 00 8d ad 	bc 68 <bc__add> \|\| add fp,fp
+			68: R_M32R_10_PCREL_RELA	bcl
+  6c:	7c 00 0d ad 	bc 6c <bc__add\+0x4> -> add fp,fp
+			6c: R_M32R_10_PCREL_RELA	bcl
 
 0+0070 <bcl__addi>:
-  70:	78 e4 cd 4d 	bcl 0 <bcl> \|\| addi fp,#77
-  74:	78 e3 cd 4d 	bcl 0 <bcl> \|\| addi fp,#77
+  70:	78 00 cd 4d 	bcl 70 <bcl__addi> \|\| addi fp,#77
+			70: R_M32R_10_PCREL_RELA	bcl
+  74:	78 00 cd 4d 	bcl 74 <bcl__addi\+0x4> \|\| addi fp,#77
+			74: R_M32R_10_PCREL_RELA	bcl
 
 0+0078 <bl__addv>:
-  78:	7e e2 8d 8d 	bl 0 <bcl> \|\| addv fp,fp
-  7c:	7e e1 8d 8d 	bl 0 <bcl> \|\| addv fp,fp
+  78:	7e 00 8d 8d 	bl 78 <bl__addv> \|\| addv fp,fp
+			78: R_M32R_10_PCREL_RELA	bcl
+  7c:	7e 00 8d 8d 	bl 7c <bl__addv\+0x4> \|\| addv fp,fp
+			7c: R_M32R_10_PCREL_RELA	bcl
 
 0+0080 <bnc__addx>:
-  80:	7d e0 8d 9d 	bnc 0 <bcl> \|\| addx fp,fp
-  84:	7d df 0d 9d 	bnc 0 <bcl> -> addx fp,fp
+  80:	7d 00 8d 9d 	bnc 80 <bnc__addx> \|\| addx fp,fp
+			80: R_M32R_10_PCREL_RELA	bcl
+  84:	7d 00 0d 9d 	bnc 84 <bnc__addx\+0x4> -> addx fp,fp
+			84: R_M32R_10_PCREL_RELA	bcl
 
 0+0088 <bncl__and>:
-  88:	79 de 8d cd 	bncl 0 <bcl> \|\| and fp,fp
-  8c:	0d cd 79 dd 	and fp,fp -> bncl 0 <bcl>
+  88:	79 00 8d cd 	bncl 88 <bncl__and> \|\| and fp,fp
+			88: R_M32R_10_PCREL_RELA	bcl
+  8c:	79 00 8d cd 	bncl 8c <bncl__and\+0x4> \|\| and fp,fp
+			8c: R_M32R_10_PCREL_RELA	bcl
 
 0+0090 <bra__cmp>:
-  90:	7f dc 8d 4d 	bra 0 <bcl> \|\| cmp fp,fp
-  94:	7f db 8d 4d 	bra 0 <bcl> \|\| cmp fp,fp
+  90:	7f 00 8d 4d 	bra 90 <bra__cmp> \|\| cmp fp,fp
+			90: R_M32R_10_PCREL_RELA	bcl
+  94:	7f 00 8d 4d 	bra 94 <bra__cmp\+0x4> \|\| cmp fp,fp
+			94: R_M32R_10_PCREL_RELA	bcl
 
 0+0098 <jl__cmpeq>:
   98:	1e cd 8d 6d 	jl fp \|\| cmpeq fp,fp
diff --git a/gas/testsuite/gas/m32r/m32rx.s b/gas/testsuite/gas/m32r/m32rx.s
index b86dab0..e25ec77 100644
--- a/gas/testsuite/gas/m32r/m32rx.s
+++ b/gas/testsuite/gas/m32r/m32rx.s
@@ -172,7 +172,7 @@ bnc__addx:
 bncl__and:
 	bncl bcl || and fp, fp
 	and fp, fp
-	bncl bcl
+	bncl.s bcl
 
 	.text
 	.global bra__cmp
diff --git a/gas/testsuite/gas/m32r/pic.d b/gas/testsuite/gas/m32r/pic.d
new file mode 100644
index 0000000..a880a1b
--- /dev/null
+++ b/gas/testsuite/gas/m32r/pic.d
@@ -0,0 +1,47 @@
+#as: -K PIC
+#objdump: -dr 
+#name: pic
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+0000 <pic_gotpc>:
+   0:	7e 01 f0 00 	bl 4 <pic_gotpc\+0x4> \|\| nop
+   4:	ec 00 00 00 	ld24 r12,0 <pic_gotpc>
+			4: R_M32R_GOTPC24	_GLOBAL_OFFSET_TABLE_
+   8:	0c ae f0 00 	add r12,lr \|\| nop
+
+0+000c <pic_gotpc_slo>:
+   c:	7e 01 f0 00 	bl 10 <pic_gotpc_slo\+0x4> \|\| nop
+  10:	dc c0 00 00 	seth r12,[#]0x0
+			10: R_M32R_GOTPC_HI_SLO	_GLOBAL_OFFSET_TABLE_
+  14:	8c ac 00 00 	add3 r12,r12,[#]0
+			14: R_M32R_GOTPC_LO	_GLOBAL_OFFSET_TABLE_\+0x4
+  18:	0c ae f0 00 	add r12,lr \|\| nop
+
+0+001c <pic_gotpc_ulo>:
+  1c:	7e 01 f0 00 	bl 20 <pic_gotpc_ulo\+0x4> \|\| nop
+  20:	dc c0 00 00 	seth r12,[#]0x0
+			20: R_M32R_GOTPC_HI_ULO	_GLOBAL_OFFSET_TABLE_
+  24:	8c ec 00 00 	or3 r12,r12,[#]0x0
+			24: R_M32R_GOTPC_LO	_GLOBAL_OFFSET_TABLE_\+0x4
+  28:	0c ae f0 00 	add r12,lr \|\| nop
+
+0+002c <pic_got>:
+  2c:	e0 00 00 00 	ld24 r0,0 <pic_gotpc>
+			2c: R_M32R_GOT24	sym
+
+0+0030 <pic_got16>:
+  30:	dc c0 00 00 	seth r12,[#]0x0
+			30: R_M32R_GOT16_HI_SLO	sym2
+  34:	8c ac 00 00 	add3 r12,r12,[#]0
+			34: R_M32R_GOT16_LO	sym2\+0x4
+  38:	dc c0 00 00 	seth r12,[#]0x0
+			38: R_M32R_GOT16_HI_ULO	sym2
+  3c:	8c ec 00 00 	or3 r12,r12,[#]0x0
+			3c: R_M32R_GOT16_LO	sym2\+0x4
+
+0+0040 <pic_plt>:
+  40:	fe 00 00 00 	bl 40 <pic_plt>
+			40: R_M32R_26_PLTREL	func
diff --git a/gas/testsuite/gas/m32r/pic.exp b/gas/testsuite/gas/m32r/pic.exp
new file mode 100644
index 0000000..391a780
--- /dev/null
+++ b/gas/testsuite/gas/m32r/pic.exp
@@ -0,0 +1,5 @@
+# M32R PIC testcases
+
+if [istarget m32r*-*-*] {
+    run_dump_test "pic"
+}
diff --git a/gas/testsuite/gas/m32r/pic.s b/gas/testsuite/gas/m32r/pic.s
new file mode 100644
index 0000000..94b3b35
--- /dev/null
+++ b/gas/testsuite/gas/m32r/pic.s
@@ -0,0 +1,43 @@
+	.section .text
+# R_M32R_GOTPC24
+pic_gotpc:
+	bl.s .+4
+        ld24 r12,#_GLOBAL_OFFSET_TABLE_
+	add r12,lr
+
+# R_M32R_GOTPC_HI_ULO
+# R_M32R_GOTPC_HI_SLO
+# R_M32R_GOTPC_LO
+pic_gotpc_slo:
+	bl.s .+4
+        seth r12,#shigh(_GLOBAL_OFFSET_TABLE_)
+        add3 r12,r12,#low(_GLOBAL_OFFSET_TABLE_+4)
+	add r12,lr
+
+pic_gotpc_ulo:
+	bl.s .+4
+        seth r12,#high(_GLOBAL_OFFSET_TABLE_)
+        or3 r12,r12,#low(_GLOBAL_OFFSET_TABLE_+4)
+	add r12,lr
+
+# R_M32R_GOT24
+pic_got:
+	.global sym
+	ld24 r0,#sym
+
+# R_M32R_GOT16_HI_ULO
+# R_M32R_GOT16_HI_SLO
+# R_M32R_GOT16_LO
+pic_got16:
+	.global sym2
+        seth r12,#shigh(sym2)
+        add3 r12,r12,#low(sym2+4)
+        seth r12,#high(sym2)
+        or3 r12,r12,#low(sym2+4)
+
+# R_M32R_26_PLTREL
+pic_plt:
+	.global func
+	bl func
+
+	.end
diff --git a/gas/testsuite/gas/m32r/relax-1.d b/gas/testsuite/gas/m32r/relax-1.d
index 2a4fcb8..64f906c 100644
--- a/gas/testsuite/gas/m32r/relax-1.d
+++ b/gas/testsuite/gas/m32r/relax-1.d
@@ -15,4 +15,4 @@ Disassembly of section .branch:
 
 0* <branch>:
  *0:	ff 00 00 01 	bra 4 <Work>
-[ 	]*0: R_M32R_26_PCREL	.text
+[ 	]*0: R_M32R_26_PCREL_RELA	.text
diff --git a/gas/testsuite/gas/m32r/uppercase.d b/gas/testsuite/gas/m32r/uppercase.d
index 12b1345..ead239c 100644
--- a/gas/testsuite/gas/m32r/uppercase.d
+++ b/gas/testsuite/gas/m32r/uppercase.d
@@ -11,16 +11,16 @@ Disassembly of section .text:
 
 0+0004 <high>:
    4:	d0 c0 00 00 	seth r0,#0x0
-[ 	]*4: R_M32R_HI16_ULO	[.]text
+[ 	]*4: R_M32R_HI16_ULO_RELA	[.]text\+0x4
 
 0+0008 <shigh>:
    8:	d0 c0 00 00 	seth r0,#0x0
-[ 	]*8: R_M32R_HI16_SLO	[.]text
+[ 	]*8: R_M32R_HI16_SLO_RELA	[.]text\+0x8
 
 0+000c <low>:
-   c:	80 e0 00 0c 	or3 r0,r0,#0xc
-[ 	]*c: R_M32R_LO16	[.]text
+   c:	80 e0 00 00 	or3 r0,r0,#0x0
+[ 	]*c: R_M32R_LO16_RELA	[.]text\+0xc
 
 0+0010 <sda>:
   10:	80 a0 00 00 	add3 r0,r0,#0
-[ 	]*10: R_M32R_SDA16	sdavar
+[ 	]*10: R_M32R_SDA16_RELA	sdavar
diff --git a/gas/testsuite/gas/vtable/vtable.exp b/gas/testsuite/gas/vtable/vtable.exp
index 0b50921..cb74b7a 100644
--- a/gas/testsuite/gas/vtable/vtable.exp
+++ b/gas/testsuite/gas/vtable/vtable.exp
@@ -41,7 +41,6 @@ if { (   [istarget "*-*-elf*"] || [istarget "*-*-linux*"])
 	|| [istarget "d10v-*"]
 	|| [istarget "dlx-*"]
 	|| [istarget "i*86-*"] 
-	|| [istarget "m32r-*"] 
 	|| ([istarget "mips*-*"]
 	    && ! [istarget "mips64*-*-linux*"]
 	    && ! [istarget "mips*-*-irix6*"])