binutils: support for the SPARC M8 processor

This patch adds support for the new SPARC M8 processor (implementing OSA
2017) to binutils.

New instructions:

- Dictionary Unpack

  + dictunpack

- Partitioned Compare with shifted result

  + Signed variants:   fpcmp{le,gt,eq,ne}{8,16,32}shl
  + Unsigned variants: fpcmpu{le,gt}{8,16,32}shl

- Partitioned Dual-Equal compared, with shifted result

  + fpcmpde{8,16,32}shl

- Partitioned Unsigned Range Compare, with shifted result

  + fpcmpur{8,16,32}shl

- 64-bit shifts on Floating-Point registers

  + fps{ll,ra,rl}64x

- Misaligned loads and stores

  + ldm{sh,uh,sw,uw,x,ux}
  + ldm{sh,uh,sw,uw,x,ux}a
  + ldmf{s,d}
  + ldmf{s,d}a

  + stm{h,w,x}
  + stm{h,w,x}a
  + stmf{s,d}
  + stmf{s,d}a

- Oracle Numbers

  + on{add,sub,mul,div}

- Reverse Bytes/Bits

  + revbitsb
  + revbytes{h,w,x}

- Run-Length instructions

  + rle_burst
  + rle_length

- New crypto instructions

  + sha3

- Instruction to read the new register %entropy

  + rd %entropy

New Alternate Address Identifiers:

- 0x24, #ASI_CORE_COMMIT_COUNT
- 0x24, #ASI_CORE_SELECT_COUNT
- 0x48, #ASI_ARF_ECC_REG
- 0x53, #ASI_ITLB_PROBE
- 0x58, #ASI_DSFAR
- 0x5a, #ASI_DTLB_PROBE_PRIMARY
- 0x5b, #ASI_DTLB_PROBE_REAL
- 0x64, #ASI_CORE_SELECT_COMMIT_NHT

The new assembler command-line options for selecting the M8 architecture
are:

-Av9m8 or -Asparc6 for 64-bit binaries.
-Av8plusm8 for 32-bit (v8+) binaries.

The corresponding disassembler command-line options are:

-msparc:v9m8 for 64-bit binaries.
-msparc:v8plusm8 for 32-bit (v8+) binaries.

Tested for regressions in the following targets:
sparc-aout sparc-linux sparc-vxworks sparc64-linux

bfd/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* archures.c (bfd_mach_sparc_v9m8): Define.
	(bfd_mach_sparc_v8plusm8): Likewise.
	(bfd_mach_sparc_v9_p): Adjust to M8.
	(bfd_mach_sparc_64bit_p): Likewise.
	* aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and
	bfd_mach_sparc_v8plusm8.
	* bfd-in2.h: Regenerated.
	* cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and
	sparc:v8plusm8.
	* elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle
	bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw
	capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and
	SHA3.
	* elf32-sparc.c (elf32_sparc_final_write_processing): Handle
	bfd_mach_sparc_v8plusm8.

binutils/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* NEWS: Mention the SPARC M8 support.

gas/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
	`v9m8' and `v8plusm8'.
	(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
	(get_hwcap_name): Support the M8 hardware capabilities.
	(sparc_ip): Handle new operand types.
	* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
	-Asparc6, and the corresponding -xarch aliases.
	* testsuite/gas/sparc/sparc6.s: New file.
	* testsuite/gas/sparc/sparc6.d: Likewise.
	* testsuite/gas/sparc/sparc6-diag.s: Likewise.
	* testsuite/gas/sparc/sparc6-diag.l: Likewise.
	* testsuite/gas/sparc/fpcmpshl.s: Likewise.
	* testsuite/gas/sparc/fpcmpshl.d: Likewise.
	* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
	* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
	* testsuite/gas/sparc/ldm-stm.s: Likewise.
	* testsuite/gas/sparc/ldm-stm.d: Likewise.
	* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
	* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
	* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
	* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
	* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
	* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
	* testsuite/gas/sparc/on.s: Likewise.
	* testsuite/gas/sparc/on.d: Likewise.
	* testsuite/gas/sparc/on-diag.s: Likewise.
	* testsuite/gas/sparc/on-diag.l: Likewise.
	* testsuite/gas/sparc/rle.s: Likewise.
	* testsuite/gas/sparc/rle.d: Likewise.
	* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
	* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
	* testsuite/gas/sparc/rdasr.d: Likewise.

include/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
	(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
	(ELF_SPARC_HWCAP2_ONMUL): Likewise.
	(ELF_SPARC_HWCAP2_ONDIV): Likewise.
	(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
	(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
	(ELF_SPARC_HWCAP2_RLE): Likewise.
	(ELF_SPARC_HWCAP2_SHA3): Likewise.
	* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
	and adjust SPARC_OPCODE_ARCH_MAX.
	(HWCAP2_SPARC6): Define.
	(HWCAP2_ONADDSUB): Likewise.
	(HWCAP2_ONMUL): Likewise.
	(HWCAP2_ONDIV): Likewise.
	(HWCAP2_DICTUNP): Likewise.
	(HWCAP2_FPCMPSHL): Likewise.
	(HWCAP2_RLE): Likewise.
	(HWCAP2_SHA3): Likewise.
	(OPM): Likewise.
	(OPMI): Likewise.
	(ONFCN): Likewise.
	(REVFCN): Likewise.
	(SIMM10): Likewise.

opcodes/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
	(X_IMM2): Define.
	(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
	bfd_mach_sparc_v9m8.
	(print_insn_sparc): Handle new operand types.
	* sparc-opc.c (MASK_M8): Define.
	(v6): Add MASK_M8.
	(v6notlet): Likewise.
	(v7): Likewise.
	(v8): Likewise.
	(v9): Likewise.
	(v9a): Likewise.
	(v9b): Likewise.
	(v9c): Likewise.
	(v9d): Likewise.
	(v9e): Likewise.
	(v9v): Likewise.
	(v9m): Likewise.
	(v9andleon): Likewise.
	(m8): Define.
	(HWS_VM8): Define.
	(HWS2_VM8): Likewise.
	(sparc_opcode_archs): Add entry for "m8".
	(sparc_opcodes): Add OSA2017 and M8 instructions
	dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
	fpx{ll,ra,rl}64x,
	ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
	ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
	revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
	stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
	(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
	ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
	ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
	ASI_CORE_SELECT_COMMIT_NHT.

28 files changed, 523 insertions, 11 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 211a5a3..8fff0e4 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,40 @@
 2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
+	* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
+	`v9m8' and `v8plusm8'.
+	(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
+	(get_hwcap_name): Support the M8 hardware capabilities.
+	(sparc_ip): Handle new operand types.
+	* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
+	-Asparc6, and the corresponding -xarch aliases.
+	* testsuite/gas/sparc/sparc6.s: New file.
+	* testsuite/gas/sparc/sparc6.d: Likewise.
+	* testsuite/gas/sparc/sparc6-diag.s: Likewise.
+	* testsuite/gas/sparc/sparc6-diag.l: Likewise.
+	* testsuite/gas/sparc/fpcmpshl.s: Likewise.
+	* testsuite/gas/sparc/fpcmpshl.d: Likewise.
+	* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
+	* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
+	* testsuite/gas/sparc/ldm-stm.s: Likewise.
+	* testsuite/gas/sparc/ldm-stm.d: Likewise.
+	* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
+	* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
+	* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
+	* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
+	* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
+	* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
+	* testsuite/gas/sparc/on.s: Likewise.
+	* testsuite/gas/sparc/on.d: Likewise.
+	* testsuite/gas/sparc/on-diag.s: Likewise.
+	* testsuite/gas/sparc/on-diag.l: Likewise.
+	* testsuite/gas/sparc/rle.s: Likewise.
+	* testsuite/gas/sparc/rle.d: Likewise.
+	* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
+	* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
+	* testsuite/gas/sparc/rdasr.d: Likewise.
+
+2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
 	* testsuite/gas/sparc/call-relax.d: Support 32-bit targets.
 	* testsuite/gas/sparc/sparc.exp (gas_64_check): Use -64 to
 	run asi-bump-warn.
diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index 4c930b5..692a187 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -256,6 +256,7 @@ static struct sparc_arch {
 
   { "sparc4",     "v9v", v9,  0, 1, 0, 0 },
   { "sparc5",     "v9m", v9,  0, 1, 0, 0 },
+  { "sparc6",     "m8",  v9,  0, 1, 0, 0 },
 
   { "leon",      "leon",      leon,      32, 1, 0, 0 },
   { "sparclet",  "sparclet",  sparclet,  32, 1, 0, 0 },
@@ -270,7 +271,8 @@ static struct sparc_arch {
   { "v8pluse", "v9e", v9,  0, 1, HWCAP_V8PLUS, 0 },
   { "v8plusv", "v9v", v9,  0, 1, HWCAP_V8PLUS, 0 },
   { "v8plusm", "v9m", v9,  0, 1, HWCAP_V8PLUS, 0 },
-
+  { "v8plusm8", "m8", v9,  0, 1, HWCAP_V8PLUS, 0 },
+  
   { "v9",      "v9",  v9,  0, 1, 0, 0 },
   { "v9a",     "v9a", v9,  0, 1, 0, 0 },
   { "v9b",     "v9b", v9,  0, 1, 0, 0 },
@@ -279,6 +281,7 @@ static struct sparc_arch {
   { "v9e",     "v9e", v9,  0, 1, 0, 0 },
   { "v9v",     "v9v", v9,  0, 1, 0, 0 },
   { "v9m",     "v9m", v9,  0, 1, 0, 0 },
+  { "v9m8",     "m8", v9,  0, 1, 0, 0 },
 
   /* This exists to allow configure.tgt to pass one
      value to specify both the default machine and default word size.  */
@@ -1160,6 +1163,7 @@ sparc_md_end (void)
       case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v9e; break;
       case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v9v; break;
       case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v9m; break;
+      case SPARC_OPCODE_ARCH_M8:  mach = bfd_mach_sparc_v9m8; break;
       default: mach = bfd_mach_sparc_v9; break;
       }
   else
@@ -1174,6 +1178,7 @@ sparc_md_end (void)
       case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v8pluse; break;
       case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v8plusv; break;
       case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v8plusm; break;
+      case SPARC_OPCODE_ARCH_M8:  mach = bfd_mach_sparc_v8plusm8; break;
       /* The sparclite is treated like a normal sparc.  Perhaps it shouldn't
 	 be but for now it is (since that's the way it's always been
 	 treated).  */
@@ -1744,6 +1749,22 @@ get_hwcap_name (bfd_uint64_t mask)
     return "xmont";
   if (mask & HWCAP2_NSEC)
     return "nsec";
+  if (mask & HWCAP2_SPARC6)
+    return "sparc6";
+  if (mask & HWCAP2_ONADDSUB)
+    return "onaddsub";
+  if (mask & HWCAP2_ONMUL)
+    return "onmul";
+  if (mask & HWCAP2_ONDIV)
+    return "ondiv";
+  if (mask & HWCAP2_DICTUNP)
+    return "dictunp";
+  if (mask & HWCAP2_FPCMPSHL)
+    return "fpcmpshl";
+  if (mask & HWCAP2_RLE)
+    return "rle";
+  if (mask & HWCAP2_SHA3)
+    return "sha3";
 
   return "UNKNOWN";
 }
@@ -2532,10 +2553,13 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
 	    case 'e':		/* next operand is a floating point register */
 	    case 'v':
 	    case 'V':
+            case ';':
 
 	    case 'f':
 	    case 'B':
 	    case 'R':
+            case ':':
+            case '\'':
 
 	    case '4':
 	    case '5':
@@ -2544,6 +2568,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
 	    case 'H':
 	    case 'J':
 	    case '}':
+            case '^':
 	      {
 		char format;
 
@@ -2562,6 +2587,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
 			 || *args == 'B'
 			 || *args == '5'
 			 || *args == 'H'
+                         || *args == '\''
 			 || format == 'd')
 			&& (mask & 1))
 		      {
@@ -2579,6 +2605,21 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
 			break;
 		      }
 
+                    if ((*args == ':'
+                         || *args == ';'
+                         || *args == '^')
+                        && (mask & 7))
+                      {
+                        /* register must be multiple of 8 */
+                        break;
+                      }
+
+                    if (*args == '\'' && mask < 48)
+                      {
+                        /* register must be higher or equal than %f48 */
+                        break;
+                      }
+
 		    if (mask >= 64)
 		      {
 			if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
@@ -2624,15 +2665,21 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
 		  case 'v':
 		  case 'V':
 		  case 'e':
+                  case ';':
 		    opcode |= RS1 (mask);
 		    continue;
 
 		  case 'f':
 		  case 'B':
 		  case 'R':
+                  case ':':
 		    opcode |= RS2 (mask);
 		    continue;
 
+                  case '\'':
+                    opcode |= RS2 (mask & 0xe);
+                    continue;
+                    
 		  case '4':
 		  case '5':
 		    opcode |= RS3 (mask);
@@ -2642,6 +2689,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
 		  case 'H':
 		  case 'J':
 		  case '}':
+                  case '^':
 		    opcode |= RD (mask);
 		    continue;
 		  }		/* Pack it in.  */
@@ -3061,6 +3109,12 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
 	      s += 7;
 	      continue;
 
+            case '&':
+              if (strncmp (s, "%entropy", 8) != 0)
+                break;
+              s += 8;
+              continue;
+
 	    case 'E':
 	      if (strncmp (s, "%ccr", 4) != 0)
 		break;
@@ -3079,6 +3133,26 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
 	      s += 4;
 	      continue;
 
+            case '|':
+              {
+                int imm2 = 0;
+
+                /* Parse a 2-bit immediate.  */
+                if (! parse_const_expr_arg (&s, &imm2))
+                  {
+                    error_message = _(": non-immdiate imm2 operand");
+                    goto error;
+                  }
+                if ((imm2 & ~0x3) != 0)
+                  {
+                    error_message = _(": imm2 immediate operand out of range (0-3)");
+                    goto error;
+                  }
+
+                opcode |= ((imm2 & 0x2) << 3) | (imm2 & 0x1);
+                continue;
+              }
+              
 	    case 'x':
 	      {
 		char *push = input_line_pointer;
diff --git a/gas/doc/c-sparc.texi b/gas/doc/c-sparc.texi
index 1f789cf..2d15239 100644
--- a/gas/doc/c-sparc.texi
+++ b/gas/doc/c-sparc.texi
@@ -71,10 +71,11 @@ is explicitly requested.  SPARC v9 is always incompatible with sparclite.
 @kindex -Asparcvis3
 @kindex -Asparcvis3r
 @item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite
-@itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv | -Av8plusm
-@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m
+@itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd |
+@itemx -Av8plusv | -Av8plusm | -Av8plusm8
+@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m | -Av9m8
 @itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
-@itemx -Asparcvis3 | -Asparcvis3r | -Asparc5
+@itemx -Asparcvis3 | -Asparcvis3r | -Asparc5 | -Asparc6
 Use one of the @samp{-A} options to select one of the SPARC
 architectures explicitly.  If you select an architecture explicitly,
 @code{@value{AS}} reports a fatal error if it encounters an instruction
@@ -113,6 +114,10 @@ enabled by @samp{-Av8pluse} and @samp{-Av9e}.
 xmpmul, xmontmul and xmontsqr instructions, as well as the instructions
 enabled by @samp{-Av8plusv} and @samp{-Av9v}.
 
+@samp{-Av8plusm8} and @samp{-Av9m8} enable the instructions introduced
+in the Oracle SPARC Architecture 2017 and the M8 processor, as
+well as the instructions enabled by @samp{-Av8plusm} and @samp{-Av9m}.
+
 @samp{-Asparc} specifies a v9 environment.  It is equivalent to
 @samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise.
 
@@ -136,17 +141,22 @@ and floating point unfused multiply-add instructions enabled.
 
 @samp{-Asparc5} is equivalent to @samp{-Av9m}.
 
+@samp{-Asparc6} is equivalent to @samp{-Av9m8}.
+
 @item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
-@itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm | -xarch=v9 | -xarch=v9a
-@itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v | -xarch=v9m
+@itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm |
+@itemx -xarch=v8plusm8 | -xarch=v9 | -xarch=v9a | -xarch=v9b
+@itemx -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v
+@itemx -xarch=v9m | -xarch=v9m8
 @itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
 @itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
-@itemx -xarch=sparcvis3r | -xarch=sparc5
+@itemx -xarch=sparcvis3r | -xarch=sparc5 | -xarch=sparc6
 For compatibility with the SunOS v9 assembler.  These options are
 equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
--Av8plusv, -Av8plusm, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9e, -Av9v, -Av9m,
--Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf, -Asparcima,
--Asparcvis3, and -Asparcvis3r, respectively.
+-Av8plusv, -Av8plusm, -Av8plusm8, -Av9, -Av9a, -Av9b, -Av9c, -Av9d,
+-Av9e, -Av9v, -Av9m, -Av9m8, -Asparc, -Asparcvis, -Asparcvis2,
+-Asparcfmaf, -Asparcima, -Asparcvis3, -Asparcvis3r, -Asparc5 and
+-Asparc6 respectively.
 
 @item -bump
 Warn whenever it is necessary to switch to another level.
diff --git a/gas/testsuite/gas/sparc/fpcmpshl-diag.l b/gas/testsuite/gas/sparc/fpcmpshl-diag.l
new file mode 100644
index 0000000..d48f59f
--- /dev/null
+++ b/gas/testsuite/gas/sparc/fpcmpshl-diag.l
@@ -0,0 +1,6 @@
+.*fpcmpshl-diag.s: Assembler messages:
+.*fpcmpshl-diag.s:3: Error: Illegal operands: imm2 immediate operand out of range.*
+.*fpcmpshl-diag.s:4: Error: Illegal operands
+.*fpcmpshl-diag.s:5: Error: Illegal operands
+.*fpcmpshl-diag.s:6: Error: Illegal operands
+.*fpcmpshl-diag.s:7: Error: Illegal operands
diff --git a/gas/testsuite/gas/sparc/fpcmpshl-diag.s b/gas/testsuite/gas/sparc/fpcmpshl-diag.s
new file mode 100644
index 0000000..943a37e
--- /dev/null
+++ b/gas/testsuite/gas/sparc/fpcmpshl-diag.s
@@ -0,0 +1,7 @@
+# Diagnostic tests for FPCP{ULE8,UGT8,EQ8,NE}{8,16,32}SHL instructions.
+        .text
+        fpcmpule8shl	%f32, %f48, 4, %g1	! Overflow in imm2 operand.
+        fpcmpugt8shl	%f33, %f50, 4, %g2	! Invalid frs1.
+        fpcmpeq8shl	%f36, %f53, 4, %g3	! Invalid frs2.
+        fpcmpne8shl	%f38, %f46, 4, %g4	! Likewise.
+        fpcmpule16shl	%f32, %f0, 4, %g1	! Likewise.
diff --git a/gas/testsuite/gas/sparc/fpcmpshl.d b/gas/testsuite/gas/sparc/fpcmpshl.d
new file mode 100644
index 0000000..de0764c
--- /dev/null
+++ b/gas/testsuite/gas/sparc/fpcmpshl.d
@@ -0,0 +1,27 @@
+#as: -Av9m8
+#objdump: -dr
+#name: FPCMPSHL OSA2017 instructions
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	83 b0 72 00 	fpcmpule8shl  %f32, %f48, 0, %g1
+   4:	85 b0 f2 23 	fpcmpugt8shl  %f34, %f50, 1, %g2
+   8:	87 b1 72 54 	fpcmpeq8shl  %f36, %f52, 2, %g3
+   c:	89 b1 f2 7f 	fpcmpne8shl  %f38, %f62, 3, %g4
+  10:	83 b0 72 80 	fpcmpule16shl  %f32, %f48, 0, %g1
+  14:	85 b0 f2 a3 	fpcmpugt16shl  %f34, %f50, 1, %g2
+  18:	87 b1 72 d4 	fpcmpeq16shl  %f36, %f52, 2, %g3
+  1c:	89 b1 f2 ff 	fpcmpne16shl  %f38, %f62, 3, %g4$
+  20:	83 b0 73 00 	fpcmpule32shl  %f32, %f48, 0, %g1
+  24:	85 b0 f3 23 	fpcmpugt32shl  %f34, %f50, 1, %g2
+  28:	87 b1 73 54 	fpcmpeq32shl  %f36, %f52, 2, %g3
+  2c:	89 b1 f3 7f 	fpcmpne32shl  %f38, %f62, 3, %g4
+  30:	83 b0 48 a0 	fpcmpde8shl  %f32, %f48, 0, %g1
+  34:	85 b0 c8 e3 	fpcmpde16shl  %f34, %f50, 1, %g2
+  38:	87 b1 49 54 	fpcmpde32shl  %f36, %f52, 2, %g3
+  3c:	83 b0 73 80 	fpcmpur8shl  %f32, %f48, 0, %g1
+  40:	85 b0 f3 a3 	fpcmpur16shl  %f34, %f50, 1, %g2
+  44:	87 b1 73 d4 	fpcmpur32shl  %f36, %f52, 2, %g3
diff --git a/gas/testsuite/gas/sparc/fpcmpshl.s b/gas/testsuite/gas/sparc/fpcmpshl.s
new file mode 100644
index 0000000..11fe5ca
--- /dev/null
+++ b/gas/testsuite/gas/sparc/fpcmpshl.s
@@ -0,0 +1,19 @@
+# Test FPCMP{ULE8,UGT8,EQ8,NE,DE,UR}{8,16,32}SHL instructions.
+        fpcmpule8shl	%f32, %f48, 0, %g1
+        fpcmpugt8shl	%f34, %f50, 1, %g2
+        fpcmpeq8shl	%f36, %f52, 2, %g3
+        fpcmpne8shl	%f38, %f62, 3, %g4
+        fpcmpule16shl	%f32, %f48, 0x0, %g1
+        fpcmpugt16shl	%f34, %f50, 0x1, %g2
+        fpcmpeq16shl	%f36, %f52, 0x2, %g3
+        fpcmpne16shl	%f38, %f62, 0x3, %g4
+        fpcmpule32shl	%f32, %f48, 0, %g1
+        fpcmpugt32shl	%f34, %f50, 2-1, %g2
+        fpcmpeq32shl	%f36, %f52, 4/2, %g3
+        fpcmpne32shl	%f38, %f62, 3*1, %g4
+        fpcmpde8shl	%f32, %f48, 0, %g1
+        fpcmpde16shl	%f34, %f50, 1, %g2
+        fpcmpde32shl	%f36, %f52, 2, %g3
+        fpcmpur8shl	%f32, %f48, 0, %g1
+        fpcmpur16shl	%f34, %f50, 1, %g2
+        fpcmpur32shl	%f36, %f52, 2, %g3
diff --git a/gas/testsuite/gas/sparc/ldm-stm-diag.l b/gas/testsuite/gas/sparc/ldm-stm-diag.l
new file mode 100644
index 0000000..45daeeb
--- /dev/null
+++ b/gas/testsuite/gas/sparc/ldm-stm-diag.l
@@ -0,0 +1,3 @@
+.*ldm-stm-diag.s: Assembler messages:
+.*ldm-stm-diag.s:3: Error: relocation overflow
+.*ldm-stm-diag.s:4: Error: relocation overflow
diff --git a/gas/testsuite/gas/sparc/ldm-stm-diag.s b/gas/testsuite/gas/sparc/ldm-stm-diag.s
new file mode 100644
index 0000000..10cabcb
--- /dev/null
+++ b/gas/testsuite/gas/sparc/ldm-stm-diag.s
@@ -0,0 +1,4 @@
+# Diagnostic tests for ldm/stm/ldma/stma
+        .text
+        ldmsh	[%g1+0x401], %g2	! Overflow in simm10 constant.
+        stmh	%g2, [%g1+0x401]	! Likewise.
diff --git a/gas/testsuite/gas/sparc/ldm-stm.d b/gas/testsuite/gas/sparc/ldm-stm.d
new file mode 100644
index 0000000..655ef36
--- /dev/null
+++ b/gas/testsuite/gas/sparc/ldm-stm.d
@@ -0,0 +1,70 @@
+#as: -Av9m8
+#objdump: -dr
+#name: sparc LDM/STM/LDMA/STMA
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	c5 88 00 01 	ldmsh  \[ %g0 \+ %g1 \], %g2
+   4:	c7 88 40 00 	ldmsh  \[ %g1 \], %g3
+   8:	c7 88 60 66 	ldmsh  \[ %g1 \+ 0x66 \], %g3
+   c:	c7 88 60 66 	ldmsh  \[ %g1 \+ 0x66 \], %g3
+  10:	c7 88 20 66 	ldmsh  \[ 0x66 \], %g3
+  14:	c5 88 04 01 	ldmuh  \[ %g0 \+ %g1 \], %g2
+  18:	c7 88 44 00 	ldmuh  \[ %g1 \], %g3
+  1c:	c7 88 64 66 	ldmuh  \[ %g1 \+ 0x66 \], %g3
+  20:	c7 88 64 66 	ldmuh  \[ %g1 \+ 0x66 \], %g3
+  24:	c7 88 24 66 	ldmuh  \[ 0x66 \], %g3
+  28:	c5 88 08 01 	ldmsw  \[ %g0 \+ %g1 \], %g2
+  2c:	c7 88 48 00 	ldmsw  \[ %g1 \], %g3
+  30:	c7 88 68 66 	ldmsw  \[ %g1 \+ 0x66 \], %g3
+  34:	c7 88 68 66 	ldmsw  \[ %g1 \+ 0x66 \], %g3
+  38:	c7 88 28 66 	ldmsw  \[ 0x66 \], %g3
+  3c:	c5 88 0c 01 	ldmuw  \[ %g0 \+ %g1 \], %g2
+  40:	c7 88 4c 00 	ldmuw  \[ %g1 \], %g3
+  44:	c7 88 6c 66 	ldmuw  \[ %g1 \+ 0x66 \], %g3
+  48:	c7 88 6c 66 	ldmuw  \[ %g1 \+ 0x66 \], %g3
+  4c:	c7 88 2c 66 	ldmuw  \[ 0x66 \], %g3
+  50:	c5 88 14 01 	ldmx  \[ %g0 \+ %g1 \], %g2
+  54:	c7 88 54 00 	ldmx  \[ %g1 \], %g3
+  58:	c7 88 74 66 	ldmx  \[ %g1 \+ 0x66 \], %g3
+  5c:	c7 88 74 66 	ldmx  \[ %g1 \+ 0x66 \], %g3
+  60:	c7 88 34 66 	ldmx  \[ 0x66 \], %g3
+  64:	c5 88 14 01 	ldmx  \[ %g0 \+ %g1 \], %g2
+  68:	c7 88 54 00 	ldmx  \[ %g1 \], %g3
+  6c:	c7 88 74 66 	ldmx  \[ %g1 \+ 0x66 \], %g3
+  70:	c7 88 74 66 	ldmx  \[ %g1 \+ 0x66 \], %g3
+  74:	c7 88 34 66 	ldmx  \[ 0x66 \], %g3
+  78:	c7 88 42 02 	ldmsha  \[ %g1 \+ %g2 \] %asi, %g3
+  7c:	c5 88 42 00 	ldmsha  \[ %g1 \] %asi, %g2
+  80:	c7 88 46 02 	ldmuha  \[ %g1 \+ %g2 \] %asi, %g3
+  84:	c5 88 46 00 	ldmuha  \[ %g1 \] %asi, %g2
+  88:	c7 88 4a 02 	ldmswa  \[ %g1 \+ %g2 \] %asi, %g3
+  8c:	c5 88 4a 00 	ldmswa  \[ %g1 \] %asi, %g2
+  90:	c7 88 4e 02 	ldmuwa  \[ %g1 \+ %g2 \] %asi, %g3
+  94:	c5 88 4e 00 	ldmuwa  \[ %g1 \] %asi, %g2
+  98:	c7 88 56 02 	ldmxa  \[ %g1 \+ %g2 \] %asi, %g3
+  9c:	c5 88 56 00 	ldmxa  \[ %g1 \] %asi, %g2
+  a0:	c5 a8 04 01 	stmh  %g2, \[ %g0 \+ %g1 \]
+  a4:	c7 a8 44 00 	stmh  %g3, \[ %g1 \]
+  a8:	c7 a8 64 66 	stmh  %g3, \[ %g1 \+ 0x66 \]
+  ac:	c7 a8 64 66 	stmh  %g3, \[ %g1 \+ 0x66 \]
+  b0:	c7 a8 24 66 	stmh  %g3, \[ 0x66 \]
+  b4:	c5 a8 0c 01 	stmw  %g2, \[ %g0 \+ %g1 \]
+  b8:	c7 a8 4c 00 	stmw  %g3, \[ %g1 \]
+  bc:	c7 a8 6c 66 	stmw  %g3, \[ %g1 \+ 0x66 \]
+  c0:	c7 a8 6c 66 	stmw  %g3, \[ %g1 \+ 0x66 \]
+  c4:	c7 a8 2c 66 	stmw  %g3, \[ 0x66 \]
+  c8:	c5 a8 14 01 	stmx  %g2, \[ %g0 \+ %g1 \]
+  cc:	c7 a8 54 00 	stmx  %g3, \[ %g1 \]
+  d0:	c7 a8 74 66 	stmx  %g3, \[ %g1 \+ 0x66 \]
+  d4:	c7 a8 74 66 	stmx  %g3, \[ %g1 \+ 0x66 \]
+  d8:	c7 a8 34 66 	stmx  %g3, \[ 0x66 \]
+  dc:	c5 a8 06 01 	stmha  %g2, \[ %g0 \+ %g1 \] %asi
+  e0:	c7 a8 46 00 	stmha  %g3, \[ %g1 \] %asi
+  e4:	c5 a8 0e 01 	stmwa  %g2, \[ %g0 \+ %g1 \] %asi
+  e8:	c7 a8 4e 00 	stmwa  %g3, \[ %g1 \] %asi
+  ec:	c5 a8 16 01 	stmxa  %g2, \[ %g0 \+ %g1 \] %asi
+  f0:	c7 a8 56 00 	stmxa  %g3, \[ %g1 \] %asi
diff --git a/gas/testsuite/gas/sparc/ldm-stm.s b/gas/testsuite/gas/sparc/ldm-stm.s
new file mode 100644
index 0000000..09050cf
--- /dev/null
+++ b/gas/testsuite/gas/sparc/ldm-stm.s
@@ -0,0 +1,63 @@
+# Test ldm/stm/ldma/stma
+        .text
+        ldmsh	[%g0+%g1], %g2
+        ldmsh	[%g1], %g3
+        ldmsh	[%g1+102], %g3
+        ldmsh	[102+%g1], %g3
+        ldmsh	[102], %g3
+        ldmuh	[%g0+%g1], %g2
+        ldmuh	[%g1], %g3
+        ldmuh	[%g1+102], %g3
+        ldmuh	[102+%g1], %g3
+        ldmuh	[102], %g3
+        ldmsw	[%g0+%g1], %g2
+        ldmsw	[%g1], %g3
+        ldmsw	[%g1+102], %g3
+        ldmsw	[102+%g1], %g3
+        ldmsw	[102], %g3
+        ldmuw	[%g0+%g1], %g2
+        ldmuw	[%g1], %g3
+        ldmuw	[%g1+102], %g3
+        ldmuw	[102+%g1], %g3
+        ldmuw	[102], %g3
+        ldmx	[%g0+%g1], %g2
+        ldmx	[%g1], %g3
+        ldmx	[%g1+102], %g3
+        ldmx	[102+%g1], %g3
+        ldmx	[102], %g3
+        ldmux	[%g0+%g1], %g2
+        ldmux	[%g1], %g3
+        ldmux	[%g1+102], %g3
+        ldmux	[102+%g1], %g3
+        ldmux	[102], %g3
+        ldmsha	[%g1+%g2] %asi, %g3
+        ldmsha	[%g1] %asi, %g2
+        ldmuha	[%g1+%g2] %asi, %g3
+        ldmuha	[%g1] %asi, %g2
+        ldmswa	[%g1+%g2] %asi, %g3
+        ldmswa	[%g1] %asi, %g2
+        ldmuwa	[%g1+%g2] %asi, %g3
+        ldmuwa	[%g1] %asi, %g2
+        ldmxa	[%g1+%g2] %asi, %g3
+        ldmxa	[%g1] %asi, %g2
+	stmh	%g2, [%g0+%g1]
+        stmh	%g3, [%g1]
+        stmh	%g3, [%g1+102]
+        stmh	%g3, [102+%g1]
+        stmh	%g3, [102]
+        stmw	%g2, [%g0+%g1]
+        stmw	%g3, [%g1]
+        stmw	%g3, [%g1+102]
+        stmw	%g3, [102+%g1]
+        stmw	%g3, [102]
+        stmx	%g2, [%g0+%g1]
+        stmx	%g3, [%g1]
+        stmx	%g3, [%g1+102]
+        stmx	%g3, [102+%g1]
+        stmx	%g3, [102]
+        stmha	%g2, [%g0+%g1] %asi
+        stmha   %g3, [%g1] %asi
+        stmwa	%g2, [%g0+%g1] %asi
+        stmwa	%g3, [%g1] %asi
+        stmxa	%g2, [%g0+%g1] %asi
+        stmxa	%g3, [%g1] %asi
diff --git a/gas/testsuite/gas/sparc/ldmf-stmf-diag.l b/gas/testsuite/gas/sparc/ldmf-stmf-diag.l
new file mode 100644
index 0000000..a8192b7
--- /dev/null
+++ b/gas/testsuite/gas/sparc/ldmf-stmf-diag.l
@@ -0,0 +1,11 @@
+.*ldmf-stmf-diag.s: Assembler messages:
+.*ldmf-stmf-diag.s:7: Error: Illegal operands
+.*ldmf-stmf-diag.s:12: Error: Illegal operands
+.*ldmf-stmf-diag.s:3: Error: relocation overflow
+.*ldmf-stmf-diag.s:4: Error: relocation overflow
+.*ldmf-stmf-diag.s:5: Error: relocation overflow
+.*ldmf-stmf-diag.s:6: Error: relocation overflow
+.*ldmf-stmf-diag.s:8: Error: relocation overflow
+.*ldmf-stmf-diag.s:9: Error: relocation overflow
+.*ldmf-stmf-diag.s:10: Error: relocation overflow
+.*ldmf-stmf-diag.s:11: Error: relocation overflow
diff --git a/gas/testsuite/gas/sparc/ldmf-stmf-diag.s b/gas/testsuite/gas/sparc/ldmf-stmf-diag.s
new file mode 100644
index 0000000..5f7b182
--- /dev/null
+++ b/gas/testsuite/gas/sparc/ldmf-stmf-diag.s
@@ -0,0 +1,12 @@
+# Diagnostic tests for ldmf/stmf/ldmfa/stmfs
+        .text
+        ldmfs	[%g1+0x401], %f1	! Overflow in simm10 constant.
+        ldmfs   [0x401], %f1		! Likewise.
+        ldmfd	[%g1+0x401], %f2	! Likewise.
+        ldmfd	[0x401], %f2		! Likewise.
+        ldmfd	[%g1+%g2], %f1  	! Invalid frd.
+        stmfs	%f1, [%g1+0x401]	! Overflow in simm10 constant.
+        stmfs	%f1, [0x401]	        ! Likewise.
+        stmfd	%f2, [%g1+0x401]	! Likewise.
+        stmfd	%f2, [0x401]		! Likewise.
+        stmfd	%f1, [%g1+%g2]		! Invalid frd.
diff --git a/gas/testsuite/gas/sparc/ldmf-stmf.d b/gas/testsuite/gas/sparc/ldmf-stmf.d
new file mode 100644
index 0000000..70cde85
--- /dev/null
+++ b/gas/testsuite/gas/sparc/ldmf-stmf.d
@@ -0,0 +1,37 @@
+#as: -Av9m8
+#objdump: -dr
+#name: sparc LDMF/STMF/LDMFA/STMFA
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	c3 88 18 01 	ldmfs  \[ %g0 \+ %g1 \], %f1
+   4:	c3 88 58 00 	ldmfs  \[ %g1 \], %f1
+   8:	c3 88 78 66 	ldmfs  \[ %g1 \+ 0x66 \], %f1
+   c:	c3 88 78 66 	ldmfs  \[ %g1 \+ 0x66 \], %f1
+  10:	c3 88 38 66 	ldmfs  \[ 0x66 \], %f1
+  14:	c3 88 1c 01 	ldmfd  \[ %g0 \+ %g1 \], %f32
+  18:	c3 88 5c 00 	ldmfd  \[ %g1 \], %f32
+  1c:	c3 88 7c 66 	ldmfd  \[ %g1 \+ 0x66 \], %f32
+  20:	c3 88 7c 66 	ldmfd  \[ %g1 \+ 0x66 \], %f32
+  24:	c3 88 3c 66 	ldmfd  \[ 0x66 \], %f32
+  28:	c3 88 1a 01 	ldmfsa  \[ %g0 \+ %g1 \] %asi, %f1
+  2c:	c3 88 5a 00 	ldmfsa  \[ %g1 \] %asi, %f1
+  30:	c3 88 1e 01 	ldmfda  \[ %g0 \+ %g1 \] %asi, %f32
+  34:	c3 88 5e 00 	ldmfda  \[ %g1 \] %asi, %f32
+  38:	c3 a8 18 01 	stmfs  %f1, \[ %g0 \+ %g1 \]
+  3c:	c3 a8 58 00 	stmfs  %f1, \[ %g1 \]
+  40:	c3 a8 78 66 	stmfs  %f1, \[ %g1 \+ 0x66 \]
+  44:	c3 a8 78 66 	stmfs  %f1, \[ %g1 \+ 0x66 \]
+  48:	c3 a8 38 66 	stmfs  %f1, \[ 0x66 \]
+  4c:	c3 a8 1c 01 	stmfd  %f32, \[ %g0 \+ %g1 \]
+  50:	c3 a8 5c 00 	stmfd  %f32, \[ %g1 \]
+  54:	c3 a8 7c 66 	stmfd  %f32, \[ %g1 \+ 0x66 \]
+  58:	c3 a8 7c 66 	stmfd  %f32, \[ %g1 \+ 0x66 \]
+  5c:	c3 a8 3c 66 	stmfd  %f32, \[ 0x66 \]
+  60:	c3 a8 1a 01 	stmfsa  %f1, \[ %g0 \+ %g1 \] %asi
+  64:	c3 a8 5a 00 	stmfsa  %f1, \[ %g1 \] %asi
+  68:	c3 a8 1e 01 	stmfda  %f32, \[ %g0 \+ %g1 \] %asi
+  6c:	c3 a8 5e 00 	stmfda  %f32, \[ %g1 \] %asi
diff --git a/gas/testsuite/gas/sparc/ldmf-stmf.s b/gas/testsuite/gas/sparc/ldmf-stmf.s
new file mode 100644
index 0000000..37e5024
--- /dev/null
+++ b/gas/testsuite/gas/sparc/ldmf-stmf.s
@@ -0,0 +1,31 @@
+# Test ldmf/stmf/ldmfa/stmfa
+        .text
+        ldmfs	[%g0+%g1], %f1
+        ldmfs	[%g1],	%f1
+        ldmfs	[%g1+102], %f1
+        ldmfs	[102+%g1], %f1
+        ldmfs	[102], %f1
+        ldmfd	[%g0+%g1], %f32
+        ldmfd	[%g1],	%f32
+        ldmfd	[%g1+102], %f32
+        ldmfd	[102+%g1], %f32
+        ldmfd	[102], %f32
+        ldmfsa	[%g0+%g1] %asi, %f1
+        ldmfsa	[%g1] %asi, %f1
+        ldmfda	[%g0+%g1] %asi, %f32
+        ldmfda	[%g1] %asi, %f32
+        stmfs	%f1, [%g0+%g1]
+        stmfs	%f1, [%g1]
+        stmfs	%f1, [%g1+102]
+        stmfs	%f1, [102+%g1]
+        stmfs	%f1, [102]
+        stmfd	%f32, [%g0+%g1]
+        stmfd	%f32, [%g1]
+        stmfd	%f32, [%g1+102]
+        stmfd	%f32, [102+%g1]
+        stmfd	%f32, [102]
+        stmfsa	%f1, [%g0+%g1] %asi
+        stmfsa	%f1, [%g1] %asi
+        stmfda	%f32, [%g0+%g1] %asi
+        stmfda	%f32, [%g1] %asi
+
diff --git a/gas/testsuite/gas/sparc/on-diag.l b/gas/testsuite/gas/sparc/on-diag.l
new file mode 100644
index 0000000..67e7813
--- /dev/null
+++ b/gas/testsuite/gas/sparc/on-diag.l
@@ -0,0 +1,5 @@
+.*on-diag.s: Assembler messages:
+.*on-diag.s:3: Error: Illegal operands
+.*on-diag.s:4: Error: Illegal operands
+.*on-diag.s:5: Error: Illegal operands
+.*on-diag.s:6: Error: Illegal operands
diff --git a/gas/testsuite/gas/sparc/on-diag.s b/gas/testsuite/gas/sparc/on-diag.s
new file mode 100644
index 0000000..4d2bc68
--- /dev/null
+++ b/gas/testsuite/gas/sparc/on-diag.s
@@ -0,0 +1,6 @@
+# Diagnostic tests for ON instructions
+        .text
+        onadd	%f1, %f8, %f16		! Invalid frs1
+        onsub	%f8, %f17, %f24 	! Invalid frs2
+        onmul	%f32, %f24, %f17 	! Invalid frd
+        ondiv	%f32, %f24, %f1		! Likewise.
diff --git a/gas/testsuite/gas/sparc/on.d b/gas/testsuite/gas/sparc/on.d
new file mode 100644
index 0000000..6638ded
--- /dev/null
+++ b/gas/testsuite/gas/sparc/on.d
@@ -0,0 +1,13 @@
+#as: -Av9m8
+#objdump: -dr
+#name: OSA2017 ONADD/ONSUB/ONMUL/ONDIV instructions.
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	a1 b0 02 a8 	onadd  %f0, %f8, %f16
+   4:	b5 b2 02 b0 	onsub  %f8, %f16, %f24
+   8:	a9 b0 42 b8 	onmul  %f32, %f24, %f16
+   c:	9d b2 02 a0 	ondiv  %f8, %f0, %f8
diff --git a/gas/testsuite/gas/sparc/on.s b/gas/testsuite/gas/sparc/on.s
new file mode 100644
index 0000000..6bfeac1
--- /dev/null
+++ b/gas/testsuite/gas/sparc/on.s
@@ -0,0 +1,6 @@
+# Test onadd/onsub/onmul/ondiv
+        .text
+        onadd	%f0, %f8, %f16
+        onsub	%f8, %f16, %f24
+        onmul	%f32, %f24, %f16
+        ondiv	%f8, %f0, %f8
diff --git a/gas/testsuite/gas/sparc/rdasr.d b/gas/testsuite/gas/sparc/rdasr.d
index 6acd9c8..19d3e32 100644
--- a/gas/testsuite/gas/sparc/rdasr.d
+++ b/gas/testsuite/gas/sparc/rdasr.d
@@ -1,4 +1,4 @@
-#as: -64 -Av9m
+#as: -64 -Av9m8
 #objdump: -dr
 #name: sparc64 rdasr
 
@@ -16,3 +16,4 @@ Disassembly of section .text:
   18:	8b 46 00 00 	rd  %stick, %g5
   1c:	89 46 40 00 	rd  %stick_cmpr, %g4
   20:	8d 46 80 00 	rd  %cfr, %g6
+  24:	85 43 40 00 	rd  %entropy, %g2
diff --git a/gas/testsuite/gas/sparc/rdasr.s b/gas/testsuite/gas/sparc/rdasr.s
index 8499764..b5fd873 100644
--- a/gas/testsuite/gas/sparc/rdasr.s
+++ b/gas/testsuite/gas/sparc/rdasr.s
@@ -9,3 +9,4 @@
 	rd %sys_tick,%g5
 	rd %sys_tick_cmpr,%g4
 	rd %cfr,%g6
+	rd %entropy,%g2
diff --git a/gas/testsuite/gas/sparc/rle.d b/gas/testsuite/gas/sparc/rle.d
new file mode 100644
index 0000000..b6e3f33
--- /dev/null
+++ b/gas/testsuite/gas/sparc/rle.d
@@ -0,0 +1,12 @@
+#as: -Av9m8
+#objdump: -dr
+#name: OSA2017 RLE instructions
+
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	87 b0 46 02 	rle_burst  %g1, %g2, %g3
+   4:	85 b0 06 41 	rle_length  %g1, %g2
diff --git a/gas/testsuite/gas/sparc/rle.s b/gas/testsuite/gas/sparc/rle.s
new file mode 100644
index 0000000..4d30f0e
--- /dev/null
+++ b/gas/testsuite/gas/sparc/rle.s
@@ -0,0 +1,4 @@
+# OSA2017 RLE instructions
+        .text
+        rle_burst	%g1, %g2, %g3
+        rle_length	%g1, %g2
diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp
index f65fb24..23983bc 100644
--- a/gas/testsuite/gas/sparc/sparc.exp
+++ b/gas/testsuite/gas/sparc/sparc.exp
@@ -73,6 +73,17 @@ if [istarget sparc*-*-*] {
         run_dump_test "imm-plus-rreg"
         run_dump_test "dcti-couples-v9"
         run_dump_test "call-relax"
+        run_dump_test "sparc6"
+        run_list_test "sparc6-diag" "-64"
+        run_dump_test "fpcmpshl"
+        run_list_test "fpcmpshl-diag" "-64"
+        run_dump_test "ldm-stm"
+        run_list_test "ldm-stm-diag" "-64"
+        run_dump_test "ldmf-stmf"
+        run_list_test "ldmf-stmf-diag" "-64"
+        run_dump_test "on"
+        run_list_test "on-diag" "-64"
+        run_dump_test "rle"
     } else {
         # The next tests are a.out only.
         run_dump_test "call-relax-aout"
diff --git a/gas/testsuite/gas/sparc/sparc6-diag.l b/gas/testsuite/gas/sparc/sparc6-diag.l
new file mode 100644
index 0000000..4a17196
--- /dev/null
+++ b/gas/testsuite/gas/sparc/sparc6-diag.l
@@ -0,0 +1,7 @@
+.*sparc6-diag.s: Assembler messages:
+.*sparc6-diag.s:4: Error: Illegal operands
+.*sparc6-diag.s:5: Error: Illegal operands
+.*sparc6-diag.s:6: Error: Illegal operands
+.*sparc6-diag.s:7: Error: Illegal operands
+.*sparc6-diag.s:8: Error: Illegal operands
+.*sparc6-diag.s:3: Error: relocation overflow
diff --git a/gas/testsuite/gas/sparc/sparc6-diag.s b/gas/testsuite/gas/sparc/sparc6-diag.s
new file mode 100644
index 0000000..752c545
--- /dev/null
+++ b/gas/testsuite/gas/sparc/sparc6-diag.s
@@ -0,0 +1,8 @@
+# Test error detection and reporting in SPARC6 instructions.
+        .text
+        dictunpack	%f32, 100, %f34 ! Too big immediate.
+        dictunpack	%f1, 10, %f32	! rs1 is not a double fp-register
+        dictunpack	%32, 10, %f5	! rd is not a double fp-register
+	fpsll64x	%f31, %f34, %f36 ! rs1 is not a double fp-register
+        fpsra64x	%f32, %f33, %f36 ! rs2 is not a double fp-register
+        fpsrl64x	%f32, %f34, %f1	 ! rd is not a double fp-register
diff --git a/gas/testsuite/gas/sparc/sparc6.d b/gas/testsuite/gas/sparc/sparc6.d
new file mode 100644
index 0000000..540ccca
--- /dev/null
+++ b/gas/testsuite/gas/sparc/sparc6.d
@@ -0,0 +1,18 @@
+#as: -Av9m8
+#objdump: -dr
+#name: SPARC6
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	87 b0 43 8a 	dictunpack  %f32, 0xa, %f34
+   4:	8b b0 60 c3 	fpsll64x  %f32, %f34, %f36
+   8:	97 b1 e1 e9 	fpsra64x  %f38, %f40, %f42
+   c:	a7 b3 60 f1 	fpsrl64x  %f44, %f48, %f50
+  10:	85 b0 43 c0 	revbitsb  %g1, %g2
+  14:	89 b0 c3 c1 	revbytesh  %g3, %g4
+  18:	8d b1 43 c2 	revbytesw  %g5, %g6
+  1c:	89 b0 83 c3 	revbytesx  %g2, %g4
+  20:	81 b0 28 80 	sha3 
diff --git a/gas/testsuite/gas/sparc/sparc6.s b/gas/testsuite/gas/sparc/sparc6.s
new file mode 100644
index 0000000..a7ab436
--- /dev/null
+++ b/gas/testsuite/gas/sparc/sparc6.s
@@ -0,0 +1,11 @@
+# Test SPARC6 instructions
+        .text
+        dictunpack	%f32, 10, %f34
+	fpsll64x	%f32, %f34, %f36
+        fpsra64x	%f38, %f40, %f42
+        fpsrl64x	%f44, %f48, %f50
+        revbitsb	%g1, %g2
+        revbytesh	%g3, %g4
+        revbytesw	%g5, %g6
+        revbytesx	%g2, %g4
+        sha3