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| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2016-03-15 22:01:34 +0000 |
|---|---|---|
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2016-03-21 16:44:50 +0000 |
| commit | e23e8ebee364b79556ec05075532da20b317c100 (patch) | |
| tree | 3bd8c54e74807f0087043515a4fb481f23de94e3 /gas | |
| parent | 1ae8ab4714eaab3d98fd906cfd6a5fedc469643a (diff) | |
| download | gdb-e23e8ebee364b79556ec05075532da20b317c100.zip gdb-e23e8ebee364b79556ec05075532da20b317c100.tar.gz gdb-e23e8ebee364b79556ec05075532da20b317c100.tar.bz2 | |
arc/nps400: Add first nps400 instructions
Adds the first few nps400 instructions.
gas/ChangeLog:
* testsuite/gas/arc/nps400-0.d: New file.
* testsuite/gas/arc/nps400-0.s: New file.
* testsuite/gas/arc/nps400-1.d: New file.
* testsuite/gas/arc/nps400-1.s: New file.
include/ChangeLog:
* opcodes/arc.h (insn_class_t): Add BITOP type.
opcodes/ChangeLog:
* arc-nps400-tbl.h: New file.
* arc-opc.c: Add top level comment.
(insert_nps_3bit_dst): New function.
(extract_nps_3bit_dst): New function.
(insert_nps_3bit_src2): New function.
(extract_nps_3bit_src2): New function.
(insert_nps_bitop_size): New function.
(extract_nps_bitop_size): New function.
(arc_flag_operands): Add nps400 entries.
(arc_flag_classes): Add nps400 entries.
(arc_operands): Add nps400 entries.
(arc_opcodes): Add nps400 include.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/arc/nps400-0.d | 15 | ||||
| -rw-r--r-- | gas/testsuite/gas/arc/nps400-0.s | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/arc/nps400-1.d | 18 | ||||
| -rw-r--r-- | gas/testsuite/gas/arc/nps400-1.s | 12 |
5 files changed, 54 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index ff3c35e4..25c0ee6 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,12 @@ 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> + * testsuite/gas/arc/nps400-0.d: New file. + * testsuite/gas/arc/nps400-0.s: New file. + * testsuite/gas/arc/nps400-1.d: New file. + * testsuite/gas/arc/nps400-1.s: New file. + +2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> + * config/tc-arc.c (find_opcode_match): Move lnflg, and i declarations to start of block. Reset code on all flags before attempting to match them. Handle multiple hits on the same flag. diff --git a/gas/testsuite/gas/arc/nps400-0.d b/gas/testsuite/gas/arc/nps400-0.d new file mode 100644 index 0000000..a34a4d5 --- /dev/null +++ b/gas/testsuite/gas/arc/nps400-0.d @@ -0,0 +1,15 @@ +#as: -mcpu=nps400 +#readelf: -h + +#... + Class: ELF32 + Data: 2's complement, .* endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: REL \(Relocatable file\) + Machine: ARCompact + Version: 0x1 +#... + Flags: 0x307, NPS400, v3 no-legacy-syscalls ABI +#...
\ No newline at end of file diff --git a/gas/testsuite/gas/arc/nps400-0.s b/gas/testsuite/gas/arc/nps400-0.s new file mode 100644 index 0000000..2b6cc1d --- /dev/null +++ b/gas/testsuite/gas/arc/nps400-0.s @@ -0,0 +1,2 @@ + .text + nop diff --git a/gas/testsuite/gas/arc/nps400-1.d b/gas/testsuite/gas/arc/nps400-1.d new file mode 100644 index 0000000..294356a --- /dev/null +++ b/gas/testsuite/gas/arc/nps400-1.d @@ -0,0 +1,18 @@ +#as: -mcpu=nps400 +#objdump: -dr + +.*: +file format .*arc.* + +Disassembly of section .text: + +[0-9a-f]+ <.*>: + 0: 4821 1485 movb r0,r0,r1,0x4,0x5,0x6 + 4: 4881 1485 movb r0,r0,r12,0x4,0x5,0x6 + 8: 4f81 1485 movb r15,r15,r12,0x4,0x5,0x6 + c: 4821 9485 movb.cl r0,r1,0x4,0x5,0x6 + 10: 48c1 9485 movb.cl r0,r14,0x4,0x5,0x6 + 14: 4d21 9485 movb.cl r13,r1,0x4,0x5,0x6 + 18: 4808 04d2 movh r0,r0,0x4d2 + 1c: 4868 ffff movh r3,r3,0xffff + 20: 4818 04d2 movh.cl r0,0x4d2 + 24: 4878 ffff movh.cl r3,0xffff diff --git a/gas/testsuite/gas/arc/nps400-1.s b/gas/testsuite/gas/arc/nps400-1.s new file mode 100644 index 0000000..34d43d0 --- /dev/null +++ b/gas/testsuite/gas/arc/nps400-1.s @@ -0,0 +1,12 @@ + .text + movb r0, r0, r1, 4, 5, 6 + movb r0, r0, r12, 4, 5, 6 + movb r15, r15, r12, 4, 5, 6 + movb.cl r0, r1, 4, 5, 6 + movb.cl r0, r14, 4, 5, 6 + movb.cl r13, r1, 4, 5, 6 + + movh r0, r0, 1234 + movh r3, r3, 0xffff + movh.cl r0, 1234 + movh.cl r3, 0xffff |