[AArch64] Add ARMv8.3 javascript floating-point conversion instruction

Add support for ARMv8.3 FJCVTZS floating-point conversion
instruction.

For details about javascript floating-point conversion see
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions

opcodes/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
	(QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

gas/
2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* testsuite/gas/aarch64/fp-armv8_3.s: Add fjcvtzs test.
	* testsuite/gas/aarch64/fp-armv8_3.d: Likewise.
	* testsuite/gas/aarch64/illegal-fjcvtzs.s: Likewise.
	* testsuite/gas/aarch64/illegal-fjcvtzs.d: Likewise.
	* testsuite/gas/aarch64/illegal-fjcvtzs.l: Likewise.
	* testsuite/gas/aarch64/illegal-nofp-armv8_3.s: Likewise.
	* testsuite/gas/aarch64/illegal-nofp-armv8_3.d: Likewise.
	* testsuite/gas/aarch64/illegal-nofp-armv8_3.l: Likewise.

9 files changed, 61 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 4cdfea5..7aafe4e 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,16 @@
 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 
+	* testsuite/gas/aarch64/fp-armv8_3.s: Add fjcvtzs test.
+	* testsuite/gas/aarch64/fp-armv8_3.d: Likewise.
+	* testsuite/gas/aarch64/illegal-fjcvtzs.s: Likewise.
+	* testsuite/gas/aarch64/illegal-fjcvtzs.d: Likewise.
+	* testsuite/gas/aarch64/illegal-fjcvtzs.l: Likewise.
+	* testsuite/gas/aarch64/illegal-nofp-armv8_3.s: Likewise.
+	* testsuite/gas/aarch64/illegal-nofp-armv8_3.d: Likewise.
+	* testsuite/gas/aarch64/illegal-nofp-armv8_3.l: Likewise.
+
+2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
 	* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_ADDR_SIMM10.
 	(fix_insn): Likewise.
 	(warn_unpredictable_ldst): Handle ldst_imm10.
diff --git a/gas/testsuite/gas/aarch64/fp-armv8_3.d b/gas/testsuite/gas/aarch64/fp-armv8_3.d
new file mode 100644
index 0000000..9be6fca
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp-armv8_3.d
@@ -0,0 +1,10 @@
+#objdump: -dr
+#as: -march=armv8.3-a
+
+.*:     file .*
+
+Disassembly of section \.text:
+
+0000000000000000 <.*>:
+   0:	1e7e0041 	fjcvtzs	w1, d2
+   4:	1e7e00e7 	fjcvtzs	w7, d7
diff --git a/gas/testsuite/gas/aarch64/fp-armv8_3.s b/gas/testsuite/gas/aarch64/fp-armv8_3.s
new file mode 100644
index 0000000..15db3d1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp-armv8_3.s
@@ -0,0 +1,5 @@
+	/* ARMv8.3 Javascript conversion instruction.  */
+	.text
+
+	fjcvtzs w1, d2
+	fjcvtzs w7, d7
diff --git a/gas/testsuite/gas/aarch64/illegal-fjcvtzs.d b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.d
new file mode 100644
index 0000000..000904b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.d
@@ -0,0 +1,2 @@
+#as: -march=armv8.3-a -mno-verbose-error
+#error-output: illegal-fjcvtzs.l
diff --git a/gas/testsuite/gas/aarch64/illegal-fjcvtzs.l b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.l
new file mode 100644
index 0000000..7a38ddc
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.l
@@ -0,0 +1,8 @@
+[^:]+: Assembler messages:
+[^:]+:8: Error: operand 1 must be an integer register -- `fjcvtzs d0,d1'
+[^:]+:9: Error: operand 1 must be an integer register -- `fjcvtzs s0,d1'
+[^:]+:10: Error: operand mismatch -- `fjcvtzs x0,d1'
+[^:]+:11: Error: operand mismatch -- `fjcvtzs w0,s1'
+[^:]+:12: Error: operand mismatch -- `fjcvtzs w0,h1'
+[^:]+:13: Error: operand mismatch -- `fjcvtzs w0,q1'
+[^:]+:14: Error: operand 2 must be a floating-point register -- `fjcvtzs w0,x1'
diff --git a/gas/testsuite/gas/aarch64/illegal-fjcvtzs.s b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.s
new file mode 100644
index 0000000..74f6e3c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.s
@@ -0,0 +1,14 @@
+// Test illegal ARMv8.3 FJCVTZS instructions
+.text
+
+	// Good.
+	fjcvtzs w0, d1
+
+	// Bad.
+	fjcvtzs d0, d1
+	fjcvtzs s0, d1
+	fjcvtzs x0, d1
+	fjcvtzs w0, s1
+	fjcvtzs w0, h1
+	fjcvtzs w0, q1
+	fjcvtzs w0, x1
diff --git a/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.d b/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.d
new file mode 100644
index 0000000..89e0e89
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.d
@@ -0,0 +1,2 @@
+#as: -march=armv8.3-a+nofp -mno-verbose-error
+#error-output: illegal-nofp-armv8_3.l
diff --git a/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.l b/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.l
new file mode 100644
index 0000000..41d7fcc
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.l
@@ -0,0 +1,3 @@
+[^:]*: Assembler messages:
+[^:]+:4: Error: selected processor does not support `fneg s0,s1'
+[^:]+:6: Error: selected processor does not support `fjcvtzs w0,d1'
diff --git a/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.s b/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.s
new file mode 100644
index 0000000..549d89d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-nofp-armv8_3.s
@@ -0,0 +1,6 @@
+// Test -march=armv8.3-a+nofp to disable fp-dependent ARMv8.3 instructions.
+.text
+	neg w0, w1
+	fneg s0, s1
+	pacia x0, x1
+	fjcvtzs w0, d1