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authorNick Clifton <nickc@redhat.com>2001-06-19 11:57:29 +0000
committerNick Clifton <nickc@redhat.com>2001-06-19 11:57:29 +0000
commitc45021f2d2dffbe6b87f7d9f0ce5d0cc9038a37c (patch)
tree91b942fd35d48e36535b99d03341910a386a33dd /gas
parent1107dce2cdc0b2601ada908a2e2adc25d0dab4b2 (diff)
downloadgdb-c45021f2d2dffbe6b87f7d9f0ce5d0cc9038a37c.zip
gdb-c45021f2d2dffbe6b87f7d9f0ce5d0cc9038a37c.tar.gz
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Remove auot generated man pages
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog8
-rw-r--r--gas/Makefile.am6
-rw-r--r--gas/Makefile.in8
-rw-r--r--gas/config/tc-arm.c8897
-rw-r--r--gas/doc/Makefile.am15
-rw-r--r--gas/doc/Makefile.in16
-rw-r--r--gas/doc/as.1724
-rw-r--r--gas/po/POTFILES.in2
-rw-r--r--gas/po/gas.pot1929
9 files changed, 1006 insertions, 10599 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index f7365a8..a9a0332 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2001-06-18 H.J. Lu <hjl@gnu.org>
+
+ * doc/Makefile.am (info): Depend on $(MANS).
+ (as.1): Remove the prefix `$(srcdir)/'.
+ * doc/Makefile.in: Regenerated.
+
+ * as.1: Removed.
+
2001-06-18 Philip Blundell <philb@gnu.org>
* config/tc-arm.c (do_msr): Remove restriction on usage of
diff --git a/gas/Makefile.am b/gas/Makefile.am
index 52a19a6..499e9ef 100644
--- a/gas/Makefile.am
+++ b/gas/Makefile.am
@@ -435,10 +435,8 @@ stamp-mk.com: vmsconf.sh Makefile
$(SHELL) $(srcdir)/../move-if-change new-make.com $(srcdir)/make-gas.com
touch stamp-mk.com
-EXTRA_DIST = make-gas.com
-
-DISTSTUFF = make-gas.com m68k-parse.c itbl-parse.c itbl-parse.h itbl-lex.c
-diststuff: $(DISTSTUFF) info
+EXTRA_DIST = make-gas.com m68k-parse.c itbl-parse.c itbl-parse.h itbl-lex.c
+diststuff: $(EXTRA_DIST) info
DISTCLEANFILES = targ-cpu.h obj-format.h targ-env.h itbl-cpu.h cgen-desc.h
diff --git a/gas/Makefile.in b/gas/Makefile.in
index 1de6c50..bcce02f 100644
--- a/gas/Makefile.in
+++ b/gas/Makefile.in
@@ -552,9 +552,7 @@ noinst_PROGRAMS = as-new gasp-new
noinst_SCRIPTS = $(GDBINIT)
EXTRA_SCRIPTS = .gdbinit
-EXTRA_DIST = make-gas.com
-
-DISTSTUFF = make-gas.com m68k-parse.c itbl-parse.c itbl-parse.h itbl-lex.c
+EXTRA_DIST = make-gas.com m68k-parse.c itbl-parse.c itbl-parse.h itbl-lex.c
DISTCLEANFILES = targ-cpu.h obj-format.h targ-env.h itbl-cpu.h cgen-desc.h
@@ -2008,7 +2006,7 @@ configure configure.in gdbinit.in itbl-lex.c itbl-parse.c
DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
-TAR = tar
+TAR = gtar
GZIP_ENV = --best
SOURCES = $(itbl_test_SOURCES) $(as_new_SOURCES) $(EXTRA_as_new_SOURCES) $(gasp_new_SOURCES)
OBJECTS = $(itbl_test_OBJECTS) $(as_new_OBJECTS) $(gasp_new_OBJECTS)
@@ -2407,7 +2405,7 @@ stamp-mk.com: vmsconf.sh Makefile
sh $(srcdir)/vmsconf.sh $(GENERIC_OBJS) > new-make.com
$(SHELL) $(srcdir)/../move-if-change new-make.com $(srcdir)/make-gas.com
touch stamp-mk.com
-diststuff: $(DISTSTUFF) info
+diststuff: $(EXTRA_DIST) info
$(OBJS): @ALL_OBJ_DEPS@
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
deleted file mode 100644
index 99aff8e..0000000
--- a/gas/config/tc-arm.c
+++ /dev/null
@@ -1,8897 +0,0 @@
-/* tc-arm.c -- Assemble for the ARM
- Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
- Free Software Foundation, Inc.
- Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
- Modified by David Taylor (dtaylor@armltd.co.uk)
-
- This file is part of GAS, the GNU Assembler.
-
- GAS is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
- any later version.
-
- GAS is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with GAS; see the file COPYING. If not, write to the Free
- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
- 02111-1307, USA. */
-
-#include <ctype.h>
-#include <string.h>
-#define NO_RELOC 0
-#include "as.h"
-
-/* Need TARGET_CPU. */
-#include "config.h"
-#include "subsegs.h"
-#include "obstack.h"
-#include "symbols.h"
-#include "listing.h"
-
-#ifdef OBJ_ELF
-#include "elf/arm.h"
-#include "dwarf2dbg.h"
-#endif
-
-/* Types of processor to assemble for. */
-#define ARM_1 0x00000001
-#define ARM_2 0x00000002
-#define ARM_3 0x00000004
-#define ARM_250 ARM_3
-#define ARM_6 0x00000008
-#define ARM_7 ARM_6 /* Same core instruction set. */
-#define ARM_8 ARM_6 /* Same core instruction set. */
-#define ARM_9 ARM_6 /* Same core instruction set. */
-#define ARM_CPU_MASK 0x0000000f
-
-/* The following bitmasks control CPU extensions (ARM7 onwards): */
-#define ARM_EXT_LONGMUL 0x00000010 /* Allow long multiplies. */
-#define ARM_EXT_HALFWORD 0x00000020 /* Allow half word loads. */
-#define ARM_EXT_THUMB 0x00000040 /* Allow BX instruction. */
-#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
-#define ARM_EXT_V5E 0x00000100 /* "El Segundo". */
-#define ARM_EXT_XSCALE 0x00000200 /* Allow MIA etc. */
-
-/* Architectures are the sum of the base and extensions. */
-#define ARM_ARCH_V3M ARM_EXT_LONGMUL
-#define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_HALFWORD)
-#define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_THUMB)
-#define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
-#define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_THUMB)
-#define ARM_ARCH_V5TE (ARM_ARCH_V5T | ARM_EXT_V5E)
-#define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_EXT_XSCALE)
-
-/* Some useful combinations: */
-#define ARM_ANY 0x00ffffff
-#define ARM_2UP (ARM_ANY - ARM_1)
-#define ARM_ALL ARM_2UP /* Not arm1 only. */
-#define ARM_3UP 0x00fffffc
-#define ARM_6UP 0x00fffff8 /* Includes ARM7. */
-
-#define FPU_CORE 0x80000000
-#define FPU_FPA10 0x40000000
-#define FPU_FPA11 0x40000000
-#define FPU_NONE 0
-
-/* Some useful combinations. */
-#define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY. */
-#define FPU_MEMMULTI 0x7f000000 /* Not fpu_core. */
-
-#ifndef CPU_DEFAULT
-#if defined __XSCALE__
-#define CPU_DEFAULT (ARM_9 | ARM_ARCH_XSCALE)
-#else
-#if defined __thumb__
-#define CPU_DEFAULT (ARM_7 | ARM_ARCH_V4T)
-#else
-#define CPU_DEFAULT ARM_ALL
-#endif
-#endif
-#endif
-
-#ifndef FPU_DEFAULT
-#define FPU_DEFAULT FPU_ALL
-#endif
-
-#define streq(a, b) (strcmp (a, b) == 0)
-#define skip_whitespace(str) while (*(str) == ' ') ++(str)
-
-static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
-static int target_oabi = 0;
-
-#if defined OBJ_COFF || defined OBJ_ELF
-/* Flags stored in private area of BFD structure. */
-static boolean uses_apcs_26 = false;
-static boolean atpcs = false;
-static boolean support_interwork = false;
-static boolean uses_apcs_float = false;
-static boolean pic_code = false;
-#endif
-
-/* This array holds the chars that always start a comment. If the
- pre-processor is disabled, these aren't very useful. */
-CONST char comment_chars[] = "@";
-
-/* This array holds the chars that only start a comment at the beginning of
- a line. If the line seems to have the form '# 123 filename'
- .line and .file directives will appear in the pre-processed output. */
-/* Note that input_file.c hand checks for '#' at the beginning of the
- first line of the input file. This is because the compiler outputs
- #NO_APP at the beginning of its output. */
-/* Also note that comments like this one will always work. */
-CONST char line_comment_chars[] = "#";
-
-CONST char line_separator_chars[] = ";";
-
-/* Chars that can be used to separate mant
- from exp in floating point numbers. */
-CONST char EXP_CHARS[] = "eE";
-
-/* Chars that mean this number is a floating point constant. */
-/* As in 0f12.456 */
-/* or 0d1.2345e12 */
-
-CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
-
-/* Prefix characters that indicate the start of an immediate
- value. */
-#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
-
-#ifdef OBJ_ELF
-/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
-symbolS * GOT_symbol;
-#endif
-
-/* Size of relocation record. */
-CONST int md_reloc_size = 8;
-
-/* 0: assemble for ARM,
- 1: assemble for Thumb,
- 2: assemble for Thumb even though target CPU does not support thumb
- instructions. */
-static int thumb_mode = 0;
-
-typedef struct arm_fix
-{
- int thumb_mode;
-} arm_fix_data;
-
-struct arm_it
-{
- CONST char * error;
- unsigned long instruction;
- int suffix;
- int size;
- struct
- {
- bfd_reloc_code_real_type type;
- expressionS exp;
- int pc_rel;
- } reloc;
-};
-
-struct arm_it inst;
-
-enum asm_shift_index
-{
- SHIFT_LSL = 0,
- SHIFT_LSR,
- SHIFT_ASR,
- SHIFT_ROR,
- SHIFT_RRX
-};
-
-struct asm_shift_properties
-{
- enum asm_shift_index index;
- unsigned long bit_field;
- unsigned int allows_0 : 1;
- unsigned int allows_32 : 1;
-};
-
-static const struct asm_shift_properties shift_properties [] =
-{
- { SHIFT_LSL, 0, 1, 0},
- { SHIFT_LSR, 0x20, 0, 1},
- { SHIFT_ASR, 0x40, 0, 1},
- { SHIFT_ROR, 0x60, 0, 0},
- { SHIFT_RRX, 0x60, 0, 0}
-};
-
-struct asm_shift_name
-{
- const char * name;
- const struct asm_shift_properties * properties;
-};
-
-static const struct asm_shift_name shift_names [] =
-{
- { "asl", shift_properties + SHIFT_LSL },
- { "lsl", shift_properties + SHIFT_LSL },
- { "lsr", shift_properties + SHIFT_LSR },
- { "asr", shift_properties + SHIFT_ASR },
- { "ror", shift_properties + SHIFT_ROR },
- { "rrx", shift_properties + SHIFT_RRX },
- { "ASL", shift_properties + SHIFT_LSL },
- { "LSL", shift_properties + SHIFT_LSL },
- { "LSR", shift_properties + SHIFT_LSR },
- { "ASR", shift_properties + SHIFT_ASR },
- { "ROR", shift_properties + SHIFT_ROR },
- { "RRX", shift_properties + SHIFT_RRX }
-};
-
-#define NO_SHIFT_RESTRICT 1
-#define SHIFT_RESTRICT 0
-
-#define NUM_FLOAT_VALS 8
-
-CONST char * fp_const[] =
-{
- "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
-};
-
-/* Number of littlenums required to hold an extended precision number. */
-#define MAX_LITTLENUMS 6
-
-LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
-
-#define FAIL (-1)
-#define SUCCESS (0)
-
-#define SUFF_S 1
-#define SUFF_D 2
-#define SUFF_E 3
-#define SUFF_P 4
-
-#define CP_T_X 0x00008000
-#define CP_T_Y 0x00400000
-#define CP_T_Pre 0x01000000
-#define CP_T_UD 0x00800000
-#define CP_T_WB 0x00200000
-
-#define CONDS_BIT 0x00100000
-#define LOAD_BIT 0x00100000
-#define TRANS_BIT 0x00200000
-
-#define DOUBLE_LOAD_FLAG 0x00000001
-
-struct asm_cond
-{
- CONST char * template;
- unsigned long value;
-};
-
-/* This is to save a hash look-up in the common case. */
-#define COND_ALWAYS 0xe0000000
-
-static CONST struct asm_cond conds[] =
-{
- {"eq", 0x00000000},
- {"ne", 0x10000000},
- {"cs", 0x20000000}, {"hs", 0x20000000},
- {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
- {"mi", 0x40000000},
- {"pl", 0x50000000},
- {"vs", 0x60000000},
- {"vc", 0x70000000},
- {"hi", 0x80000000},
- {"ls", 0x90000000},
- {"ge", 0xa0000000},
- {"lt", 0xb0000000},
- {"gt", 0xc0000000},
- {"le", 0xd0000000},
- {"al", 0xe0000000},
- {"nv", 0xf0000000}
-};
-
-/* Warning: If the top bit of the set_bits is set, then the standard
- instruction bitmask is ignored, and the new bitmask is taken from
- the set_bits: */
-struct asm_flg
-{
- CONST char * template; /* Basic flag string. */
- unsigned long set_bits; /* Bits to set. */
-};
-
-static CONST struct asm_flg s_flag[] =
-{
- {"s", CONDS_BIT},
- {NULL, 0}
-};
-
-static CONST struct asm_flg ldr_flags[] =
-{
- {"d", DOUBLE_LOAD_FLAG},
- {"b", 0x00400000},
- {"t", TRANS_BIT},
- {"bt", 0x00400000 | TRANS_BIT},
- {"h", 0x801000b0},
- {"sh", 0x801000f0},
- {"sb", 0x801000d0},
- {NULL, 0}
-};
-
-static CONST struct asm_flg str_flags[] =
-{
- {"d", DOUBLE_LOAD_FLAG},
- {"b", 0x00400000},
- {"t", TRANS_BIT},
- {"bt", 0x00400000 | TRANS_BIT},
- {"h", 0x800000b0},
- {NULL, 0}
-};
-
-static CONST struct asm_flg byte_flag[] =
-{
- {"b", 0x00400000},
- {NULL, 0}
-};
-
-static CONST struct asm_flg cmp_flags[] =
-{
- {"s", CONDS_BIT},
- {"p", 0x0010f000},
- {NULL, 0}
-};
-
-static CONST struct asm_flg ldm_flags[] =
-{
- {"ed", 0x01800000},
- {"fd", 0x00800000},
- {"ea", 0x01000000},
- {"fa", 0x00000000},
- {"ib", 0x01800000},
- {"ia", 0x00800000},
- {"db", 0x01000000},
- {"da", 0x00000000},
- {NULL, 0}
-};
-
-static CONST struct asm_flg stm_flags[] =
-{
- {"ed", 0x00000000},
- {"fd", 0x01000000},
- {"ea", 0x00800000},
- {"fa", 0x01800000},
- {"ib", 0x01800000},
- {"ia", 0x00800000},
- {"db", 0x01000000},
- {"da", 0x00000000},
- {NULL, 0}
-};
-
-static CONST struct asm_flg lfm_flags[] =
-{
- {"fd", 0x00800000},
- {"ea", 0x01000000},
- {NULL, 0}
-};
-
-static CONST struct asm_flg sfm_flags[] =
-{
- {"fd", 0x01000000},
- {"ea", 0x00800000},
- {NULL, 0}
-};
-
-static CONST struct asm_flg round_flags[] =
-{
- {"p", 0x00000020},
- {"m", 0x00000040},
- {"z", 0x00000060},
- {NULL, 0}
-};
-
-/* The implementation of the FIX instruction is broken on some assemblers,
- in that it accepts a precision specifier as well as a rounding specifier,
- despite the fact that this is meaningless. To be more compatible, we
- accept it as well, though of course it does not set any bits. */
-static CONST struct asm_flg fix_flags[] =
-{
- {"p", 0x00000020},
- {"m", 0x00000040},
- {"z", 0x00000060},
- {"sp", 0x00000020},
- {"sm", 0x00000040},
- {"sz", 0x00000060},
- {"dp", 0x00000020},
- {"dm", 0x00000040},
- {"dz", 0x00000060},
- {"ep", 0x00000020},
- {"em", 0x00000040},
- {"ez", 0x00000060},
- {NULL, 0}
-};
-
-static CONST struct asm_flg except_flag[] =
-{
- {"e", 0x00400000},
- {NULL, 0}
-};
-
-static CONST struct asm_flg cplong_flag[] =
-{
- {"l", 0x00400000},
- {NULL, 0}
-};
-
-struct asm_psr
-{
- CONST char * template;
- boolean cpsr;
- unsigned long field;
-};
-
-/* The bit that distnguishes CPSR and SPSR. */
-#define SPSR_BIT (1 << 22)
-
-/* How many bits to shift the PSR_xxx bits up by. */
-#define PSR_SHIFT 16
-
-#define PSR_c (1 << 0)
-#define PSR_x (1 << 1)
-#define PSR_s (1 << 2)
-#define PSR_f (1 << 3)
-
-static CONST struct asm_psr psrs[] =
-{
- {"CPSR", true, PSR_c | PSR_f},
- {"CPSR_all", true, PSR_c | PSR_f},
- {"SPSR", false, PSR_c | PSR_f},
- {"SPSR_all", false, PSR_c | PSR_f},
- {"CPSR_flg", true, PSR_f},
- {"CPSR_f", true, PSR_f},
- {"SPSR_flg", false, PSR_f},
- {"SPSR_f", false, PSR_f},
- {"CPSR_c", true, PSR_c},
- {"CPSR_ctl", true, PSR_c},
- {"SPSR_c", false, PSR_c},
- {"SPSR_ctl", false, PSR_c},
- {"CPSR_x", true, PSR_x},
- {"CPSR_s", true, PSR_s},
- {"SPSR_x", false, PSR_x},
- {"SPSR_s", false, PSR_s},
- /* Combinations of flags. */
- {"CPSR_fs", true, PSR_f | PSR_s},
- {"CPSR_fx", true, PSR_f | PSR_x},
- {"CPSR_fc", true, PSR_f | PSR_c},
- {"CPSR_sf", true, PSR_s | PSR_f},
- {"CPSR_sx", true, PSR_s | PSR_x},
- {"CPSR_sc", true, PSR_s | PSR_c},
- {"CPSR_xf", true, PSR_x | PSR_f},
- {"CPSR_xs", true, PSR_x | PSR_s},
- {"CPSR_xc", true, PSR_x | PSR_c},
- {"CPSR_cf", true, PSR_c | PSR_f},
- {"CPSR_cs", true, PSR_c | PSR_s},
- {"CPSR_cx", true, PSR_c | PSR_x},
- {"CPSR_fsx", true, PSR_f | PSR_s | PSR_x},
- {"CPSR_fsc", true, PSR_f | PSR_s | PSR_c},
- {"CPSR_fxs", true, PSR_f | PSR_x | PSR_s},
- {"CPSR_fxc", true, PSR_f | PSR_x | PSR_c},
- {"CPSR_fcs", true, PSR_f | PSR_c | PSR_s},
- {"CPSR_fcx", true, PSR_f | PSR_c | PSR_x},
- {"CPSR_sfx", true, PSR_s | PSR_f | PSR_x},
- {"CPSR_sfc", true, PSR_s | PSR_f | PSR_c},
- {"CPSR_sxf", true, PSR_s | PSR_x | PSR_f},
- {"CPSR_sxc", true, PSR_s | PSR_x | PSR_c},
- {"CPSR_scf", true, PSR_s | PSR_c | PSR_f},
- {"CPSR_scx", true, PSR_s | PSR_c | PSR_x},
- {"CPSR_xfs", true, PSR_x | PSR_f | PSR_s},
- {"CPSR_xfc", true, PSR_x | PSR_f | PSR_c},
- {"CPSR_xsf", true, PSR_x | PSR_s | PSR_f},
- {"CPSR_xsc", true, PSR_x | PSR_s | PSR_c},
- {"CPSR_xcf", true, PSR_x | PSR_c | PSR_f},
- {"CPSR_xcs", true, PSR_x | PSR_c | PSR_s},
- {"CPSR_cfs", true, PSR_c | PSR_f | PSR_s},
- {"CPSR_cfx", true, PSR_c | PSR_f | PSR_x},
- {"CPSR_csf", true, PSR_c | PSR_s | PSR_f},
- {"CPSR_csx", true, PSR_c | PSR_s | PSR_x},
- {"CPSR_cxf", true, PSR_c | PSR_x | PSR_f},
- {"CPSR_cxs", true, PSR_c | PSR_x | PSR_s},
- {"CPSR_fsxc", true, PSR_f | PSR_s | PSR_x | PSR_c},
- {"CPSR_fscx", true, PSR_f | PSR_s | PSR_c | PSR_x},
- {"CPSR_fxsc", true, PSR_f | PSR_x | PSR_s | PSR_c},
- {"CPSR_fxcs", true, PSR_f | PSR_x | PSR_c | PSR_s},
- {"CPSR_fcsx", true, PSR_f | PSR_c | PSR_s | PSR_x},
- {"CPSR_fcxs", true, PSR_f | PSR_c | PSR_x | PSR_s},
- {"CPSR_sfxc", true, PSR_s | PSR_f | PSR_x | PSR_c},
- {"CPSR_sfcx", true, PSR_s | PSR_f | PSR_c | PSR_x},
- {"CPSR_sxfc", true, PSR_s | PSR_x | PSR_f | PSR_c},
- {"CPSR_sxcf", true, PSR_s | PSR_x | PSR_c | PSR_f},
- {"CPSR_scfx", true, PSR_s | PSR_c | PSR_f | PSR_x},
- {"CPSR_scxf", true, PSR_s | PSR_c | PSR_x | PSR_f},
- {"CPSR_xfsc", true, PSR_x | PSR_f | PSR_s | PSR_c},
- {"CPSR_xfcs", true, PSR_x | PSR_f | PSR_c | PSR_s},
- {"CPSR_xsfc", true, PSR_x | PSR_s | PSR_f | PSR_c},
- {"CPSR_xscf", true, PSR_x | PSR_s | PSR_c | PSR_f},
- {"CPSR_xcfs", true, PSR_x | PSR_c | PSR_f | PSR_s},
- {"CPSR_xcsf", true, PSR_x | PSR_c | PSR_s | PSR_f},
- {"CPSR_cfsx", true, PSR_c | PSR_f | PSR_s | PSR_x},
- {"CPSR_cfxs", true, PSR_c | PSR_f | PSR_x | PSR_s},
- {"CPSR_csfx", true, PSR_c | PSR_s | PSR_f | PSR_x},
- {"CPSR_csxf", true, PSR_c | PSR_s | PSR_x | PSR_f},
- {"CPSR_cxfs", true, PSR_c | PSR_x | PSR_f | PSR_s},
- {"CPSR_cxsf", true, PSR_c | PSR_x | PSR_s | PSR_f},
- {"SPSR_fs", false, PSR_f | PSR_s},
- {"SPSR_fx", false, PSR_f | PSR_x},
- {"SPSR_fc", false, PSR_f | PSR_c},
- {"SPSR_sf", false, PSR_s | PSR_f},
- {"SPSR_sx", false, PSR_s | PSR_x},
- {"SPSR_sc", false, PSR_s | PSR_c},
- {"SPSR_xf", false, PSR_x | PSR_f},
- {"SPSR_xs", false, PSR_x | PSR_s},
- {"SPSR_xc", false, PSR_x | PSR_c},
- {"SPSR_cf", false, PSR_c | PSR_f},
- {"SPSR_cs", false, PSR_c | PSR_s},
- {"SPSR_cx", false, PSR_c | PSR_x},
- {"SPSR_fsx", false, PSR_f | PSR_s | PSR_x},
- {"SPSR_fsc", false, PSR_f | PSR_s | PSR_c},
- {"SPSR_fxs", false, PSR_f | PSR_x | PSR_s},
- {"SPSR_fxc", false, PSR_f | PSR_x | PSR_c},
- {"SPSR_fcs", false, PSR_f | PSR_c | PSR_s},
- {"SPSR_fcx", false, PSR_f | PSR_c | PSR_x},
- {"SPSR_sfx", false, PSR_s | PSR_f | PSR_x},
- {"SPSR_sfc", false, PSR_s | PSR_f | PSR_c},
- {"SPSR_sxf", false, PSR_s | PSR_x | PSR_f},
- {"SPSR_sxc", false, PSR_s | PSR_x | PSR_c},
- {"SPSR_scf", false, PSR_s | PSR_c | PSR_f},
- {"SPSR_scx", false, PSR_s | PSR_c | PSR_x},
- {"SPSR_xfs", false, PSR_x | PSR_f | PSR_s},
- {"SPSR_xfc", false, PSR_x | PSR_f | PSR_c},
- {"SPSR_xsf", false, PSR_x | PSR_s | PSR_f},
- {"SPSR_xsc", false, PSR_x | PSR_s | PSR_c},
- {"SPSR_xcf", false, PSR_x | PSR_c | PSR_f},
- {"SPSR_xcs", false, PSR_x | PSR_c | PSR_s},
- {"SPSR_cfs", false, PSR_c | PSR_f | PSR_s},
- {"SPSR_cfx", false, PSR_c | PSR_f | PSR_x},
- {"SPSR_csf", false, PSR_c | PSR_s | PSR_f},
- {"SPSR_csx", false, PSR_c | PSR_s | PSR_x},
- {"SPSR_cxf", false, PSR_c | PSR_x | PSR_f},
- {"SPSR_cxs", false, PSR_c | PSR_x | PSR_s},
- {"SPSR_fsxc", false, PSR_f | PSR_s | PSR_x | PSR_c},
- {"SPSR_fscx", false, PSR_f | PSR_s | PSR_c | PSR_x},
- {"SPSR_fxsc", false, PSR_f | PSR_x | PSR_s | PSR_c},
- {"SPSR_fxcs", false, PSR_f | PSR_x | PSR_c | PSR_s},
- {"SPSR_fcsx", false, PSR_f | PSR_c | PSR_s | PSR_x},
- {"SPSR_fcxs", false, PSR_f | PSR_c | PSR_x | PSR_s},
- {"SPSR_sfxc", false, PSR_s | PSR_f | PSR_x | PSR_c},
- {"SPSR_sfcx", false, PSR_s | PSR_f | PSR_c | PSR_x},
- {"SPSR_sxfc", false, PSR_s | PSR_x | PSR_f | PSR_c},
- {"SPSR_sxcf", false, PSR_s | PSR_x | PSR_c | PSR_f},
- {"SPSR_scfx", false, PSR_s | PSR_c | PSR_f | PSR_x},
- {"SPSR_scxf", false, PSR_s | PSR_c | PSR_x | PSR_f},
- {"SPSR_xfsc", false, PSR_x | PSR_f | PSR_s | PSR_c},
- {"SPSR_xfcs", false, PSR_x | PSR_f | PSR_c | PSR_s},
- {"SPSR_xsfc", false, PSR_x | PSR_s | PSR_f | PSR_c},
- {"SPSR_xscf", false, PSR_x | PSR_s | PSR_c | PSR_f},
- {"SPSR_xcfs", false, PSR_x | PSR_c | PSR_f | PSR_s},
- {"SPSR_xcsf", false, PSR_x | PSR_c | PSR_s | PSR_f},
- {"SPSR_cfsx", false, PSR_c | PSR_f | PSR_s | PSR_x},
- {"SPSR_cfxs", false, PSR_c | PSR_f | PSR_x | PSR_s},
- {"SPSR_csfx", false, PSR_c | PSR_s | PSR_f | PSR_x},
- {"SPSR_csxf", false, PSR_c | PSR_s | PSR_x | PSR_f},
- {"SPSR_cxfs", false, PSR_c | PSR_x | PSR_f | PSR_s},
- {"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f},
-};
-
-/* Functions called by parser. */
-/* ARM instructions. */
-static void do_arit PARAMS ((char *, unsigned long));
-static void do_cmp PARAMS ((char *, unsigned long));
-static void do_mov PARAMS ((char *, unsigned long));
-static void do_ldst PARAMS ((char *, unsigned long));
-static void do_ldmstm PARAMS ((char *, unsigned long));
-static void do_branch PARAMS ((char *, unsigned long));
-static void do_swi PARAMS ((char *, unsigned long));
-/* Pseudo Op codes. */
-static void do_adr PARAMS ((char *, unsigned long));
-static void do_adrl PARAMS ((char *, unsigned long));
-static void do_nop PARAMS ((char *, unsigned long));
-/* ARM 2. */
-static void do_mul PARAMS ((char *, unsigned long));
-static void do_mla PARAMS ((char *, unsigned long));
-/* ARM 3. */
-static void do_swap PARAMS ((char *, unsigned long));
-/* ARM 6. */
-static void do_msr PARAMS ((char *, unsigned long));
-static void do_mrs PARAMS ((char *, unsigned long));
-/* ARM 7M. */
-static void do_mull PARAMS ((char *, unsigned long));
-/* ARM THUMB. */
-static void do_bx PARAMS ((char *, unsigned long));
-
-/* ARM_EXT_XScale. */
-static void do_mia PARAMS ((char *, unsigned long));
-static void do_mar PARAMS ((char *, unsigned long));
-static void do_mra PARAMS ((char *, unsigned long));
-static void do_pld PARAMS ((char *, unsigned long));
-static void do_ldrd PARAMS ((char *, unsigned long));
-
-/* ARM_EXT_V5. */
-static void do_blx PARAMS ((char *, unsigned long));
-static void do_bkpt PARAMS ((char *, unsigned long));
-static void do_clz PARAMS ((char *, unsigned long));
-static void do_lstc2 PARAMS ((char *, unsigned long));
-static void do_cdp2 PARAMS ((char *, unsigned long));
-static void do_co_reg2 PARAMS ((char *, unsigned long));
-
-static void do_t_blx PARAMS ((char *));
-static void do_t_bkpt PARAMS ((char *));
-
-/* ARM_EXT_V5E. */
-static void do_smla PARAMS ((char *, unsigned long));
-static void do_smlal PARAMS ((char *, unsigned long));
-static void do_smul PARAMS ((char *, unsigned long));
-static void do_qadd PARAMS ((char *, unsigned long));
-static void do_co_reg2c PARAMS ((char *, unsigned long));
-
-/* Coprocessor Instructions. */
-static void do_cdp PARAMS ((char *, unsigned long));
-static void do_lstc PARAMS ((char *, unsigned long));
-static void do_co_reg PARAMS ((char *, unsigned long));
-static void do_fp_ctrl PARAMS ((char *, unsigned long));
-static void do_fp_ldst PARAMS ((char *, unsigned long));
-static void do_fp_ldmstm PARAMS ((char *, unsigned long));
-static void do_fp_dyadic PARAMS ((char *, unsigned long));
-static void do_fp_monadic PARAMS ((char *, unsigned long));
-static void do_fp_cmp PARAMS ((char *, unsigned long));
-static void do_fp_from_reg PARAMS ((char *, unsigned long));
-static void do_fp_to_reg PARAMS ((char *, unsigned long));
-
-static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
-static int arm_reg_parse PARAMS ((char **));
-static CONST struct asm_psr * arm_psr_parse PARAMS ((char **));
-static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
-static int add_to_lit_pool PARAMS ((void));
-static unsigned validate_immediate PARAMS ((unsigned));
-static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
-static int validate_offset_imm PARAMS ((unsigned int, int));
-static void opcode_select PARAMS ((int));
-static void end_of_line PARAMS ((char *));
-static int reg_required_here PARAMS ((char **, int));
-static int psr_required_here PARAMS ((char **));
-static int co_proc_number PARAMS ((char **));
-static int cp_opc_expr PARAMS ((char **, int, int));
-static int cp_reg_required_here PARAMS ((char **, int));
-static int fp_reg_required_here PARAMS ((char **, int));
-static int cp_address_offset PARAMS ((char **));
-static int cp_address_required_here PARAMS ((char **));
-static int my_get_float_expression PARAMS ((char **));
-static int skip_past_comma PARAMS ((char **));
-static int walk_no_bignums PARAMS ((symbolS *));
-static int negate_data_op PARAMS ((unsigned long *, unsigned long));
-static int data_op2 PARAMS ((char **));
-static int fp_op2 PARAMS ((char **));
-static long reg_list PARAMS ((char **));
-static void thumb_load_store PARAMS ((char *, int, int));
-static int decode_shift PARAMS ((char **, int));
-static int ldst_extend PARAMS ((char **, int));
-static void thumb_add_sub PARAMS ((char *, int));
-static void insert_reg PARAMS ((int));
-static void thumb_shift PARAMS ((char *, int));
-static void thumb_mov_compare PARAMS ((char *, int));
-static void set_constant_flonums PARAMS ((void));
-static valueT md_chars_to_number PARAMS ((char *, int));
-static void insert_reg_alias PARAMS ((char *, int));
-static void output_inst PARAMS ((void));
-#ifdef OBJ_ELF
-static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
-#endif
-
-/* ARM instructions take 4bytes in the object file, Thumb instructions
- take 2: */
-#define INSN_SIZE 4
-
-/* LONGEST_INST is the longest basic instruction name without
- conditions or flags. ARM7M has 4 of length 5. El Segundo
- has one basic instruction name of length 7 (SMLALxy). */
-#define LONGEST_INST 7
-
-struct asm_opcode
-{
- /* Basic string to match. */
- CONST char * template;
-
- /* Basic instruction code. */
- unsigned long value;
-
- /* Compulsory suffix that must follow conds. If "", then the
- instruction is not conditional and must have no suffix. */
- CONST char * comp_suffix;
-
- /* Bits to toggle if flag 'n' set. */
- CONST struct asm_flg * flags;
-
- /* Which CPU variants this exists for. */
- unsigned long variants;
-
- /* Function to call to parse args. */
- void (* parms) PARAMS ((char *, unsigned long));
-};
-
-static CONST struct asm_opcode insns[] =
-{
-/* Intel XScale extensions to ARM V5 ISA. */
- {"mia", 0x0e200010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
- {"miaph", 0x0e280010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
- {"miabb", 0x0e2c0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
- {"miabt", 0x0e2d0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
- {"miatb", 0x0e2e0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
- {"miatt", 0x0e2f0010, NULL, NULL, ARM_EXT_XSCALE, do_mia},
- {"mar", 0x0c400000, NULL, NULL, ARM_EXT_XSCALE, do_mar},
- {"mra", 0x0c500000, NULL, NULL, ARM_EXT_XSCALE, do_mra},
- {"pld", 0xf450f000, "", NULL, ARM_EXT_XSCALE, do_pld},
- {"ldr", 0x000000d0, NULL, ldr_flags, ARM_ANY, do_ldrd},
- {"str", 0x000000f0, NULL, str_flags, ARM_ANY, do_ldrd},
-
-/* ARM Instructions. */
- {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
- {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
- {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
- {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
- {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
- {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
- {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
- {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
- {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
- {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
- {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
- {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
- {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
- {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
- {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
- {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
- {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
- {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
- {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
- {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
- {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
-#ifdef TE_WINCE
- {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch},
- {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch},
-#else
- {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
- {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
-#endif
-
-/* Pseudo ops. */
- {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
- {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
- {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
-
-/* ARM 2 multiplies. */
- {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
- {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
-
-/* ARM 3 - swp instructions. */
- {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
-
-/* ARM 6 Coprocessor instructions. */
- {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
- {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
-/* ScottB: our code uses 0x0128f000 for msr.
- NickC: but this is wrong because the bits 16 through 19 are
- handled by the PSR_xxx defines above. */
-
-/* ARM 7M long multiplies - need signed/unsigned flags! */
- {"smull", 0x00c00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
- {"umull", 0x00800090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
- {"smlal", 0x00e00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
- {"umlal", 0x00a00090, NULL, s_flag, ARM_EXT_LONGMUL, do_mull},
-
-/* ARM THUMB interworking. */
- {"bx", 0x012fff10, NULL, NULL, ARM_EXT_THUMB, do_bx},
-
-/* Floating point instructions. */
- {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
- {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
- {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
- {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
- {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
- {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
- {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
- {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
- {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
- {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
- {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
- {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
- {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
- {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
- {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
- {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
- {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
- {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
- {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
- {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
- {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
- {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
- {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
- {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
-/* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
- be an optional suffix, but part of the instruction. To be compatible,
- we accept either. */
- {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
- {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
- {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
- {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
-
-/* Generic copressor instructions. */
- {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
- {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
- {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
- {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
- {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
-
-/* ARM ISA extension 5. */
-/* Note: blx is actually 2 opcodes, so the .value is set dynamically.
- And it's sometimes conditional and sometimes not. */
- {"blx", 0, NULL, NULL, ARM_EXT_V5, do_blx},
- {"clz", 0x016f0f10, NULL, NULL, ARM_EXT_V5, do_clz},
- {"bkpt", 0xe1200070, "", NULL, ARM_EXT_V5, do_bkpt},
- {"ldc2", 0xfc100000, "", cplong_flag, ARM_EXT_V5, do_lstc2},
- {"stc2", 0xfc000000, "", cplong_flag, ARM_EXT_V5, do_lstc2},
- {"cdp2", 0xfe000000, "", NULL, ARM_EXT_V5, do_cdp2},
- {"mcr2", 0xfe000010, "", NULL, ARM_EXT_V5, do_co_reg2},
- {"mrc2", 0xfe100010, "", NULL, ARM_EXT_V5, do_co_reg2},
-
-/* ARM ISA extension 5E, El Segundo. */
- {"smlabb", 0x01000080, NULL, NULL, ARM_EXT_V5E, do_smla},
- {"smlatb", 0x010000a0, NULL, NULL, ARM_EXT_V5E, do_smla},
- {"smlabt", 0x010000c0, NULL, NULL, ARM_EXT_V5E, do_smla},
- {"smlatt", 0x010000e0, NULL, NULL, ARM_EXT_V5E, do_smla},
-
- {"smlawb", 0x01200080, NULL, NULL, ARM_EXT_V5E, do_smla},
- {"smlawt", 0x012000c0, NULL, NULL, ARM_EXT_V5E, do_smla},
-
- {"smlalbb",0x01400080, NULL, NULL, ARM_EXT_V5E, do_smlal},
- {"smlaltb",0x014000a0, NULL, NULL, ARM_EXT_V5E, do_smlal},
- {"smlalbt",0x014000c0, NULL, NULL, ARM_EXT_V5E, do_smlal},
- {"smlaltt",0x014000e0, NULL, NULL, ARM_EXT_V5E, do_smlal},
-
- {"smulbb", 0x01600080, NULL, NULL, ARM_EXT_V5E, do_smul},
- {"smultb", 0x016000a0, NULL, NULL, ARM_EXT_V5E, do_smul},
- {"smulbt", 0x016000c0, NULL, NULL, ARM_EXT_V5E, do_smul},
- {"smultt", 0x016000e0, NULL, NULL, ARM_EXT_V5E, do_smul},
-
- {"smulwb", 0x012000a0, NULL, NULL, ARM_EXT_V5E, do_smul},
- {"smulwt", 0x012000e0, NULL, NULL, ARM_EXT_V5E, do_smul},
-
- {"qadd", 0x01000050, NULL, NULL, ARM_EXT_V5E, do_qadd},
- {"qdadd", 0x01400050, NULL, NULL, ARM_EXT_V5E, do_qadd},
- {"qsub", 0x01200050, NULL, NULL, ARM_EXT_V5E, do_qadd},
- {"qdsub", 0x01600050, NULL, NULL, ARM_EXT_V5E, do_qadd},
-
- {"mcrr", 0x0c400000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c},
- {"mrrc", 0x0c500000, NULL, NULL, ARM_EXT_V5E, do_co_reg2c},
-};
-
-/* Defines for various bits that we will want to toggle. */
-#define INST_IMMEDIATE 0x02000000
-#define OFFSET_REG 0x02000000
-#define HWOFFSET_IMM 0x00400000
-#define SHIFT_BY_REG 0x00000010
-#define PRE_INDEX 0x01000000
-#define INDEX_UP 0x00800000
-#define WRITE_BACK 0x00200000
-#define LDM_TYPE_2_OR_3 0x00400000
-
-#define LITERAL_MASK 0xf000f000
-#define COND_MASK 0xf0000000
-#define OPCODE_MASK 0xfe1fffff
-#define DATA_OP_SHIFT 21
-
-/* Codes to distinguish the arithmetic instructions. */
-#define OPCODE_AND 0
-#define OPCODE_EOR 1
-#define OPCODE_SUB 2
-#define OPCODE_RSB 3
-#define OPCODE_ADD 4
-#define OPCODE_ADC 5
-#define OPCODE_SBC 6
-#define OPCODE_RSC 7
-#define OPCODE_TST 8
-#define OPCODE_TEQ 9
-#define OPCODE_CMP 10
-#define OPCODE_CMN 11
-#define OPCODE_ORR 12
-#define OPCODE_MOV 13
-#define OPCODE_BIC 14
-#define OPCODE_MVN 15
-
-static void do_t_nop PARAMS ((char *));
-static void do_t_arit PARAMS ((char *));
-static void do_t_add PARAMS ((char *));
-static void do_t_asr PARAMS ((char *));
-static void do_t_branch9 PARAMS ((char *));
-static void do_t_branch12 PARAMS ((char *));
-static void do_t_branch23 PARAMS ((char *));
-static void do_t_bx PARAMS ((char *));
-static void do_t_compare PARAMS ((char *));
-static void do_t_ldmstm PARAMS ((char *));
-static void do_t_ldr PARAMS ((char *));
-static void do_t_ldrb PARAMS ((char *));
-static void do_t_ldrh PARAMS ((char *));
-static void do_t_lds PARAMS ((char *));
-static void do_t_lsl PARAMS ((char *));
-static void do_t_lsr PARAMS ((char *));
-static void do_t_mov PARAMS ((char *));
-static void do_t_push_pop PARAMS ((char *));
-static void do_t_str PARAMS ((char *));
-static void do_t_strb PARAMS ((char *));
-static void do_t_strh PARAMS ((char *));
-static void do_t_sub PARAMS ((char *));
-static void do_t_swi PARAMS ((char *));
-static void do_t_adr PARAMS ((char *));
-
-#define T_OPCODE_MUL 0x4340
-#define T_OPCODE_TST 0x4200
-#define T_OPCODE_CMN 0x42c0
-#define T_OPCODE_NEG 0x4240
-#define T_OPCODE_MVN 0x43c0
-
-#define T_OPCODE_ADD_R3 0x1800
-#define T_OPCODE_SUB_R3 0x1a00
-#define T_OPCODE_ADD_HI 0x4400
-#define T_OPCODE_ADD_ST 0xb000
-#define T_OPCODE_SUB_ST 0xb080
-#define T_OPCODE_ADD_SP 0xa800
-#define T_OPCODE_ADD_PC 0xa000
-#define T_OPCODE_ADD_I8 0x3000
-#define T_OPCODE_SUB_I8 0x3800
-#define T_OPCODE_ADD_I3 0x1c00
-#define T_OPCODE_SUB_I3 0x1e00
-
-#define T_OPCODE_ASR_R 0x4100
-#define T_OPCODE_LSL_R 0x4080
-#define T_OPCODE_LSR_R 0x40c0
-#define T_OPCODE_ASR_I 0x1000
-#define T_OPCODE_LSL_I 0x0000
-#define T_OPCODE_LSR_I 0x0800
-
-#define T_OPCODE_MOV_I8 0x2000
-#define T_OPCODE_CMP_I8 0x2800
-#define T_OPCODE_CMP_LR 0x4280
-#define T_OPCODE_MOV_HR 0x4600
-#define T_OPCODE_CMP_HR 0x4500
-
-#define T_OPCODE_LDR_PC 0x4800
-#define T_OPCODE_LDR_SP 0x9800
-#define T_OPCODE_STR_SP 0x9000
-#define T_OPCODE_LDR_IW 0x6800
-#define T_OPCODE_STR_IW 0x6000
-#define T_OPCODE_LDR_IH 0x8800
-#define T_OPCODE_STR_IH 0x8000
-#define T_OPCODE_LDR_IB 0x7800
-#define T_OPCODE_STR_IB 0x7000
-#define T_OPCODE_LDR_RW 0x5800
-#define T_OPCODE_STR_RW 0x5000
-#define T_OPCODE_LDR_RH 0x5a00
-#define T_OPCODE_STR_RH 0x5200
-#define T_OPCODE_LDR_RB 0x5c00
-#define T_OPCODE_STR_RB 0x5400
-
-#define T_OPCODE_PUSH 0xb400
-#define T_OPCODE_POP 0xbc00
-
-#define T_OPCODE_BRANCH 0xe7fe
-
-static int thumb_reg PARAMS ((char ** str, int hi_lo));
-
-#define THUMB_SIZE 2 /* Size of thumb instruction. */
-#define THUMB_REG_LO 0x1
-#define THUMB_REG_HI 0x2
-#define THUMB_REG_ANY 0x3
-
-#define THUMB_H1 0x0080
-#define THUMB_H2 0x0040
-
-#define THUMB_ASR 0
-#define THUMB_LSL 1
-#define THUMB_LSR 2
-
-#define THUMB_MOVE 0
-#define THUMB_COMPARE 1
-
-#define THUMB_LOAD 0
-#define THUMB_STORE 1
-
-#define THUMB_PP_PC_LR 0x0100
-
-/* These three are used for immediate shifts, do not alter. */
-#define THUMB_WORD 2
-#define THUMB_HALFWORD 1
-#define THUMB_BYTE 0
-
-struct thumb_opcode
-{
- /* Basic string to match. */
- CONST char * template;
-
- /* Basic instruction code. */
- unsigned long value;
-
- int size;
-
- /* Which CPU variants this exists for. */
- unsigned long variants;
-
- /* Function to call to parse args. */
- void (* parms) PARAMS ((char *));
-};
-
-static CONST struct thumb_opcode tinsns[] =
-{
- {"adc", 0x4140, 2, ARM_EXT_THUMB, do_t_arit},
- {"add", 0x0000, 2, ARM_EXT_THUMB, do_t_add},
- {"and", 0x4000, 2, ARM_EXT_THUMB, do_t_arit},
- {"asr", 0x0000, 2, ARM_EXT_THUMB, do_t_asr},
- {"b", T_OPCODE_BRANCH, 2, ARM_EXT_THUMB, do_t_branch12},
- {"beq", 0xd0fe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bne", 0xd1fe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bcs", 0xd2fe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bhs", 0xd2fe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bcc", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bul", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"blo", 0xd3fe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bmi", 0xd4fe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bpl", 0xd5fe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bvs", 0xd6fe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bvc", 0xd7fe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bhi", 0xd8fe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bls", 0xd9fe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bge", 0xdafe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"blt", 0xdbfe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bgt", 0xdcfe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"ble", 0xddfe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bal", 0xdefe, 2, ARM_EXT_THUMB, do_t_branch9},
- {"bic", 0x4380, 2, ARM_EXT_THUMB, do_t_arit},
- {"bl", 0xf7fffffe, 4, ARM_EXT_THUMB, do_t_branch23},
- {"blx", 0, 0, ARM_EXT_V5, do_t_blx},
- {"bkpt", 0xbe00, 2, ARM_EXT_V5, do_t_bkpt},
- {"bx", 0x4700, 2, ARM_EXT_THUMB, do_t_bx},
- {"cmn", T_OPCODE_CMN, 2, ARM_EXT_THUMB, do_t_arit},
- {"cmp", 0x0000, 2, ARM_EXT_THUMB, do_t_compare},
- {"eor", 0x4040, 2, ARM_EXT_THUMB, do_t_arit},
- {"ldmia", 0xc800, 2, ARM_EXT_THUMB, do_t_ldmstm},
- {"ldr", 0x0000, 2, ARM_EXT_THUMB, do_t_ldr},
- {"ldrb", 0x0000, 2, ARM_EXT_THUMB, do_t_ldrb},
- {"ldrh", 0x0000, 2, ARM_EXT_THUMB, do_t_ldrh},
- {"ldrsb", 0x5600, 2, ARM_EXT_THUMB, do_t_lds},
- {"ldrsh", 0x5e00, 2, ARM_EXT_THUMB, do_t_lds},
- {"ldsb", 0x5600, 2, ARM_EXT_THUMB, do_t_lds},
- {"ldsh", 0x5e00, 2, ARM_EXT_THUMB, do_t_lds},
- {"lsl", 0x0000, 2, ARM_EXT_THUMB, do_t_lsl},
- {"lsr", 0x0000, 2, ARM_EXT_THUMB, do_t_lsr},
- {"mov", 0x0000, 2, ARM_EXT_THUMB, do_t_mov},
- {"mul", T_OPCODE_MUL, 2, ARM_EXT_THUMB, do_t_arit},
- {"mvn", T_OPCODE_MVN, 2, ARM_EXT_THUMB, do_t_arit},
- {"neg", T_OPCODE_NEG, 2, ARM_EXT_THUMB, do_t_arit},
- {"orr", 0x4300, 2, ARM_EXT_THUMB, do_t_arit},
- {"pop", 0xbc00, 2, ARM_EXT_THUMB, do_t_push_pop},
- {"push", 0xb400, 2, ARM_EXT_THUMB, do_t_push_pop},
- {"ror", 0x41c0, 2, ARM_EXT_THUMB, do_t_arit},
- {"sbc", 0x4180, 2, ARM_EXT_THUMB, do_t_arit},
- {"stmia", 0xc000, 2, ARM_EXT_THUMB, do_t_ldmstm},
- {"str", 0x0000, 2, ARM_EXT_THUMB, do_t_str},
- {"strb", 0x0000, 2, ARM_EXT_THUMB, do_t_strb},
- {"strh", 0x0000, 2, ARM_EXT_THUMB, do_t_strh},
- {"swi", 0xdf00, 2, ARM_EXT_THUMB, do_t_swi},
- {"sub", 0x0000, 2, ARM_EXT_THUMB, do_t_sub},
- {"tst", T_OPCODE_TST, 2, ARM_EXT_THUMB, do_t_arit},
- /* Pseudo ops: */
- {"adr", 0x0000, 2, ARM_EXT_THUMB, do_t_adr},
- {"nop", 0x46C0, 2, ARM_EXT_THUMB, do_t_nop}, /* mov r8,r8 */
-};
-
-struct reg_entry
-{
- CONST char * name;
- int number;
-};
-
-#define int_register(reg) ((reg) >= 0 && (reg) <= 15)
-#define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
-#define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
-
-#define REG_PC 15
-#define REG_LR 14
-#define REG_SP 13
-
-/* These are the standard names. Users can add aliases with .req. */
-static CONST struct reg_entry reg_table[] =
-{
- /* Processor Register Numbers. */
- {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
- {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
- {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
- {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
- /* APCS conventions. */
- {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
- {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
- {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
- {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
- /* ATPCS additions to APCS conventions. */
- {"wr", 7}, {"v8", 11},
- /* FP Registers. */
- {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
- {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
- {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
- {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
- {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
- {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
- {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
- {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
- {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
- {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
- /* ATPCS additions to float register names. */
- {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
- {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
- {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
- {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
- /* FIXME: At some point we need to add VFP register names. */
- /* Array terminator. */
- {NULL, 0}
-};
-
-#define BAD_ARGS _("Bad arguments to instruction")
-#define BAD_PC _("r15 not allowed here")
-#define BAD_FLAGS _("Instruction should not have flags")
-#define BAD_COND _("Instruction is not conditional")
-#define ERR_NO_ACCUM _("acc0 expected")
-
-static struct hash_control * arm_ops_hsh = NULL;
-static struct hash_control * arm_tops_hsh = NULL;
-static struct hash_control * arm_cond_hsh = NULL;
-static struct hash_control * arm_shift_hsh = NULL;
-static struct hash_control * arm_reg_hsh = NULL;
-static struct hash_control * arm_psr_hsh = NULL;
-
-/* This table describes all the machine specific pseudo-ops the assembler
- has to support. The fields are:
- pseudo-op name without dot
- function to call to execute this pseudo-op
- Integer arg to pass to the function. */
-
-static void s_req PARAMS ((int));
-static void s_align PARAMS ((int));
-static void s_bss PARAMS ((int));
-static void s_even PARAMS ((int));
-static void s_ltorg PARAMS ((int));
-static void s_arm PARAMS ((int));
-static void s_thumb PARAMS ((int));
-static void s_code PARAMS ((int));
-static void s_force_thumb PARAMS ((int));
-static void s_thumb_func PARAMS ((int));
-static void s_thumb_set PARAMS ((int));
-static void arm_s_text PARAMS ((int));
-static void arm_s_data PARAMS ((int));
-#ifdef OBJ_ELF
-static void arm_s_section PARAMS ((int));
-static void s_arm_elf_cons PARAMS ((int));
-#endif
-
-static int my_get_expression PARAMS ((expressionS *, char **));
-
-CONST pseudo_typeS md_pseudo_table[] =
-{
- /* Never called becasue '.req' does not start line. */
- { "req", s_req, 0 },
- { "bss", s_bss, 0 },
- { "align", s_align, 0 },
- { "arm", s_arm, 0 },
- { "thumb", s_thumb, 0 },
- { "code", s_code, 0 },
- { "force_thumb", s_force_thumb, 0 },
- { "thumb_func", s_thumb_func, 0 },
- { "thumb_set", s_thumb_set, 0 },
- { "even", s_even, 0 },
- { "ltorg", s_ltorg, 0 },
- { "pool", s_ltorg, 0 },
- /* Allow for the effect of section changes. */
- { "text", arm_s_text, 0 },
- { "data", arm_s_data, 0 },
-#ifdef OBJ_ELF
- { "section", arm_s_section, 0 },
- { "section.s", arm_s_section, 0 },
- { "sect", arm_s_section, 0 },
- { "sect.s", arm_s_section, 0 },
- { "word", s_arm_elf_cons, 4 },
- { "long", s_arm_elf_cons, 4 },
- { "file", dwarf2_directive_file, 0 },
- { "loc", dwarf2_directive_loc, 0 },
-#else
- { "word", cons, 4},
-#endif
- { "extend", float_cons, 'x' },
- { "ldouble", float_cons, 'x' },
- { "packed", float_cons, 'p' },
- { 0, 0, 0 }
-};
-
-/* Stuff needed to resolve the label ambiguity
- As:
- ...
- label: <insn>
- may differ from:
- ...
- label:
- <insn>
-*/
-
-symbolS * last_label_seen;
-static int label_is_thumb_function_name = false;
-
-/* Literal stuff. */
-
-#define MAX_LITERAL_POOL_SIZE 1024
-
-typedef struct literalS
-{
- struct expressionS exp;
- struct arm_it * inst;
-} literalT;
-
-literalT literals[MAX_LITERAL_POOL_SIZE];
-
-/* Next free entry in the pool. */
-int next_literal_pool_place = 0;
-
-/* Next literal pool number. */
-int lit_pool_num = 1;
-
-symbolS * current_poolP = NULL;
-
-static int
-add_to_lit_pool ()
-{
- int lit_count = 0;
-
- if (current_poolP == NULL)
- current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
- (valueT) 0, &zero_address_frag);
-
- /* Check if this literal value is already in the pool: */
- while (lit_count < next_literal_pool_place)
- {
- if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
- && inst.reloc.exp.X_op == O_constant
- && (literals[lit_count].exp.X_add_number
- == inst.reloc.exp.X_add_number)
- && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
- break;
-
- if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
- && inst.reloc.exp.X_op == O_symbol
- && (literals[lit_count].exp.X_add_number
- == inst.reloc.exp.X_add_number)
- && (literals[lit_count].exp.X_add_symbol
- == inst.reloc.exp.X_add_symbol)
- && (literals[lit_count].exp.X_op_symbol
- == inst.reloc.exp.X_op_symbol))
- break;
-
- lit_count++;
- }
-
- if (lit_count == next_literal_pool_place) /* New entry. */
- {
- if (next_literal_pool_place >= MAX_LITERAL_POOL_SIZE)
- {
- inst.error = _("Literal Pool Overflow");
- return FAIL;
- }
-
- literals[next_literal_pool_place].exp = inst.reloc.exp;
- lit_count = next_literal_pool_place++;
- }
-
- inst.reloc.exp.X_op = O_symbol;
- inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
- inst.reloc.exp.X_add_symbol = current_poolP;
-
- return SUCCESS;
-}
-
-/* Can't use symbol_new here, so have to create a symbol and then at
- a later date assign it a value. Thats what these functions do. */
-
-static void
-symbol_locate (symbolP, name, segment, valu, frag)
- symbolS * symbolP;
- CONST char * name; /* It is copied, the caller can modify. */
- segT segment; /* Segment identifier (SEG_<something>). */
- valueT valu; /* Symbol value. */
- fragS * frag; /* Associated fragment. */
-{
- unsigned int name_length;
- char * preserved_copy_of_name;
-
- name_length = strlen (name) + 1; /* +1 for \0. */
- obstack_grow (&notes, name, name_length);
- preserved_copy_of_name = obstack_finish (&notes);
-#ifdef STRIP_UNDERSCORE
- if (preserved_copy_of_name[0] == '_')
- preserved_copy_of_name++;
-#endif
-
-#ifdef tc_canonicalize_symbol_name
- preserved_copy_of_name =
- tc_canonicalize_symbol_name (preserved_copy_of_name);
-#endif
-
- S_SET_NAME (symbolP, preserved_copy_of_name);
-
- S_SET_SEGMENT (symbolP, segment);
- S_SET_VALUE (symbolP, valu);
- symbol_clear_list_pointers(symbolP);
-
- symbol_set_frag (symbolP, frag);
-
- /* Link to end of symbol chain. */
- {
- extern int symbol_table_frozen;
- if (symbol_table_frozen)
- abort ();
- }
-
- symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
-
- obj_symbol_new_hook (symbolP);
-
-#ifdef tc_symbol_new_hook
- tc_symbol_new_hook (symbolP);
-#endif
-
-#ifdef DEBUG_SYMS
- verify_symbol_chain (symbol_rootP, symbol_lastP);
-#endif /* DEBUG_SYMS */
-}
-
-/* Check that an immediate is valid.
- If so, convert it to the right format. */
-
-static unsigned int
-validate_immediate (val)
- unsigned int val;
-{
- unsigned int a;
- unsigned int i;
-
-#define rotate_left(v, n) (v << n | v >> (32 - n))
-
- for (i = 0; i < 32; i += 2)
- if ((a = rotate_left (val, i)) <= 0xff)
- return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
-
- return FAIL;
-}
-
-/* Check to see if an immediate can be computed as two seperate immediate
- values, added together. We already know that this value cannot be
- computed by just one ARM instruction. */
-
-static unsigned int
-validate_immediate_twopart (val, highpart)
- unsigned int val;
- unsigned int * highpart;
-{
- unsigned int a;
- unsigned int i;
-
- for (i = 0; i < 32; i += 2)
- if (((a = rotate_left (val, i)) & 0xff) != 0)
- {
- if (a & 0xff00)
- {
- if (a & ~ 0xffff)
- continue;
- * highpart = (a >> 8) | ((i + 24) << 7);
- }
- else if (a & 0xff0000)
- {
- if (a & 0xff000000)
- continue;
- * highpart = (a >> 16) | ((i + 16) << 7);
- }
- else
- {
- assert (a & 0xff000000);
- * highpart = (a >> 24) | ((i + 8) << 7);
- }
-
- return (a & 0xff) | (i << 7);
- }
-
- return FAIL;
-}
-
-static int
-validate_offset_imm (val, hwse)
- unsigned int val;
- int hwse;
-{
- if ((hwse && val > 255) || val > 4095)
- return FAIL;
- return val;
-}
-
-static void
-s_req (a)
- int a ATTRIBUTE_UNUSED;
-{
- as_bad (_("Invalid syntax for .req directive."));
-}
-
-static void
-s_bss (ignore)
- int ignore ATTRIBUTE_UNUSED;
-{
- /* We don't support putting frags in the BSS segment, we fake it by
- marking in_bss, then looking at s_skip for clues. */
- subseg_set (bss_section, 0);
- demand_empty_rest_of_line ();
-}
-
-static void
-s_even (ignore)
- int ignore ATTRIBUTE_UNUSED;
-{
- /* Never make frag if expect extra pass. */
- if (!need_pass_2)
- frag_align (1, 0, 0);
-
- record_alignment (now_seg, 1);
-
- demand_empty_rest_of_line ();
-}
-
-static void
-s_ltorg (ignored)
- int ignored ATTRIBUTE_UNUSED;
-{
- int lit_count = 0;
- char sym_name[20];
-
- if (current_poolP == NULL)
- return;
-
- /* Align pool as you have word accesses.
- Only make a frag if we have to. */
- if (!need_pass_2)
- frag_align (2, 0, 0);
-
- record_alignment (now_seg, 2);
-
- sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
-
- symbol_locate (current_poolP, sym_name, now_seg,
- (valueT) frag_now_fix (), frag_now);
- symbol_table_insert (current_poolP);
-
- ARM_SET_THUMB (current_poolP, thumb_mode);
-
-#if defined OBJ_COFF || defined OBJ_ELF
- ARM_SET_INTERWORK (current_poolP, support_interwork);
-#endif
-
- while (lit_count < next_literal_pool_place)
- /* First output the expression in the instruction to the pool. */
- emit_expr (&(literals[lit_count++].exp), 4); /* .word */
-
- next_literal_pool_place = 0;
- current_poolP = NULL;
-}
-
-/* Same as s_align_ptwo but align 0 => align 2. */
-
-static void
-s_align (unused)
- int unused ATTRIBUTE_UNUSED;
-{
- register int temp;
- register long temp_fill;
- long max_alignment = 15;
-
- temp = get_absolute_expression ();
- if (temp > max_alignment)
- as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
- else if (temp < 0)
- {
- as_bad (_("Alignment negative. 0 assumed."));
- temp = 0;
- }
-
- if (*input_line_pointer == ',')
- {
- input_line_pointer++;
- temp_fill = get_absolute_expression ();
- }
- else
- temp_fill = 0;
-
- if (!temp)
- temp = 2;
-
- /* Only make a frag if we HAVE to. */
- if (temp && !need_pass_2)
- frag_align (temp, (int) temp_fill, 0);
- demand_empty_rest_of_line ();
-
- record_alignment (now_seg, temp);
-}
-
-static void
-s_force_thumb (ignore)
- int ignore ATTRIBUTE_UNUSED;
-{
- /* If we are not already in thumb mode go into it, EVEN if
- the target processor does not support thumb instructions.
- This is used by gcc/config/arm/lib1funcs.asm for example
- to compile interworking support functions even if the
- target processor should not support interworking. */
- if (! thumb_mode)
- {
- thumb_mode = 2;
-
- record_alignment (now_seg, 1);
- }
-
- demand_empty_rest_of_line ();
-}
-
-static void
-s_thumb_func (ignore)
- int ignore ATTRIBUTE_UNUSED;
-{
- if (! thumb_mode)
- opcode_select (16);
-
- /* The following label is the name/address of the start of a Thumb function.
- We need to know this for the interworking support. */
- label_is_thumb_function_name = true;
-
- demand_empty_rest_of_line ();
-}
-
-/* Perform a .set directive, but also mark the alias as
- being a thumb function. */
-
-static void
-s_thumb_set (equiv)
- int equiv;
-{
- /* XXX the following is a duplicate of the code for s_set() in read.c
- We cannot just call that code as we need to get at the symbol that
- is created. */
- register char * name;
- register char delim;
- register char * end_name;
- register symbolS * symbolP;
-
- /* Especial apologies for the random logic:
- This just grew, and could be parsed much more simply!
- Dean - in haste. */
- name = input_line_pointer;
- delim = get_symbol_end ();
- end_name = input_line_pointer;
- *end_name = delim;
-
- SKIP_WHITESPACE ();
-
- if (*input_line_pointer != ',')
- {
- *end_name = 0;
- as_bad (_("Expected comma after name \"%s\""), name);
- *end_name = delim;
- ignore_rest_of_line ();
- return;
- }
-
- input_line_pointer++;
- *end_name = 0;
-
- if (name[0] == '.' && name[1] == '\0')
- {
- /* XXX - this should not happen to .thumb_set. */
- abort ();
- }
-
- if ((symbolP = symbol_find (name)) == NULL
- && (symbolP = md_undefined_symbol (name)) == NULL)
- {
-#ifndef NO_LISTING
- /* When doing symbol listings, play games with dummy fragments living
- outside the normal fragment chain to record the file and line info
- for this symbol. */
- if (listing & LISTING_SYMBOLS)
- {
- extern struct list_info_struct * listing_tail;
- fragS * dummy_frag = (fragS *) xmalloc (sizeof (fragS));
-
- memset (dummy_frag, 0, sizeof (fragS));
- dummy_frag->fr_type = rs_fill;
- dummy_frag->line = listing_tail;
- symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
- dummy_frag->fr_symbol = symbolP;
- }
- else
-#endif
- symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
-
-#ifdef OBJ_COFF
- /* "set" symbols are local unless otherwise specified. */
- SF_SET_LOCAL (symbolP);
-#endif /* OBJ_COFF */
- } /* Make a new symbol. */
-
- symbol_table_insert (symbolP);
-
- * end_name = delim;
-
- if (equiv
- && S_IS_DEFINED (symbolP)
- && S_GET_SEGMENT (symbolP) != reg_section)
- as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
-
- pseudo_set (symbolP);
-
- demand_empty_rest_of_line ();
-
- /* XXX Now we come to the Thumb specific bit of code. */
-
- THUMB_SET_FUNC (symbolP, 1);
- ARM_SET_THUMB (symbolP, 1);
-#if defined OBJ_ELF || defined OBJ_COFF
- ARM_SET_INTERWORK (symbolP, support_interwork);
-#endif
-}
-
-/* If we change section we must dump the literal pool first. */
-
-static void
-arm_s_text (ignore)
- int ignore;
-{
- if (now_seg != text_section)
- s_ltorg (0);
-
-#ifdef OBJ_ELF
- obj_elf_text (ignore);
-#else
- s_text (ignore);
-#endif
-}
-
-static void
-arm_s_data (ignore)
- int ignore;
-{
- if (flag_readonly_data_in_text)
- {
- if (now_seg != text_section)
- s_ltorg (0);
- }
- else if (now_seg != data_section)
- s_ltorg (0);
-
-#ifdef OBJ_ELF
- obj_elf_data (ignore);
-#else
- s_data (ignore);
-#endif
-}
-
-#ifdef OBJ_ELF
-static void
-arm_s_section (ignore)
- int ignore;
-{
- s_ltorg (0);
-
- obj_elf_section (ignore);
-}
-#endif
-
-static void
-opcode_select (width)
- int width;
-{
- switch (width)
- {
- case 16:
- if (! thumb_mode)
- {
- if (! (cpu_variant & ARM_EXT_THUMB))
- as_bad (_("selected processor does not support THUMB opcodes"));
-
- thumb_mode = 1;
- /* No need to force the alignment, since we will have been
- coming from ARM mode, which is word-aligned. */
- record_alignment (now_seg, 1);
- }
- break;
-
- case 32:
- if (thumb_mode)
- {
- if ((cpu_variant & ARM_ANY) == ARM_EXT_THUMB)
- as_bad (_("selected processor does not support ARM opcodes"));
-
- thumb_mode = 0;
-
- if (!need_pass_2)
- frag_align (2, 0, 0);
-
- record_alignment (now_seg, 1);
- }
- break;
-
- default:
- as_bad (_("invalid instruction size selected (%d)"), width);
- }
-}
-
-static void
-s_arm (ignore)
- int ignore ATTRIBUTE_UNUSED;
-{
- opcode_select (32);
- demand_empty_rest_of_line ();
-}
-
-static void
-s_thumb (ignore)
- int ignore ATTRIBUTE_UNUSED;
-{
- opcode_select (16);
- demand_empty_rest_of_line ();
-}
-
-static void
-s_code (unused)
- int unused ATTRIBUTE_UNUSED;
-{
- register int temp;
-
- temp = get_absolute_expression ();
- switch (temp)
- {
- case 16:
- case 32:
- opcode_select (temp);
- break;
-
- default:
- as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
- }
-}
-
-static void
-end_of_line (str)
- char * str;
-{
- skip_whitespace (str);
-
- if (* str != '\0')
- inst.error = _("Garbage following instruction");
-}
-
-static int
-skip_past_comma (str)
- char ** str;
-{
- char * p = * str, c;
- int comma = 0;
-
- while ((c = *p) == ' ' || c == ',')
- {
- p++;
- if (c == ',' && comma++)
- return FAIL;
- }
-
- if (c == '\0')
- return FAIL;
-
- *str = p;
- return comma ? SUCCESS : FAIL;
-}
-
-/* A standard register must be given at this point.
- SHIFT is the place to put it in inst.instruction.
- Restores input start point on error.
- Returns the reg#, or FAIL. */
-
-static int
-reg_required_here (str, shift)
- char ** str;
- int shift;
-{
- static char buff [128]; /* XXX */
- int reg;
- char * start = * str;
-
- if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
- {
- if (shift >= 0)
- inst.instruction |= reg << shift;
- return reg;
- }
-
- /* Restore the start point, we may have got a reg of the wrong class. */
- *str = start;
-
- /* In the few cases where we might be able to accept something else
- this error can be overridden. */
- sprintf (buff, _("Register expected, not '%.100s'"), start);
- inst.error = buff;
-
- return FAIL;
-}
-
-static CONST struct asm_psr *
-arm_psr_parse (ccp)
- register char ** ccp;
-{
- char * start = * ccp;
- char c;
- char * p;
- CONST struct asm_psr * psr;
-
- p = start;
-
- /* Skip to the end of the next word in the input stream. */
- do
- {
- c = *p++;
- }
- while (isalpha (c) || c == '_');
-
- /* Terminate the word. */
- *--p = 0;
-
- /* CPSR's and SPSR's can now be lowercase. This is just a convenience
- feature for ease of use and backwards compatibility. */
- if (!strncmp (start, "cpsr", 4))
- strncpy (start, "CPSR", 4);
- else if (!strncmp (start, "spsr", 4))
- strncpy (start, "SPSR", 4);
-
- /* Now locate the word in the psr hash table. */
- psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
-
- /* Restore the input stream. */
- *p = c;
-
- /* If we found a valid match, advance the
- stream pointer past the end of the word. */
- *ccp = p;
-
- return psr;
-}
-
-/* Parse the input looking for a PSR flag. */
-
-static int
-psr_required_here (str)
- char ** str;
-{
- char * start = * str;
- CONST struct asm_psr * psr;
-
- psr = arm_psr_parse (str);
-
- if (psr)
- {
- /* If this is the SPSR that is being modified, set the R bit. */
- if (! psr->cpsr)
- inst.instruction |= SPSR_BIT;
-
- /* Set the psr flags in the MSR instruction. */
- inst.instruction |= psr->field << PSR_SHIFT;
-
- return SUCCESS;
- }
-
- /* In the few cases where we might be able to accept
- something else this error can be overridden. */
- inst.error = _("flag for {c}psr instruction expected");
-
- /* Restore the start point. */
- *str = start;
- return FAIL;
-}
-
-static int
-co_proc_number (str)
- char ** str;
-{
- int processor, pchar;
-
- skip_whitespace (* str);
-
- /* The data sheet seems to imply that just a number on its own is valid
- here, but the RISC iX assembler seems to accept a prefix 'p'. We will
- accept either. */
- if (**str == 'p' || **str == 'P')
- (*str)++;
-
- pchar = *(*str)++;
- if (pchar >= '0' && pchar <= '9')
- {
- processor = pchar - '0';
- if (**str >= '0' && **str <= '9')
- {
- processor = processor * 10 + *(*str)++ - '0';
- if (processor > 15)
- {
- inst.error = _("Illegal co-processor number");
- return FAIL;
- }
- }
- }
- else
- {
- inst.error = _("Bad or missing co-processor number");
- return FAIL;
- }
-
- inst.instruction |= processor << 8;
- return SUCCESS;
-}
-
-static int
-cp_opc_expr (str, where, length)
- char ** str;
- int where;
- int length;
-{
- expressionS expr;
-
- skip_whitespace (* str);
-
- memset (&expr, '\0', sizeof (expr));
-
- if (my_get_expression (&expr, str))
- return FAIL;
- if (expr.X_op != O_constant)
- {
- inst.error = _("bad or missing expression");
- return FAIL;
- }
-
- if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
- {
- inst.error = _("immediate co-processor expression too large");
- return FAIL;
- }
-
- inst.instruction |= expr.X_add_number << where;
- return SUCCESS;
-}
-
-static int
-cp_reg_required_here (str, where)
- char ** str;
- int where;
-{
- int reg;
- char * start = *str;
-
- if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
- {
- reg &= 15;
- inst.instruction |= reg << where;
- return reg;
- }
-
- /* In the few cases where we might be able to accept something else
- this error can be overridden. */
- inst.error = _("Co-processor register expected");
-
- /* Restore the start point. */
- *str = start;
- return FAIL;
-}
-
-static int
-fp_reg_required_here (str, where)
- char ** str;
- int where;
-{
- int reg;
- char * start = * str;
-
- if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
- {
- reg &= 7;
- inst.instruction |= reg << where;
- return reg;
- }
-
- /* In the few cases where we might be able to accept something else
- this error can be overridden. */
- inst.error = _("Floating point register expected");
-
- /* Restore the start point. */
- *str = start;
- return FAIL;
-}
-
-static int
-cp_address_offset (str)
- char ** str;
-{
- int offset;
-
- skip_whitespace (* str);
-
- if (! is_immediate_prefix (**str))
- {
- inst.error = _("immediate expression expected");
- return FAIL;
- }
-
- (*str)++;
-
- if (my_get_expression (& inst.reloc.exp, str))
- return FAIL;
-
- if (inst.reloc.exp.X_op == O_constant)
- {
- offset = inst.reloc.exp.X_add_number;
-
- if (offset & 3)
- {
- inst.error = _("co-processor address must be word aligned");
- return FAIL;
- }
-
- if (offset > 1023 || offset < -1023)
- {
- inst.error = _("offset too large");
- return FAIL;
- }
-
- if (offset >= 0)
- inst.instruction |= INDEX_UP;
- else
- offset = -offset;
-
- inst.instruction |= offset >> 2;
- }
- else
- inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
-
- return SUCCESS;
-}
-
-static int
-cp_address_required_here (str)
- char ** str;
-{
- char * p = * str;
- int pre_inc = 0;
- int write_back = 0;
-
- if (*p == '[')
- {
- int reg;
-
- p++;
- skip_whitespace (p);
-
- if ((reg = reg_required_here (& p, 16)) == FAIL)
- return FAIL;
-
- skip_whitespace (p);
-
- if (*p == ']')
- {
- p++;
-
- if (skip_past_comma (& p) == SUCCESS)
- {
- /* [Rn], #expr */
- write_back = WRITE_BACK;
-
- if (reg == REG_PC)
- {
- inst.error = _("pc may not be used in post-increment");
- return FAIL;
- }
-
- if (cp_address_offset (& p) == FAIL)
- return FAIL;
- }
- else
- pre_inc = PRE_INDEX | INDEX_UP;
- }
- else
- {
- /* '['Rn, #expr']'[!] */
-
- if (skip_past_comma (& p) == FAIL)
- {
- inst.error = _("pre-indexed expression expected");
- return FAIL;
- }
-
- pre_inc = PRE_INDEX;
-
- if (cp_address_offset (& p) == FAIL)
- return FAIL;
-
- skip_whitespace (p);
-
- if (*p++ != ']')
- {
- inst.error = _("missing ]");
- return FAIL;
- }
-
- skip_whitespace (p);
-
- if (*p == '!')
- {
- if (reg == REG_PC)
- {
- inst.error = _("pc may not be used with write-back");
- return FAIL;
- }
-
- p++;
- write_back = WRITE_BACK;
- }
- }
- }
- else
- {
- if (my_get_expression (&inst.reloc.exp, &p))
- return FAIL;
-
- inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
- inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */
- inst.reloc.pc_rel = 1;
- inst.instruction |= (REG_PC << 16);
- pre_inc = PRE_INDEX;
- }
-
- inst.instruction |= write_back | pre_inc;
- *str = p;
- return SUCCESS;
-}
-
-static void
-do_nop (str, flags)
- char * str;
- unsigned long flags;
-{
- /* Do nothing really. */
- inst.instruction |= flags; /* This is pointless. */
- end_of_line (str);
- return;
-}
-
-static void
-do_mrs (str, flags)
- char *str;
- unsigned long flags;
-{
- int skip = 0;
-
- /* Only one syntax. */
- skip_whitespace (str);
-
- if (reg_required_here (&str, 12) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL)
- {
- inst.error = _("comma expected after register name");
- return;
- }
-
- skip_whitespace (str);
-
- if ( strcmp (str, "CPSR") == 0
- || strcmp (str, "SPSR") == 0
- /* Lower case versions for backwards compatability. */
- || strcmp (str, "cpsr") == 0
- || strcmp (str, "spsr") == 0)
- skip = 4;
-
- /* This is for backwards compatability with older toolchains. */
- else if ( strcmp (str, "cpsr_all") == 0
- || strcmp (str, "spsr_all") == 0)
- skip = 8;
- else
- {
- inst.error = _("{C|S}PSR expected");
- return;
- }
-
- if (* str == 's' || * str == 'S')
- inst.instruction |= SPSR_BIT;
- str += skip;
-
- inst.instruction |= flags;
- end_of_line (str);
-}
-
-/* Two possible forms:
- "{C|S}PSR_<field>, Rm",
- "{C|S}PSR_f, #expression". */
-
-static void
-do_msr (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
-
- if (psr_required_here (& str) == FAIL)
- return;
-
- if (skip_past_comma (& str) == FAIL)
- {
- inst.error = _("comma missing after psr flags");
- return;
- }
-
- skip_whitespace (str);
-
- if (reg_required_here (& str, 0) != FAIL)
- {
- inst.error = NULL;
- inst.instruction |= flags;
- end_of_line (str);
- return;
- }
-
- if (! is_immediate_prefix (* str))
- {
- inst.error =
- _("only a register or immediate value can follow a psr flag");
- return;
- }
-
- str ++;
- inst.error = NULL;
-
- if (my_get_expression (& inst.reloc.exp, & str))
- {
- inst.error =
- _("only a register or immediate value can follow a psr flag");
- return;
- }
-
-#if 0 /* The first edition of the ARM architecture manual stated that
- writing anything other than the flags with an immediate operation
- had UNPREDICTABLE effects. This constraint was removed in the
- second edition of the specification. */
- if ((cpu_variant & ARM_EXT_V5) != ARM_EXT_V5
- && inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT))
- {
- inst.error = _("immediate value cannot be used to set this field");
- return;
- }
-#endif
-
- flags |= INST_IMMEDIATE;
-
- if (inst.reloc.exp.X_add_symbol)
- {
- inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
- inst.reloc.pc_rel = 0;
- }
- else
- {
- unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
-
- if (value == (unsigned) FAIL)
- {
- inst.error = _("Invalid constant");
- return;
- }
-
- inst.instruction |= value;
- }
-
- inst.error = NULL;
- inst.instruction |= flags;
- end_of_line (str);
-}
-
-/* Long Multiply Parser
- UMULL RdLo, RdHi, Rm, Rs
- SMULL RdLo, RdHi, Rm, Rs
- UMLAL RdLo, RdHi, Rm, Rs
- SMLAL RdLo, RdHi, Rm, Rs. */
-
-static void
-do_mull (str, flags)
- char * str;
- unsigned long flags;
-{
- int rdlo, rdhi, rm, rs;
-
- /* Only one format "rdlo, rdhi, rm, rs". */
- skip_whitespace (str);
-
- if ((rdlo = reg_required_here (&str, 12)) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || (rdhi = reg_required_here (&str, 16)) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || (rm = reg_required_here (&str, 0)) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- /* rdhi, rdlo and rm must all be different. */
- if (rdlo == rdhi || rdlo == rm || rdhi == rm)
- as_tsktsk (_("rdhi, rdlo and rm must all be different"));
-
- if (skip_past_comma (&str) == FAIL
- || (rs = reg_required_here (&str, 8)) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
- {
- inst.error = BAD_PC;
- return;
- }
-
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
-
-static void
-do_mul (str, flags)
- char * str;
- unsigned long flags;
-{
- int rd, rm;
-
- /* Only one format "rd, rm, rs". */
- skip_whitespace (str);
-
- if ((rd = reg_required_here (&str, 16)) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- if (rd == REG_PC)
- {
- inst.error = BAD_PC;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || (rm = reg_required_here (&str, 0)) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- if (rm == REG_PC)
- {
- inst.error = BAD_PC;
- return;
- }
-
- if (rm == rd)
- as_tsktsk (_("rd and rm should be different in mul"));
-
- if (skip_past_comma (&str) == FAIL
- || (rm = reg_required_here (&str, 8)) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- if (rm == REG_PC)
- {
- inst.error = BAD_PC;
- return;
- }
-
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
-
-static void
-do_mla (str, flags)
- char * str;
- unsigned long flags;
-{
- int rd, rm;
-
- /* Only one format "rd, rm, rs, rn". */
- skip_whitespace (str);
-
- if ((rd = reg_required_here (&str, 16)) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- if (rd == REG_PC)
- {
- inst.error = BAD_PC;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || (rm = reg_required_here (&str, 0)) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- if (rm == REG_PC)
- {
- inst.error = BAD_PC;
- return;
- }
-
- if (rm == rd)
- as_tsktsk (_("rd and rm should be different in mla"));
-
- if (skip_past_comma (&str) == FAIL
- || (rd = reg_required_here (&str, 8)) == FAIL
- || skip_past_comma (&str) == FAIL
- || (rm = reg_required_here (&str, 12)) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- if (rd == REG_PC || rm == REG_PC)
- {
- inst.error = BAD_PC;
- return;
- }
-
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
-
-/* Expects *str -> the characters "acc0", possibly with leading blanks.
- Advances *str to the next non-alphanumeric.
- Returns 0, or else FAIL (in which case sets inst.error).
-
- (In a future XScale, there may be accumulators other than zero.
- At that time this routine and its callers can be upgraded to suit.) */
-
-static int
-accum0_required_here (str)
- char ** str;
-{
- static char buff [128]; /* Note the address is taken. Hence, static. */
- char * p = * str;
- char c;
- int result = 0; /* The accum number. */
-
- skip_whitespace (p);
-
- *str = p; /* Advance caller's string pointer too. */
- c = *p++;
- while (isalnum (c))
- c = *p++;
-
- *--p = 0; /* Aap nul into input buffer at non-alnum. */
-
- if (! ( streq (*str, "acc0") || streq (*str, "ACC0")))
- {
- sprintf (buff, _("acc0 expected, not '%.100s'"), *str);
- inst.error = buff;
- result = FAIL;
- }
-
- *p = c; /* Unzap. */
- *str = p; /* Caller's string pointer to after match. */
- return result;
-}
-
-/* Expects **str -> after a comma. May be leading blanks.
- Advances *str, recognizing a load mode, and setting inst.instruction.
- Returns rn, or else FAIL (in which case may set inst.error
- and not advance str)
-
- Note: doesn't know Rd, so no err checks that require such knowledge. */
-
-static int
-ld_mode_required_here (string)
- char ** string;
-{
- char * str = * string;
- int rn;
- int pre_inc = 0;
-
- skip_whitespace (str);
-
- if (* str == '[')
- {
- str++;
-
- skip_whitespace (str);
-
- if ((rn = reg_required_here (& str, 16)) == FAIL)
- return FAIL;
-
- skip_whitespace (str);
-
- if (* str == ']')
- {
- str ++;
-
- if (skip_past_comma (& str) == SUCCESS)
- {
- /* [Rn],... (post inc) */
- if (ldst_extend (& str, 1) == FAIL)
- return FAIL;
- }
- else /* [Rn] */
- {
- skip_whitespace (str);
-
- if (* str == '!')
- {
- str ++;
- inst.instruction |= WRITE_BACK;
- }
-
- inst.instruction |= INDEX_UP | HWOFFSET_IMM;
- pre_inc = 1;
- }
- }
- else /* [Rn,...] */
- {
- if (skip_past_comma (& str) == FAIL)
- {
- inst.error = _("pre-indexed expression expected");
- return FAIL;
- }
-
- pre_inc = 1;
-
- if (ldst_extend (& str, 1) == FAIL)
- return FAIL;
-
- skip_whitespace (str);
-
- if (* str ++ != ']')
- {
- inst.error = _("missing ]");
- return FAIL;
- }
-
- skip_whitespace (str);
-
- if (* str == '!')
- {
- str ++;
- inst.instruction |= WRITE_BACK;
- }
- }
- }
- else if (* str == '=') /* ldr's "r,=label" syntax */
- /* We should never reach here, because <text> = <expression> is
- caught gas/read.c read_a_source_file() as a .set operation. */
- return FAIL;
- else /* PC +- 8 bit immediate offset. */
- {
- if (my_get_expression (& inst.reloc.exp, & str))
- return FAIL;
-
- inst.instruction |= HWOFFSET_IMM; /* The I bit. */
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
- inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */
- inst.reloc.pc_rel = 1;
- inst.instruction |= (REG_PC << 16);
-
- rn = REG_PC;
- pre_inc = 1;
- }
-
- inst.instruction |= (pre_inc ? PRE_INDEX : 0);
- * string = str;
-
- return rn;
-}
-
-/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
- SMLAxy{cond} Rd,Rm,Rs,Rn
- SMLAWy{cond} Rd,Rm,Rs,Rn
- Error if any register is R15. */
-
-static void
-do_smla (str, flags)
- char * str;
- unsigned long flags;
-{
- int rd, rm, rs, rn;
-
- skip_whitespace (str);
-
- if ((rd = reg_required_here (& str, 16)) == FAIL
- || skip_past_comma (& str) == FAIL
- || (rm = reg_required_here (& str, 0)) == FAIL
- || skip_past_comma (& str) == FAIL
- || (rs = reg_required_here (& str, 8)) == FAIL
- || skip_past_comma (& str) == FAIL
- || (rn = reg_required_here (& str, 12)) == FAIL)
- inst.error = BAD_ARGS;
-
- else if (rd == REG_PC || rm == REG_PC || rs == REG_PC || rn == REG_PC)
- inst.error = BAD_PC;
-
- else if (flags)
- inst.error = BAD_FLAGS;
-
- else
- end_of_line (str);
-}
-
-/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
- SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
- Error if any register is R15.
- Warning if Rdlo == Rdhi. */
-
-static void
-do_smlal (str, flags)
- char * str;
- unsigned long flags;
-{
- int rdlo, rdhi, rm, rs;
-
- skip_whitespace (str);
-
- if ((rdlo = reg_required_here (& str, 12)) == FAIL
- || skip_past_comma (& str) == FAIL
- || (rdhi = reg_required_here (& str, 16)) == FAIL
- || skip_past_comma (& str) == FAIL
- || (rm = reg_required_here (& str, 0)) == FAIL
- || skip_past_comma (& str) == FAIL
- || (rs = reg_required_here (& str, 8)) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- if (rdlo == REG_PC || rdhi == REG_PC || rm == REG_PC || rs == REG_PC)
- {
- inst.error = BAD_PC;
- return;
- }
-
- if (rdlo == rdhi)
- as_tsktsk (_("rdhi and rdlo must be different"));
-
- if (flags)
- inst.error = BAD_FLAGS;
- else
- end_of_line (str);
-}
-
-/* ARM V5E (El Segundo) signed-multiply (argument parse)
- SMULxy{cond} Rd,Rm,Rs
- Error if any register is R15. */
-
-static void
-do_smul (str, flags)
- char * str;
- unsigned long flags;
-{
- int rd, rm, rs;
-
- skip_whitespace (str);
-
- if ((rd = reg_required_here (& str, 16)) == FAIL
- || skip_past_comma (& str) == FAIL
- || (rm = reg_required_here (& str, 0)) == FAIL
- || skip_past_comma (& str) == FAIL
- || (rs = reg_required_here (& str, 8)) == FAIL)
- inst.error = BAD_ARGS;
-
- else if (rd == REG_PC || rm == REG_PC || rs == REG_PC)
- inst.error = BAD_PC;
-
- else if (flags)
- inst.error = BAD_FLAGS;
-
- else
- end_of_line (str);
-}
-
-/* ARM V5E (El Segundo) saturating-add/subtract (argument parse)
- Q[D]{ADD,SUB}{cond} Rd,Rm,Rn
- Error if any register is R15. */
-
-static void
-do_qadd (str, flags)
- char * str;
- unsigned long flags;
-{
- int rd, rm, rn;
-
- skip_whitespace (str);
-
- if ((rd = reg_required_here (& str, 12)) == FAIL
- || skip_past_comma (& str) == FAIL
- || (rm = reg_required_here (& str, 0)) == FAIL
- || skip_past_comma (& str) == FAIL
- || (rn = reg_required_here (& str, 16)) == FAIL)
- inst.error = BAD_ARGS;
-
- else if (rd == REG_PC || rm == REG_PC || rn == REG_PC)
- inst.error = BAD_PC;
-
- else if (flags)
- inst.error = BAD_FLAGS;
-
- else
- end_of_line (str);
-}
-
-/* ARM V5E (el Segundo)
- MCRRcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
- MRRCcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
-
- These are equivalent to the XScale instructions MAR and MRA,
- respectively, when coproc == 0, opcode == 0, and CRm == 0.
-
- Result unpredicatable if Rd or Rn is R15. */
-
-static void
-do_co_reg2c (str, flags)
- char * str;
- unsigned long flags;
-{
- int rd, rn;
-
- skip_whitespace (str);
-
- if (co_proc_number (& str) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == FAIL
- || cp_opc_expr (& str, 4, 4) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == FAIL
- || (rd = reg_required_here (& str, 12)) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == FAIL
- || (rn = reg_required_here (& str, 16)) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- /* Unpredictable result if rd or rn is R15. */
- if (rd == REG_PC || rn == REG_PC)
- as_tsktsk
- (_("Warning: Instruction unpredictable when using r15"));
-
- if (skip_past_comma (& str) == FAIL
- || cp_reg_required_here (& str, 0) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (flags)
- inst.error = BAD_COND;
-
- end_of_line (str);
-}
-
-/* ARM V5 count-leading-zeroes instruction (argument parse)
- CLZ{<cond>} <Rd>, <Rm>
- Condition defaults to COND_ALWAYS.
- Error if Rd or Rm are R15. */
-
-static void
-do_clz (str, flags)
- char * str;
- unsigned long flags;
-{
- int rd, rm;
-
- if (flags)
- {
- as_bad (BAD_FLAGS);
- return;
- }
-
- skip_whitespace (str);
-
- if (((rd = reg_required_here (& str, 12)) == FAIL)
- || (skip_past_comma (& str) == FAIL)
- || ((rm = reg_required_here (& str, 0)) == FAIL))
- inst.error = BAD_ARGS;
-
- else if (rd == REG_PC || rm == REG_PC )
- inst.error = BAD_PC;
-
- else
- end_of_line (str);
-}
-
-/* ARM V5 (argument parse)
- LDC2{L} <coproc>, <CRd>, <addressing mode>
- STC2{L} <coproc>, <CRd>, <addressing mode>
- Instruction is not conditional, and has 0xf in the codition field.
- Otherwise, it's the same as LDC/STC. */
-
-static void
-do_lstc2 (str, flags)
- char * str;
- unsigned long flags;
-{
- if (flags)
- inst.error = BAD_COND;
-
- skip_whitespace (str);
-
- if (co_proc_number (& str) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- }
- else if (skip_past_comma (& str) == FAIL
- || cp_reg_required_here (& str, 12) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- }
- else if (skip_past_comma (& str) == FAIL
- || cp_address_required_here (& str) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- }
- else
- end_of_line (str);
-}
-
-/* ARM V5 (argument parse)
- CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
- Instruction is not conditional, and has 0xf in the condition field.
- Otherwise, it's the same as CDP. */
-
-static void
-do_cdp2 (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
-
- if (co_proc_number (& str) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == FAIL
- || cp_opc_expr (& str, 20,4) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == FAIL
- || cp_reg_required_here (& str, 12) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == FAIL
- || cp_reg_required_here (& str, 16) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == FAIL
- || cp_reg_required_here (& str, 0) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == SUCCESS)
- {
- if (cp_opc_expr (& str, 5, 3) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
- }
-
- if (flags)
- inst.error = BAD_FLAGS;
-
- end_of_line (str);
-}
-
-/* ARM V5 (argument parse)
- MCR2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
- MRC2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
- Instruction is not conditional, and has 0xf in the condition field.
- Otherwise, it's the same as MCR/MRC. */
-
-static void
-do_co_reg2 (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
-
- if (co_proc_number (& str) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == FAIL
- || cp_opc_expr (& str, 21, 3) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == FAIL
- || reg_required_here (& str, 12) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == FAIL
- || cp_reg_required_here (& str, 16) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == FAIL
- || cp_reg_required_here (& str, 0) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == SUCCESS)
- {
- if (cp_opc_expr (& str, 5, 3) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
- }
-
- if (flags)
- inst.error = BAD_COND;
-
- end_of_line (str);
-}
-
-/* THUMB V5 breakpoint instruction (argument parse)
- BKPT <immed_8>. */
-
-static void
-do_t_bkpt (str)
- char * str;
-{
- expressionS expr;
- unsigned long number;
-
- skip_whitespace (str);
-
- /* Allow optional leading '#'. */
- if (is_immediate_prefix (*str))
- str ++;
-
- memset (& expr, '\0', sizeof (expr));
- if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
- {
- inst.error = _("bad or missing expression");
- return;
- }
-
- number = expr.X_add_number;
-
- /* Check it fits an 8 bit unsigned. */
- if (number != (number & 0xff))
- {
- inst.error = _("immediate value out of range");
- return;
- }
-
- inst.instruction |= number;
-
- end_of_line (str);
-}
-
-/* ARM V5 branch-link-exchange (argument parse) for BLX(1) only.
- Expects inst.instruction is set for BLX(1).
- Note: this is cloned from do_branch, and the reloc changed to be a
- new one that can cope with setting one extra bit (the H bit). */
-
-static void
-do_branch25 (str, flags)
- char * str;
- unsigned long flags ATTRIBUTE_UNUSED;
-{
- if (my_get_expression (& inst.reloc.exp, & str))
- return;
-
-#ifdef OBJ_ELF
- {
- char * save_in;
-
- /* ScottB: February 5, 1998 */
- /* Check to see of PLT32 reloc required for the instruction. */
-
- /* arm_parse_reloc() works on input_line_pointer.
- We actually want to parse the operands to the branch instruction
- passed in 'str'. Save the input pointer and restore it later. */
- save_in = input_line_pointer;
- input_line_pointer = str;
-
- if (inst.reloc.exp.X_op == O_symbol
- && *str == '('
- && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
- {
- inst.reloc.type = BFD_RELOC_ARM_PLT32;
- inst.reloc.pc_rel = 0;
- /* Modify str to point to after parsed operands, otherwise
- end_of_line() will complain about the (PLT) left in str. */
- str = input_line_pointer;
- }
- else
- {
- inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX;
- inst.reloc.pc_rel = 1;
- }
-
- input_line_pointer = save_in;
- }
-#else
- inst.reloc.type = BFD_RELOC_ARM_PCREL_BLX;
- inst.reloc.pc_rel = 1;
-#endif /* OBJ_ELF */
-
- end_of_line (str);
-}
-
-/* ARM V5 branch-link-exchange instruction (argument parse)
- BLX <target_addr> ie BLX(1)
- BLX{<condition>} <Rm> ie BLX(2)
- Unfortunately, there are two different opcodes for this mnemonic.
- So, the insns[].value is not used, and the code here zaps values
- into inst.instruction.
- Also, the <target_addr> can be 25 bits, hence has its own reloc. */
-
-static void
-do_blx (str, flags)
- char * str;
- unsigned long flags;
-{
- char * mystr = str;
- int rm;
-
- if (flags)
- {
- as_bad (BAD_FLAGS);
- return;
- }
-
- skip_whitespace (mystr);
- rm = reg_required_here (& mystr, 0);
-
- /* The above may set inst.error. Ignore his opinion. */
- inst.error = 0;
-
- if (rm != FAIL)
- {
- /* Arg is a register.
- Use the condition code our caller put in inst.instruction.
- Pass ourselves off as a BX with a funny opcode. */
- inst.instruction |= 0x012fff30;
- do_bx (str, flags);
- }
- else
- {
- /* This must be is BLX <target address>, no condition allowed. */
- if (inst.instruction != COND_ALWAYS)
- {
- inst.error = BAD_COND;
- return;
- }
-
- inst.instruction = 0xfafffffe;
-
- /* Process like a B/BL, but with a different reloc.
- Note that B/BL expecte fffffe, not 0, offset in the opcode table. */
- do_branch25 (str, flags);
- }
-}
-
-/* ARM V5 Thumb BLX (argument parse)
- BLX <target_addr> which is BLX(1)
- BLX <Rm> which is BLX(2)
- Unfortunately, there are two different opcodes for this mnemonic.
- So, the tinsns[].value is not used, and the code here zaps values
- into inst.instruction. */
-
-static void
-do_t_blx (str)
- char * str;
-{
- char * mystr = str;
- int rm;
-
- skip_whitespace (mystr);
- inst.instruction = 0x4780;
-
- /* Note that this call is to the ARM register recognizer. BLX(2)
- uses the ARM register space, not the Thumb one, so a call to
- thumb_reg() would be wrong. */
- rm = reg_required_here (& mystr, 3);
- inst.error = 0;
-
- if (rm != FAIL)
- {
- /* It's BLX(2). The .instruction was zapped with rm & is final. */
- inst.size = 2;
- }
- else
- {
- /* No ARM register. This must be BLX(1). Change the .instruction. */
- inst.instruction = 0xf7ffeffe;
- inst.size = 4;
-
- if (my_get_expression (& inst.reloc.exp, & mystr))
- return;
-
- inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
- inst.reloc.pc_rel = 1;
- }
-
- end_of_line (mystr);
-}
-
-/* ARM V5 breakpoint instruction (argument parse)
- BKPT <16 bit unsigned immediate>
- Instruction is not conditional.
- The bit pattern given in insns[] has the COND_ALWAYS condition,
- and it is an error if the caller tried to override that.
- Note "flags" is nonzero if a flag was supplied (which is an error). */
-
-static void
-do_bkpt (str, flags)
- char * str;
- unsigned long flags;
-{
- expressionS expr;
- unsigned long number;
-
- skip_whitespace (str);
-
- /* Allow optional leading '#'. */
- if (is_immediate_prefix (* str))
- str++;
-
- memset (& expr, '\0', sizeof (expr));
-
- if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
- {
- inst.error = _("bad or missing expression");
- return;
- }
-
- number = expr.X_add_number;
-
- /* Check it fits a 16 bit unsigned. */
- if (number != (number & 0xffff))
- {
- inst.error = _("immediate value out of range");
- return;
- }
-
- /* Top 12 of 16 bits to bits 19:8. */
- inst.instruction |= (number & 0xfff0) << 4;
-
- /* Bottom 4 of 16 bits to bits 3:0. */
- inst.instruction |= number & 0xf;
-
- end_of_line (str);
-
- if (flags)
- inst.error = BAD_FLAGS;
-}
-
-/* Xscale multiply-accumulate (argument parse)
- MIAcc acc0,Rm,Rs
- MIAPHcc acc0,Rm,Rs
- MIAxycc acc0,Rm,Rs. */
-
-static void
-do_mia (str, flags)
- char * str;
- unsigned long flags;
-{
- int rs;
- int rm;
-
- if (flags)
- as_bad (BAD_FLAGS);
-
- else if (accum0_required_here (& str) == FAIL)
- inst.error = ERR_NO_ACCUM;
-
- else if (skip_past_comma (& str) == FAIL
- || (rm = reg_required_here (& str, 0)) == FAIL)
- inst.error = BAD_ARGS;
-
- else if (skip_past_comma (& str) == FAIL
- || (rs = reg_required_here (& str, 12)) == FAIL)
- inst.error = BAD_ARGS;
-
- /* inst.instruction has now been zapped with both rm and rs. */
- else if (rm == REG_PC || rs == REG_PC)
- inst.error = BAD_PC; /* Undefined result if rm or rs is R15. */
-
- else
- end_of_line (str);
-}
-
-/* Xscale move-accumulator-register (argument parse)
-
- MARcc acc0,RdLo,RdHi. */
-
-static void
-do_mar (str, flags)
- char * str;
- unsigned long flags;
-{
- int rdlo, rdhi;
-
- if (flags)
- as_bad (BAD_FLAGS);
-
- else if (accum0_required_here (& str) == FAIL)
- inst.error = ERR_NO_ACCUM;
-
- else if (skip_past_comma (& str) == FAIL
- || (rdlo = reg_required_here (& str, 12)) == FAIL)
- inst.error = BAD_ARGS;
-
- else if (skip_past_comma (& str) == FAIL
- || (rdhi = reg_required_here (& str, 16)) == FAIL)
- inst.error = BAD_ARGS;
-
- /* inst.instruction has now been zapped with both rdlo and rdhi. */
- else if (rdlo == REG_PC || rdhi == REG_PC)
- inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */
-
- else
- end_of_line (str);
-}
-
-/* Xscale move-register-accumulator (argument parse)
-
- MRAcc RdLo,RdHi,acc0. */
-
-static void
-do_mra (str, flags)
- char * str;
- unsigned long flags;
-{
- int rdlo;
- int rdhi;
-
- if (flags)
- {
- as_bad (BAD_FLAGS);
- return;
- }
-
- skip_whitespace (str);
-
- if ((rdlo = reg_required_here (& str, 12)) == FAIL)
- inst.error = BAD_ARGS;
-
- else if (skip_past_comma (& str) == FAIL
- || (rdhi = reg_required_here (& str, 16)) == FAIL)
- inst.error = BAD_ARGS;
-
- else if (skip_past_comma (& str) == FAIL
- || accum0_required_here (& str) == FAIL)
- inst.error = ERR_NO_ACCUM;
-
- /* inst.instruction has now been zapped with both rdlo and rdhi. */
- else if (rdlo == rdhi)
- inst.error = BAD_ARGS; /* Undefined result if 2 writes to same reg. */
-
- else if (rdlo == REG_PC || rdhi == REG_PC)
- inst.error = BAD_PC; /* Undefined result if rdlo or rdhi is R15. */
- else
- end_of_line (str);
-}
-
-/* Xscale: Preload-Cache
-
- PLD <addr_mode>
-
- Syntactically, like LDR with B=1, W=0, L=1. */
-
-static void
-do_pld (str, flags)
- char * str;
- unsigned long flags;
-{
- int rd;
-
- if (flags)
- {
- as_bad (BAD_FLAGS);
- return;
- }
-
- skip_whitespace (str);
-
- if (* str != '[')
- {
- inst.error = _("'[' expected after PLD mnemonic");
- return;
- }
-
- ++ str;
- skip_whitespace (str);
-
- if ((rd = reg_required_here (& str, 16)) == FAIL)
- return;
-
- skip_whitespace (str);
-
- if (* str == ']')
- {
- /* [Rn], ... ? */
- ++ str;
- skip_whitespace (str);
-
- if (skip_past_comma (& str) == SUCCESS)
- {
- if (ldst_extend (& str, 0) == FAIL)
- return;
- }
- else if (* str == '!') /* [Rn]! */
- {
- inst.error = _("writeback used in preload instruction");
- ++ str;
- }
- else /* [Rn] */
- inst.instruction |= INDEX_UP | PRE_INDEX;
- }
- else /* [Rn, ...] */
- {
- if (skip_past_comma (& str) == FAIL)
- {
- inst.error = _("pre-indexed expression expected");
- return;
- }
-
- if (ldst_extend (& str, 0) == FAIL)
- return;
-
- skip_whitespace (str);
-
- if (* str != ']')
- {
- inst.error = _("missing ]");
- return;
- }
-
- ++ str;
- skip_whitespace (str);
-
- if (* str == '!') /* [Rn]! */
- {
- inst.error = _("writeback used in preload instruction");
- ++ str;
- }
-
- inst.instruction |= PRE_INDEX;
- }
-
- end_of_line (str);
-}
-
-/* Xscale load-consecutive (argument parse)
- Mode is like LDRH.
-
- LDRccD R, mode
- STRccD R, mode. */
-
-static void
-do_ldrd (str, flags)
- char * str;
- unsigned long flags;
-{
- int rd;
- int rn;
-
- if (flags != DOUBLE_LOAD_FLAG)
- {
- /* Change instruction pattern to normal ldr/str. */
- if (inst.instruction & 0x20)
- inst.instruction = (inst.instruction & COND_MASK) | 0x04000000; /* str */
- else
- inst.instruction = (inst.instruction & COND_MASK) | 0x04100000; /* ldr */
-
- /* Perform a normal load/store instruction parse. */
- do_ldst (str, flags);
-
- return;
- }
-
- if ((cpu_variant & ARM_EXT_XSCALE) != ARM_EXT_XSCALE)
- {
- static char buff[128];
-
- --str;
- while (isspace (*str))
- --str;
- str -= 4;
-
- /* Deny all knowledge. */
- sprintf (buff, _("bad instruction '%.100s'"), str);
- inst.error = buff;
- return;
- }
-
- skip_whitespace (str);
-
- if ((rd = reg_required_here (& str, 12)) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == FAIL
- || (rn = ld_mode_required_here (& str)) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- /* inst.instruction has now been zapped with Rd and the addressing mode. */
- if (rd & 1) /* Unpredictable result if Rd is odd. */
- {
- inst.error = _("Destination register must be even");
- return;
- }
-
- if (rd == REG_LR || rd == 12)
- {
- inst.error = _("r12 or r14 not allowed here");
- return;
- }
-
- if (((rd == rn) || (rd + 1 == rn))
- &&
- ((inst.instruction & WRITE_BACK)
- || (!(inst.instruction & PRE_INDEX))))
- as_warn (_("pre/post-indexing used when modified address register is destination"));
-
- end_of_line (str);
-}
-
-/* Returns the index into fp_values of a floating point number,
- or -1 if not in the table. */
-
-static int
-my_get_float_expression (str)
- char ** str;
-{
- LITTLENUM_TYPE words[MAX_LITTLENUMS];
- char * save_in;
- expressionS exp;
- int i;
- int j;
-
- memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
-
- /* Look for a raw floating point number. */
- if ((save_in = atof_ieee (*str, 'x', words)) != NULL
- && is_end_of_line[(unsigned char) *save_in])
- {
- for (i = 0; i < NUM_FLOAT_VALS; i++)
- {
- for (j = 0; j < MAX_LITTLENUMS; j++)
- {
- if (words[j] != fp_values[i][j])
- break;
- }
-
- if (j == MAX_LITTLENUMS)
- {
- *str = save_in;
- return i;
- }
- }
- }
-
- /* Try and parse a more complex expression, this will probably fail
- unless the code uses a floating point prefix (eg "0f"). */
- save_in = input_line_pointer;
- input_line_pointer = *str;
- if (expression (&exp) == absolute_section
- && exp.X_op == O_big
- && exp.X_add_number < 0)
- {
- /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
- Ditto for 15. */
- if (gen_to_words (words, 5, (long) 15) == 0)
- {
- for (i = 0; i < NUM_FLOAT_VALS; i++)
- {
- for (j = 0; j < MAX_LITTLENUMS; j++)
- {
- if (words[j] != fp_values[i][j])
- break;
- }
-
- if (j == MAX_LITTLENUMS)
- {
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return i;
- }
- }
- }
- }
-
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return -1;
-}
-
-/* Return true if anything in the expression is a bignum. */
-
-static int
-walk_no_bignums (sp)
- symbolS * sp;
-{
- if (symbol_get_value_expression (sp)->X_op == O_big)
- return 1;
-
- if (symbol_get_value_expression (sp)->X_add_symbol)
- {
- return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
- || (symbol_get_value_expression (sp)->X_op_symbol
- && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
- }
-
- return 0;
-}
-
-static int
-my_get_expression (ep, str)
- expressionS * ep;
- char ** str;
-{
- char * save_in;
- segT seg;
-
- save_in = input_line_pointer;
- input_line_pointer = *str;
- seg = expression (ep);
-
-#ifdef OBJ_AOUT
- if (seg != absolute_section
- && seg != text_section
- && seg != data_section
- && seg != bss_section
- && seg != undefined_section)
- {
- inst.error = _("bad_segment");
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return 1;
- }
-#endif
-
- /* Get rid of any bignums now, so that we don't generate an error for which
- we can't establish a line number later on. Big numbers are never valid
- in instructions, which is where this routine is always called. */
- if (ep->X_op == O_big
- || (ep->X_add_symbol
- && (walk_no_bignums (ep->X_add_symbol)
- || (ep->X_op_symbol
- && walk_no_bignums (ep->X_op_symbol)))))
- {
- inst.error = _("Invalid constant");
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return 1;
- }
-
- *str = input_line_pointer;
- input_line_pointer = save_in;
- return 0;
-}
-
-/* UNRESTRICT should be one if <shift> <register> is permitted for this
- instruction. */
-
-static int
-decode_shift (str, unrestrict)
- char ** str;
- int unrestrict;
-{
- const struct asm_shift_name * shift;
- char * p;
- char c;
-
- skip_whitespace (* str);
-
- for (p = * str; isalpha (* p); p ++)
- ;
-
- if (p == * str)
- {
- inst.error = _("Shift expression expected");
- return FAIL;
- }
-
- c = * p;
- * p = '\0';
- shift = (const struct asm_shift_name *) hash_find (arm_shift_hsh, * str);
- * p = c;
-
- if (shift == NULL)
- {
- inst.error = _("Shift expression expected");
- return FAIL;
- }
-
- assert (shift->properties->index == shift_properties[shift->properties->index].index);
-
- if (shift->properties->index == SHIFT_RRX)
- {
- * str = p;
- inst.instruction |= shift->properties->bit_field;
- return SUCCESS;
- }
-
- skip_whitespace (p);
-
- if (unrestrict && reg_required_here (& p, 8) != FAIL)
- {
- inst.instruction |= shift->properties->bit_field | SHIFT_BY_REG;
- * str = p;
- return SUCCESS;
- }
- else if (! is_immediate_prefix (* p))
- {
- inst.error = (unrestrict
- ? _("shift requires register or #expression")
- : _("shift requires #expression"));
- * str = p;
- return FAIL;
- }
-
- inst.error = NULL;
- p ++;
-
- if (my_get_expression (& inst.reloc.exp, & p))
- return FAIL;
-
- /* Validate some simple #expressions. */
- if (inst.reloc.exp.X_op == O_constant)
- {
- unsigned num = inst.reloc.exp.X_add_number;
-
- /* Reject operations greater than 32. */
- if (num > 32
- /* Reject a shift of 0 unless the mode allows it. */
- || (num == 0 && shift->properties->allows_0 == 0)
- /* Reject a shift of 32 unless the mode allows it. */
- || (num == 32 && shift->properties->allows_32 == 0)
- )
- {
- /* As a special case we allow a shift of zero for
- modes that do not support it to be recoded as an
- logical shift left of zero (ie nothing). We warn
- about this though. */
- if (num == 0)
- {
- as_warn (_("Shift of 0 ignored."));
- shift = & shift_names[0];
- assert (shift->properties->index == SHIFT_LSL);
- }
- else
- {
- inst.error = _("Invalid immediate shift");
- return FAIL;
- }
- }
-
- /* Shifts of 32 are encoded as 0, for those shifts that
- support it. */
- if (num == 32)
- num = 0;
-
- inst.instruction |= (num << 7) | shift->properties->bit_field;
- }
- else
- {
- inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
- inst.reloc.pc_rel = 0;
- inst.instruction |= shift->properties->bit_field;
- }
-
- * str = p;
- return SUCCESS;
-}
-
-/* Do those data_ops which can take a negative immediate constant
- by altering the instuction. A bit of a hack really.
- MOV <-> MVN
- AND <-> BIC
- ADC <-> SBC
- by inverting the second operand, and
- ADD <-> SUB
- CMP <-> CMN
- by negating the second operand. */
-
-static int
-negate_data_op (instruction, value)
- unsigned long * instruction;
- unsigned long value;
-{
- int op, new_inst;
- unsigned long negated, inverted;
-
- negated = validate_immediate (-value);
- inverted = validate_immediate (~value);
-
- op = (*instruction >> DATA_OP_SHIFT) & 0xf;
- switch (op)
- {
- /* First negates. */
- case OPCODE_SUB: /* ADD <-> SUB */
- new_inst = OPCODE_ADD;
- value = negated;
- break;
-
- case OPCODE_ADD:
- new_inst = OPCODE_SUB;
- value = negated;
- break;
-
- case OPCODE_CMP: /* CMP <-> CMN */
- new_inst = OPCODE_CMN;
- value = negated;
- break;
-
- case OPCODE_CMN:
- new_inst = OPCODE_CMP;
- value = negated;
- break;
-
- /* Now Inverted ops. */
- case OPCODE_MOV: /* MOV <-> MVN */
- new_inst = OPCODE_MVN;
- value = inverted;
- break;
-
- case OPCODE_MVN:
- new_inst = OPCODE_MOV;
- value = inverted;
- break;
-
- case OPCODE_AND: /* AND <-> BIC */
- new_inst = OPCODE_BIC;
- value = inverted;
- break;
-
- case OPCODE_BIC:
- new_inst = OPCODE_AND;
- value = inverted;
- break;
-
- case OPCODE_ADC: /* ADC <-> SBC */
- new_inst = OPCODE_SBC;
- value = inverted;
- break;
-
- case OPCODE_SBC:
- new_inst = OPCODE_ADC;
- value = inverted;
- break;
-
- /* We cannot do anything. */
- default:
- return FAIL;
- }
-
- if (value == (unsigned) FAIL)
- return FAIL;
-
- *instruction &= OPCODE_MASK;
- *instruction |= new_inst << DATA_OP_SHIFT;
- return value;
-}
-
-static int
-data_op2 (str)
- char ** str;
-{
- int value;
- expressionS expr;
-
- skip_whitespace (* str);
-
- if (reg_required_here (str, 0) != FAIL)
- {
- if (skip_past_comma (str) == SUCCESS)
- /* Shift operation on register. */
- return decode_shift (str, NO_SHIFT_RESTRICT);
-
- return SUCCESS;
- }
- else
- {
- /* Immediate expression. */
- if (is_immediate_prefix (**str))
- {
- (*str)++;
- inst.error = NULL;
-
- if (my_get_expression (&inst.reloc.exp, str))
- return FAIL;
-
- if (inst.reloc.exp.X_add_symbol)
- {
- inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
- inst.reloc.pc_rel = 0;
- }
- else
- {
- if (skip_past_comma (str) == SUCCESS)
- {
- /* #x, y -- ie explicit rotation by Y. */
- if (my_get_expression (&expr, str))
- return FAIL;
-
- if (expr.X_op != O_constant)
- {
- inst.error = _("Constant expression expected");
- return FAIL;
- }
-
- /* Rotate must be a multiple of 2. */
- if (((unsigned) expr.X_add_number) > 30
- || (expr.X_add_number & 1) != 0
- || ((unsigned) inst.reloc.exp.X_add_number) > 255)
- {
- inst.error = _("Invalid constant");
- return FAIL;
- }
- inst.instruction |= INST_IMMEDIATE;
- inst.instruction |= inst.reloc.exp.X_add_number;
- inst.instruction |= expr.X_add_number << 7;
- return SUCCESS;
- }
-
- /* Implicit rotation, select a suitable one. */
- value = validate_immediate (inst.reloc.exp.X_add_number);
-
- if (value == FAIL)
- {
- /* Can't be done. Perhaps the code reads something like
- "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */
- if ((value = negate_data_op (&inst.instruction,
- inst.reloc.exp.X_add_number))
- == FAIL)
- {
- inst.error = _("Invalid constant");
- return FAIL;
- }
- }
-
- inst.instruction |= value;
- }
-
- inst.instruction |= INST_IMMEDIATE;
- return SUCCESS;
- }
-
- (*str)++;
- inst.error = _("Register or shift expression expected");
- return FAIL;
- }
-}
-
-static int
-fp_op2 (str)
- char ** str;
-{
- skip_whitespace (* str);
-
- if (fp_reg_required_here (str, 0) != FAIL)
- return SUCCESS;
- else
- {
- /* Immediate expression. */
- if (*((*str)++) == '#')
- {
- int i;
-
- inst.error = NULL;
-
- skip_whitespace (* str);
-
- /* First try and match exact strings, this is to guarantee
- that some formats will work even for cross assembly. */
-
- for (i = 0; fp_const[i]; i++)
- {
- if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
- {
- char *start = *str;
-
- *str += strlen (fp_const[i]);
- if (is_end_of_line[(unsigned char) **str])
- {
- inst.instruction |= i + 8;
- return SUCCESS;
- }
- *str = start;
- }
- }
-
- /* Just because we didn't get a match doesn't mean that the
- constant isn't valid, just that it is in a format that we
- don't automatically recognize. Try parsing it with
- the standard expression routines. */
- if ((i = my_get_float_expression (str)) >= 0)
- {
- inst.instruction |= i + 8;
- return SUCCESS;
- }
-
- inst.error = _("Invalid floating point immediate expression");
- return FAIL;
- }
- inst.error =
- _("Floating point register or immediate expression expected");
- return FAIL;
- }
-}
-
-static void
-do_arit (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
-
- if (reg_required_here (&str, 12) == FAIL
- || skip_past_comma (&str) == FAIL
- || reg_required_here (&str, 16) == FAIL
- || skip_past_comma (&str) == FAIL
- || data_op2 (&str) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
-
-static void
-do_adr (str, flags)
- char * str;
- unsigned long flags;
-{
- /* This is a pseudo-op of the form "adr rd, label" to be converted
- into a relative address of the form "add rd, pc, #label-.-8". */
- skip_whitespace (str);
-
- if (reg_required_here (&str, 12) == FAIL
- || skip_past_comma (&str) == FAIL
- || my_get_expression (&inst.reloc.exp, &str))
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- /* Frag hacking will turn this into a sub instruction if the offset turns
- out to be negative. */
- inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
- inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
- inst.reloc.pc_rel = 1;
- inst.instruction |= flags;
-
- end_of_line (str);
-}
-
-static void
-do_adrl (str, flags)
- char * str;
- unsigned long flags;
-{
- /* This is a pseudo-op of the form "adrl rd, label" to be converted
- into a relative address of the form:
- add rd, pc, #low(label-.-8)"
- add rd, rd, #high(label-.-8)" */
-
- skip_whitespace (str);
-
- if (reg_required_here (& str, 12) == FAIL
- || skip_past_comma (& str) == FAIL
- || my_get_expression (& inst.reloc.exp, & str))
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- end_of_line (str);
-
- /* Frag hacking will turn this into a sub instruction if the offset turns
- out to be negative. */
- inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
- inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
- inst.reloc.pc_rel = 1;
- inst.instruction |= flags;
- inst.size = INSN_SIZE * 2;
-
- return;
-}
-
-static void
-do_cmp (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
-
- if (reg_required_here (&str, 16) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || data_op2 (&str) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- inst.instruction |= flags;
- if ((flags & 0x0000f000) == 0)
- inst.instruction |= CONDS_BIT;
-
- end_of_line (str);
- return;
-}
-
-static void
-do_mov (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
-
- if (reg_required_here (&str, 12) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || data_op2 (&str) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
-
-static int
-ldst_extend (str, hwse)
- char ** str;
- int hwse;
-{
- int add = INDEX_UP;
-
- switch (**str)
- {
- case '#':
- case '$':
- (*str)++;
- if (my_get_expression (& inst.reloc.exp, str))
- return FAIL;
-
- if (inst.reloc.exp.X_op == O_constant)
- {
- int value = inst.reloc.exp.X_add_number;
-
- if ((hwse && (value < -255 || value > 255))
- || (value < -4095 || value > 4095))
- {
- inst.error = _("address offset too large");
- return FAIL;
- }
-
- if (value < 0)
- {
- value = -value;
- add = 0;
- }
-
- /* Halfword and signextension instructions have the
- immediate value split across bits 11..8 and bits 3..0. */
- if (hwse)
- inst.instruction |= (add | HWOFFSET_IMM
- | ((value >> 4) << 8) | (value & 0xF));
- else
- inst.instruction |= add | value;
- }
- else
- {
- if (hwse)
- {
- inst.instruction |= HWOFFSET_IMM;
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
- }
- else
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
- inst.reloc.pc_rel = 0;
- }
- return SUCCESS;
-
- case '-':
- add = 0;
- /* Fall through. */
-
- case '+':
- (*str)++;
- /* Fall through. */
-
- default:
- if (reg_required_here (str, 0) == FAIL)
- return FAIL;
-
- if (hwse)
- inst.instruction |= add;
- else
- {
- inst.instruction |= add | OFFSET_REG;
- if (skip_past_comma (str) == SUCCESS)
- return decode_shift (str, SHIFT_RESTRICT);
- }
-
- return SUCCESS;
- }
-}
-
-static void
-do_ldst (str, flags)
- char * str;
- unsigned long flags;
-{
- int halfword = 0;
- int pre_inc = 0;
- int conflict_reg;
- int value;
-
- /* This is not ideal, but it is the simplest way of dealing with the
- ARM7T halfword instructions (since they use a different
- encoding, but the same mnemonic): */
- halfword = (flags & 0x80000000) != 0;
- if (halfword)
- {
- /* This is actually a load/store of a halfword, or a
- signed-extension load. */
- if ((cpu_variant & ARM_EXT_HALFWORD) == 0)
- {
- inst.error
- = _("Processor does not support halfwords or signed bytes");
- return;
- }
-
- inst.instruction = ((inst.instruction & COND_MASK)
- | (flags & ~COND_MASK));
-
- flags = 0;
- }
-
- skip_whitespace (str);
-
- if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (& str) == FAIL)
- {
- inst.error = _("Address expected");
- return;
- }
-
- if (*str == '[')
- {
- int reg;
-
- str++;
-
- skip_whitespace (str);
-
- if ((reg = reg_required_here (&str, 16)) == FAIL)
- return;
-
- /* Conflicts can occur on stores as well as loads. */
- conflict_reg = (conflict_reg == reg);
-
- skip_whitespace (str);
-
- if (*str == ']')
- {
- str ++;
-
- if (skip_past_comma (&str) == SUCCESS)
- {
- /* [Rn],... (post inc) */
- if (ldst_extend (&str, halfword) == FAIL)
- return;
- if (conflict_reg)
- {
- if (flags & TRANS_BIT)
- as_warn (_("Rn and Rd must be different in %s"),
- ((inst.instruction & LOAD_BIT)
- ? "LDRT" : "STRT"));
- else
- as_warn (_("%s register same as write-back base"),
- ((inst.instruction & LOAD_BIT)
- ? _("destination") : _("source")));
- }
- }
- else
- {
- /* [Rn] */
- if (halfword)
- inst.instruction |= HWOFFSET_IMM;
-
- skip_whitespace (str);
-
- if (*str == '!')
- {
- if (conflict_reg)
- as_warn (_("%s register same as write-back base"),
- ((inst.instruction & LOAD_BIT)
- ? _("destination") : _("source")));
- str++;
- inst.instruction |= WRITE_BACK;
- }
-
- flags |= INDEX_UP;
- if (flags & TRANS_BIT)
- {
- if (conflict_reg)
- as_warn (_("Rn and Rd must be different in %s"),
- ((inst.instruction & LOAD_BIT)
- ? "LDRT" : "STRT"));
- }
- else
- pre_inc = 1;
- }
- }
- else
- {
- /* [Rn,...] */
- if (skip_past_comma (&str) == FAIL)
- {
- inst.error = _("pre-indexed expression expected");
- return;
- }
-
- pre_inc = 1;
- if (ldst_extend (&str, halfword) == FAIL)
- return;
-
- skip_whitespace (str);
-
- if (*str++ != ']')
- {
- inst.error = _("missing ]");
- return;
- }
-
- skip_whitespace (str);
-
- if (*str == '!')
- {
- if (conflict_reg)
- as_warn (_("%s register same as write-back base"),
- ((inst.instruction & LOAD_BIT)
- ? _("destination") : _("source")));
- str++;
- inst.instruction |= WRITE_BACK;
- }
- }
- }
- else if (*str == '=')
- {
- /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
- str++;
-
- skip_whitespace (str);
-
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
-
- if (inst.reloc.exp.X_op != O_constant
- && inst.reloc.exp.X_op != O_symbol)
- {
- inst.error = _("Constant expression expected");
- return;
- }
-
- if (inst.reloc.exp.X_op == O_constant
- && (value = validate_immediate (inst.reloc.exp.X_add_number)) != FAIL)
- {
- /* This can be done with a mov instruction. */
- inst.instruction &= LITERAL_MASK;
- inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
- inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
- end_of_line (str);
- return;
- }
- else
- {
- /* Insert into literal pool. */
- if (add_to_lit_pool () == FAIL)
- {
- if (!inst.error)
- inst.error = _("literal pool insertion failed");
- return;
- }
-
- /* Change the instruction exp to point to the pool. */
- if (halfword)
- {
- inst.instruction |= HWOFFSET_IMM;
- inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
- }
- else
- inst.reloc.type = BFD_RELOC_ARM_LITERAL;
- inst.reloc.pc_rel = 1;
- inst.instruction |= (REG_PC << 16);
- pre_inc = 1;
- }
- }
- else
- {
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
-
- if (halfword)
- {
- inst.instruction |= HWOFFSET_IMM;
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
- }
- else
- inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
-#ifndef TE_WINCE
- /* PC rel adjust. */
- inst.reloc.exp.X_add_number -= 8;
-#endif
- inst.reloc.pc_rel = 1;
- inst.instruction |= (REG_PC << 16);
- pre_inc = 1;
- }
-
- if (pre_inc && (flags & TRANS_BIT))
- inst.error = _("Pre-increment instruction with translate");
-
- inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
- end_of_line (str);
- return;
-}
-
-static long
-reg_list (strp)
- char ** strp;
-{
- char * str = * strp;
- long range = 0;
- int another_range;
-
- /* We come back here if we get ranges concatenated by '+' or '|'. */
- do
- {
- another_range = 0;
-
- if (*str == '{')
- {
- int in_range = 0;
- int cur_reg = -1;
-
- str++;
- do
- {
- int reg;
-
- skip_whitespace (str);
-
- if ((reg = reg_required_here (& str, -1)) == FAIL)
- return FAIL;
-
- if (in_range)
- {
- int i;
-
- if (reg <= cur_reg)
- {
- inst.error = _("Bad range in register list");
- return FAIL;
- }
-
- for (i = cur_reg + 1; i < reg; i++)
- {
- if (range & (1 << i))
- as_tsktsk
- (_("Warning: Duplicated register (r%d) in register list"),
- i);
- else
- range |= 1 << i;
- }
- in_range = 0;
- }
-
- if (range & (1 << reg))
- as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
- reg);
- else if (reg <= cur_reg)
- as_tsktsk (_("Warning: Register range not in ascending order"));
-
- range |= 1 << reg;
- cur_reg = reg;
- }
- while (skip_past_comma (&str) != FAIL
- || (in_range = 1, *str++ == '-'));
- str--;
- skip_whitespace (str);
-
- if (*str++ != '}')
- {
- inst.error = _("Missing `}'");
- return FAIL;
- }
- }
- else
- {
- expressionS expr;
-
- if (my_get_expression (&expr, &str))
- return FAIL;
-
- if (expr.X_op == O_constant)
- {
- if (expr.X_add_number
- != (expr.X_add_number & 0x0000ffff))
- {
- inst.error = _("invalid register mask");
- return FAIL;
- }
-
- if ((range & expr.X_add_number) != 0)
- {
- int regno = range & expr.X_add_number;
-
- regno &= -regno;
- regno = (1 << regno) - 1;
- as_tsktsk
- (_("Warning: Duplicated register (r%d) in register list"),
- regno);
- }
-
- range |= expr.X_add_number;
- }
- else
- {
- if (inst.reloc.type != 0)
- {
- inst.error = _("expression too complex");
- return FAIL;
- }
-
- memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
- inst.reloc.type = BFD_RELOC_ARM_MULTI;
- inst.reloc.pc_rel = 0;
- }
- }
-
- skip_whitespace (str);
-
- if (*str == '|' || *str == '+')
- {
- str++;
- another_range = 1;
- }
- }
- while (another_range);
-
- *strp = str;
- return range;
-}
-
-static void
-do_ldmstm (str, flags)
- char * str;
- unsigned long flags;
-{
- int base_reg;
- long range;
-
- skip_whitespace (str);
-
- if ((base_reg = reg_required_here (&str, 16)) == FAIL)
- return;
-
- if (base_reg == REG_PC)
- {
- inst.error = _("r15 not allowed as base register");
- return;
- }
-
- skip_whitespace (str);
-
- if (*str == '!')
- {
- flags |= WRITE_BACK;
- str++;
- }
-
- if (skip_past_comma (&str) == FAIL
- || (range = reg_list (&str)) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (*str == '^')
- {
- str++;
- flags |= LDM_TYPE_2_OR_3;
- }
-
- inst.instruction |= flags | range;
- end_of_line (str);
- return;
-}
-
-static void
-do_swi (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
-
- /* Allow optional leading '#'. */
- if (is_immediate_prefix (*str))
- str++;
-
- if (my_get_expression (& inst.reloc.exp, & str))
- return;
-
- inst.reloc.type = BFD_RELOC_ARM_SWI;
- inst.reloc.pc_rel = 0;
- inst.instruction |= flags;
-
- end_of_line (str);
-
- return;
-}
-
-static void
-do_swap (str, flags)
- char * str;
- unsigned long flags;
-{
- int reg;
-
- skip_whitespace (str);
-
- if ((reg = reg_required_here (&str, 12)) == FAIL)
- return;
-
- if (reg == REG_PC)
- {
- inst.error = _("r15 not allowed in swap");
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || (reg = reg_required_here (&str, 0)) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (reg == REG_PC)
- {
- inst.error = _("r15 not allowed in swap");
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || *str++ != '[')
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- skip_whitespace (str);
-
- if ((reg = reg_required_here (&str, 16)) == FAIL)
- return;
-
- if (reg == REG_PC)
- {
- inst.error = BAD_PC;
- return;
- }
-
- skip_whitespace (str);
-
- if (*str++ != ']')
- {
- inst.error = _("missing ]");
- return;
- }
-
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
-
-static void
-do_branch (str, flags)
- char * str;
- unsigned long flags ATTRIBUTE_UNUSED;
-{
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
-
-#ifdef OBJ_ELF
- {
- char * save_in;
-
- /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
- required for the instruction. */
-
- /* arm_parse_reloc () works on input_line_pointer.
- We actually want to parse the operands to the branch instruction
- passed in 'str'. Save the input pointer and restore it later. */
- save_in = input_line_pointer;
- input_line_pointer = str;
- if (inst.reloc.exp.X_op == O_symbol
- && *str == '('
- && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
- {
- inst.reloc.type = BFD_RELOC_ARM_PLT32;
- inst.reloc.pc_rel = 0;
- /* Modify str to point to after parsed operands, otherwise
- end_of_line() will complain about the (PLT) left in str. */
- str = input_line_pointer;
- }
- else
- {
- inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
- inst.reloc.pc_rel = 1;
- }
- input_line_pointer = save_in;
- }
-#else
- inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
- inst.reloc.pc_rel = 1;
-#endif /* OBJ_ELF */
-
- end_of_line (str);
- return;
-}
-
-static void
-do_bx (str, flags)
- char * str;
- unsigned long flags ATTRIBUTE_UNUSED;
-{
- int reg;
-
- skip_whitespace (str);
-
- if ((reg = reg_required_here (&str, 0)) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- /* Note - it is not illegal to do a "bx pc". Useless, but not illegal. */
- if (reg == REG_PC)
- as_tsktsk (_("Use of r15 in bx in ARM mode is not really useful"));
-
- end_of_line (str);
-}
-
-static void
-do_cdp (str, flags)
- char * str;
- unsigned long flags ATTRIBUTE_UNUSED;
-{
- /* Co-processor data operation.
- Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
- skip_whitespace (str);
-
- if (co_proc_number (&str) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || cp_opc_expr (&str, 20,4) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 12) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 16) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 0) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == SUCCESS)
- {
- if (cp_opc_expr (&str, 5, 3) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
- }
-
- end_of_line (str);
- return;
-}
-
-static void
-do_lstc (str, flags)
- char * str;
- unsigned long flags;
-{
- /* Co-processor register load/store.
- Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
-
- skip_whitespace (str);
-
- if (co_proc_number (&str) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 12) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || cp_address_required_here (&str) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
-
-static void
-do_co_reg (str, flags)
- char * str;
- unsigned long flags;
-{
- /* Co-processor register transfer.
- Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
-
- skip_whitespace (str);
-
- if (co_proc_number (&str) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || cp_opc_expr (&str, 21, 3) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || reg_required_here (&str, 12) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 16) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || cp_reg_required_here (&str, 0) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == SUCCESS)
- {
- if (cp_opc_expr (&str, 5, 3) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
- }
- if (flags)
- {
- inst.error = BAD_COND;
- }
-
- end_of_line (str);
- return;
-}
-
-static void
-do_fp_ctrl (str, flags)
- char * str;
- unsigned long flags ATTRIBUTE_UNUSED;
-{
- /* FP control registers.
- Format: <WFS|RFS|WFC|RFC>{cond} Rn */
-
- skip_whitespace (str);
-
- if (reg_required_here (&str, 12) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- end_of_line (str);
- return;
-}
-
-static void
-do_fp_ldst (str, flags)
- char * str;
- unsigned long flags ATTRIBUTE_UNUSED;
-{
- skip_whitespace (str);
-
- switch (inst.suffix)
- {
- case SUFF_S:
- break;
- case SUFF_D:
- inst.instruction |= CP_T_X;
- break;
- case SUFF_E:
- inst.instruction |= CP_T_Y;
- break;
- case SUFF_P:
- inst.instruction |= CP_T_X | CP_T_Y;
- break;
- default:
- abort ();
- }
-
- if (fp_reg_required_here (&str, 12) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || cp_address_required_here (&str) == FAIL)
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- end_of_line (str);
-}
-
-static void
-do_fp_ldmstm (str, flags)
- char * str;
- unsigned long flags;
-{
- int num_regs;
-
- skip_whitespace (str);
-
- if (fp_reg_required_here (&str, 12) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- /* Get Number of registers to transfer. */
- if (skip_past_comma (&str) == FAIL
- || my_get_expression (&inst.reloc.exp, &str))
- {
- if (! inst.error)
- inst.error = _("constant expression expected");
- return;
- }
-
- if (inst.reloc.exp.X_op != O_constant)
- {
- inst.error = _("Constant value required for number of registers");
- return;
- }
-
- num_regs = inst.reloc.exp.X_add_number;
-
- if (num_regs < 1 || num_regs > 4)
- {
- inst.error = _("number of registers must be in the range [1:4]");
- return;
- }
-
- switch (num_regs)
- {
- case 1:
- inst.instruction |= CP_T_X;
- break;
- case 2:
- inst.instruction |= CP_T_Y;
- break;
- case 3:
- inst.instruction |= CP_T_Y | CP_T_X;
- break;
- case 4:
- break;
- default:
- abort ();
- }
-
- if (flags)
- {
- int reg;
- int write_back;
- int offset;
-
- /* The instruction specified "ea" or "fd", so we can only accept
- [Rn]{!}. The instruction does not really support stacking or
- unstacking, so we have to emulate these by setting appropriate
- bits and offsets. */
- if (skip_past_comma (&str) == FAIL
- || *str != '[')
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- str++;
- skip_whitespace (str);
-
- if ((reg = reg_required_here (&str, 16)) == FAIL)
- return;
-
- skip_whitespace (str);
-
- if (*str != ']')
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- str++;
- if (*str == '!')
- {
- write_back = 1;
- str++;
- if (reg == REG_PC)
- {
- inst.error =
- _("R15 not allowed as base register with write-back");
- return;
- }
- }
- else
- write_back = 0;
-
- if (flags & CP_T_Pre)
- {
- /* Pre-decrement. */
- offset = 3 * num_regs;
- if (write_back)
- flags |= CP_T_WB;
- }
- else
- {
- /* Post-increment. */
- if (write_back)
- {
- flags |= CP_T_WB;
- offset = 3 * num_regs;
- }
- else
- {
- /* No write-back, so convert this into a standard pre-increment
- instruction -- aesthetically more pleasing. */
- flags = CP_T_Pre | CP_T_UD;
- offset = 0;
- }
- }
-
- inst.instruction |= flags | offset;
- }
- else if (skip_past_comma (&str) == FAIL
- || cp_address_required_here (&str) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- end_of_line (str);
-}
-
-static void
-do_fp_dyadic (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
-
- switch (inst.suffix)
- {
- case SUFF_S:
- break;
- case SUFF_D:
- inst.instruction |= 0x00000080;
- break;
- case SUFF_E:
- inst.instruction |= 0x00080000;
- break;
- default:
- abort ();
- }
-
- if (fp_reg_required_here (&str, 12) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || fp_reg_required_here (&str, 16) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || fp_op2 (&str) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
-
-static void
-do_fp_monadic (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
-
- switch (inst.suffix)
- {
- case SUFF_S:
- break;
- case SUFF_D:
- inst.instruction |= 0x00000080;
- break;
- case SUFF_E:
- inst.instruction |= 0x00080000;
- break;
- default:
- abort ();
- }
-
- if (fp_reg_required_here (&str, 12) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || fp_op2 (&str) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
-
-static void
-do_fp_cmp (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
-
- if (fp_reg_required_here (&str, 16) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || fp_op2 (&str) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
-
-static void
-do_fp_from_reg (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
-
- switch (inst.suffix)
- {
- case SUFF_S:
- break;
- case SUFF_D:
- inst.instruction |= 0x00000080;
- break;
- case SUFF_E:
- inst.instruction |= 0x00080000;
- break;
- default:
- abort ();
- }
-
- if (fp_reg_required_here (&str, 16) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) == FAIL
- || reg_required_here (&str, 12) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
-
-static void
-do_fp_to_reg (str, flags)
- char * str;
- unsigned long flags;
-{
- skip_whitespace (str);
-
- if (reg_required_here (&str, 12) == FAIL)
- return;
-
- if (skip_past_comma (&str) == FAIL
- || fp_reg_required_here (&str, 0) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- inst.instruction |= flags;
- end_of_line (str);
- return;
-}
-
-/* Thumb specific routines. */
-
-/* Parse and validate that a register is of the right form, this saves
- repeated checking of this information in many similar cases.
- Unlike the 32-bit case we do not insert the register into the opcode
- here, since the position is often unknown until the full instruction
- has been parsed. */
-
-static int
-thumb_reg (strp, hi_lo)
- char ** strp;
- int hi_lo;
-{
- int reg;
-
- if ((reg = reg_required_here (strp, -1)) == FAIL)
- return FAIL;
-
- switch (hi_lo)
- {
- case THUMB_REG_LO:
- if (reg > 7)
- {
- inst.error = _("lo register required");
- return FAIL;
- }
- break;
-
- case THUMB_REG_HI:
- if (reg < 8)
- {
- inst.error = _("hi register required");
- return FAIL;
- }
- break;
-
- default:
- break;
- }
-
- return reg;
-}
-
-/* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
- was SUB. */
-
-static void
-thumb_add_sub (str, subtract)
- char * str;
- int subtract;
-{
- int Rd, Rs, Rn = FAIL;
-
- skip_whitespace (str);
-
- if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
- || skip_past_comma (&str) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (is_immediate_prefix (*str))
- {
- Rs = Rd;
- str++;
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
- }
- else
- {
- if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
- return;
-
- if (skip_past_comma (&str) == FAIL)
- {
- /* Two operand format, shuffle the registers
- and pretend there are 3. */
- Rn = Rs;
- Rs = Rd;
- }
- else if (is_immediate_prefix (*str))
- {
- str++;
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
- }
- else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
- return;
- }
-
- /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
- for the latter case, EXPR contains the immediate that was found. */
- if (Rn != FAIL)
- {
- /* All register format. */
- if (Rd > 7 || Rs > 7 || Rn > 7)
- {
- if (Rs != Rd)
- {
- inst.error = _("dest and source1 must be the same register");
- return;
- }
-
- /* Can't do this for SUB. */
- if (subtract)
- {
- inst.error = _("subtract valid only on lo regs");
- return;
- }
-
- inst.instruction = (T_OPCODE_ADD_HI
- | (Rd > 7 ? THUMB_H1 : 0)
- | (Rn > 7 ? THUMB_H2 : 0));
- inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
- }
- else
- {
- inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
- inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
- }
- }
- else
- {
- /* Immediate expression, now things start to get nasty. */
-
- /* First deal with HI regs, only very restricted cases allowed:
- Adjusting SP, and using PC or SP to get an address. */
- if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
- || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
- {
- inst.error = _("invalid Hi register with immediate");
- return;
- }
-
- if (inst.reloc.exp.X_op != O_constant)
- {
- /* Value isn't known yet, all we can do is store all the fragments
- we know about in the instruction and let the reloc hacking
- work it all out. */
- inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
- inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
- }
- else
- {
- int offset = inst.reloc.exp.X_add_number;
-
- if (subtract)
- offset = -offset;
-
- if (offset < 0)
- {
- offset = -offset;
- subtract = 1;
-
- /* Quick check, in case offset is MIN_INT. */
- if (offset < 0)
- {
- inst.error = _("immediate value out of range");
- return;
- }
- }
- else
- subtract = 0;
-
- if (Rd == REG_SP)
- {
- if (offset & ~0x1fc)
- {
- inst.error = _("invalid immediate value for stack adjust");
- return;
- }
- inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
- inst.instruction |= offset >> 2;
- }
- else if (Rs == REG_PC || Rs == REG_SP)
- {
- if (subtract
- || (offset & ~0x3fc))
- {
- inst.error = _("invalid immediate for address calculation");
- return;
- }
- inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
- : T_OPCODE_ADD_SP);
- inst.instruction |= (Rd << 8) | (offset >> 2);
- }
- else if (Rs == Rd)
- {
- if (offset & ~0xff)
- {
- inst.error = _("immediate value out of range");
- return;
- }
- inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
- inst.instruction |= (Rd << 8) | offset;
- }
- else
- {
- if (offset & ~0x7)
- {
- inst.error = _("immediate value out of range");
- return;
- }
- inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
- inst.instruction |= Rd | (Rs << 3) | (offset << 6);
- }
- }
- }
-
- end_of_line (str);
-}
-
-static void
-thumb_shift (str, shift)
- char * str;
- int shift;
-{
- int Rd, Rs, Rn = FAIL;
-
- skip_whitespace (str);
-
- if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
- || skip_past_comma (&str) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (is_immediate_prefix (*str))
- {
- /* Two operand immediate format, set Rs to Rd. */
- Rs = Rd;
- str ++;
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
- }
- else
- {
- if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
- return;
-
- if (skip_past_comma (&str) == FAIL)
- {
- /* Two operand format, shuffle the registers
- and pretend there are 3. */
- Rn = Rs;
- Rs = Rd;
- }
- else if (is_immediate_prefix (*str))
- {
- str++;
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
- }
- else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
- return;
- }
-
- /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
- for the latter case, EXPR contains the immediate that was found. */
-
- if (Rn != FAIL)
- {
- if (Rs != Rd)
- {
- inst.error = _("source1 and dest must be same register");
- return;
- }
-
- switch (shift)
- {
- case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
- case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
- case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
- }
-
- inst.instruction |= Rd | (Rn << 3);
- }
- else
- {
- switch (shift)
- {
- case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
- case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
- case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
- }
-
- if (inst.reloc.exp.X_op != O_constant)
- {
- /* Value isn't known yet, create a dummy reloc and let reloc
- hacking fix it up. */
- inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
- }
- else
- {
- unsigned shift_value = inst.reloc.exp.X_add_number;
-
- if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
- {
- inst.error = _("Invalid immediate for shift");
- return;
- }
-
- /* Shifts of zero are handled by converting to LSL. */
- if (shift_value == 0)
- inst.instruction = T_OPCODE_LSL_I;
-
- /* Shifts of 32 are encoded as a shift of zero. */
- if (shift_value == 32)
- shift_value = 0;
-
- inst.instruction |= shift_value << 6;
- }
-
- inst.instruction |= Rd | (Rs << 3);
- }
-
- end_of_line (str);
-}
-
-static void
-thumb_mov_compare (str, move)
- char * str;
- int move;
-{
- int Rd, Rs = FAIL;
-
- skip_whitespace (str);
-
- if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
- || skip_past_comma (&str) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (is_immediate_prefix (*str))
- {
- str++;
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
- }
- else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
- return;
-
- if (Rs != FAIL)
- {
- if (Rs < 8 && Rd < 8)
- {
- if (move == THUMB_MOVE)
- /* A move of two lowregs is encoded as ADD Rd, Rs, #0
- since a MOV instruction produces unpredictable results. */
- inst.instruction = T_OPCODE_ADD_I3;
- else
- inst.instruction = T_OPCODE_CMP_LR;
- inst.instruction |= Rd | (Rs << 3);
- }
- else
- {
- if (move == THUMB_MOVE)
- inst.instruction = T_OPCODE_MOV_HR;
- else
- inst.instruction = T_OPCODE_CMP_HR;
-
- if (Rd > 7)
- inst.instruction |= THUMB_H1;
-
- if (Rs > 7)
- inst.instruction |= THUMB_H2;
-
- inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
- }
- }
- else
- {
- if (Rd > 7)
- {
- inst.error = _("only lo regs allowed with immediate");
- return;
- }
-
- if (move == THUMB_MOVE)
- inst.instruction = T_OPCODE_MOV_I8;
- else
- inst.instruction = T_OPCODE_CMP_I8;
-
- inst.instruction |= Rd << 8;
-
- if (inst.reloc.exp.X_op != O_constant)
- inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
- else
- {
- unsigned value = inst.reloc.exp.X_add_number;
-
- if (value > 255)
- {
- inst.error = _("invalid immediate");
- return;
- }
-
- inst.instruction |= value;
- }
- }
-
- end_of_line (str);
-}
-
-static void
-thumb_load_store (str, load_store, size)
- char * str;
- int load_store;
- int size;
-{
- int Rd, Rb, Ro = FAIL;
-
- skip_whitespace (str);
-
- if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
- || skip_past_comma (&str) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (*str == '[')
- {
- str++;
- if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
- return;
-
- if (skip_past_comma (&str) != FAIL)
- {
- if (is_immediate_prefix (*str))
- {
- str++;
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
- }
- else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
- return;
- }
- else
- {
- inst.reloc.exp.X_op = O_constant;
- inst.reloc.exp.X_add_number = 0;
- }
-
- if (*str != ']')
- {
- inst.error = _("expected ']'");
- return;
- }
- str++;
- }
- else if (*str == '=')
- {
- /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
- str++;
-
- skip_whitespace (str);
-
- if (my_get_expression (& inst.reloc.exp, & str))
- return;
-
- end_of_line (str);
-
- if ( inst.reloc.exp.X_op != O_constant
- && inst.reloc.exp.X_op != O_symbol)
- {
- inst.error = "Constant expression expected";
- return;
- }
-
- if (inst.reloc.exp.X_op == O_constant
- && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
- {
- /* This can be done with a mov instruction. */
-
- inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
- inst.instruction |= inst.reloc.exp.X_add_number;
- return;
- }
-
- /* Insert into literal pool. */
- if (add_to_lit_pool () == FAIL)
- {
- if (!inst.error)
- inst.error = "literal pool insertion failed";
- return;
- }
-
- inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
- inst.reloc.pc_rel = 1;
- inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
- /* Adjust ARM pipeline offset to Thumb. */
- inst.reloc.exp.X_add_number += 4;
-
- return;
- }
- else
- {
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
-
- inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
- inst.reloc.pc_rel = 1;
- inst.reloc.exp.X_add_number -= 4; /* Pipeline offset. */
- inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
- end_of_line (str);
- return;
- }
-
- if (Rb == REG_PC || Rb == REG_SP)
- {
- if (size != THUMB_WORD)
- {
- inst.error = _("byte or halfword not valid for base register");
- return;
- }
- else if (Rb == REG_PC && load_store != THUMB_LOAD)
- {
- inst.error = _("R15 based store not allowed");
- return;
- }
- else if (Ro != FAIL)
- {
- inst.error = _("Invalid base register for register offset");
- return;
- }
-
- if (Rb == REG_PC)
- inst.instruction = T_OPCODE_LDR_PC;
- else if (load_store == THUMB_LOAD)
- inst.instruction = T_OPCODE_LDR_SP;
- else
- inst.instruction = T_OPCODE_STR_SP;
-
- inst.instruction |= Rd << 8;
- if (inst.reloc.exp.X_op == O_constant)
- {
- unsigned offset = inst.reloc.exp.X_add_number;
-
- if (offset & ~0x3fc)
- {
- inst.error = _("invalid offset");
- return;
- }
-
- inst.instruction |= offset >> 2;
- }
- else
- inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
- }
- else if (Rb > 7)
- {
- inst.error = _("invalid base register in load/store");
- return;
- }
- else if (Ro == FAIL)
- {
- /* Immediate offset. */
- if (size == THUMB_WORD)
- inst.instruction = (load_store == THUMB_LOAD
- ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
- else if (size == THUMB_HALFWORD)
- inst.instruction = (load_store == THUMB_LOAD
- ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
- else
- inst.instruction = (load_store == THUMB_LOAD
- ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
-
- inst.instruction |= Rd | (Rb << 3);
-
- if (inst.reloc.exp.X_op == O_constant)
- {
- unsigned offset = inst.reloc.exp.X_add_number;
-
- if (offset & ~(0x1f << size))
- {
- inst.error = _("Invalid offset");
- return;
- }
- inst.instruction |= (offset >> size) << 6;
- }
- else
- inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
- }
- else
- {
- /* Register offset. */
- if (size == THUMB_WORD)
- inst.instruction = (load_store == THUMB_LOAD
- ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
- else if (size == THUMB_HALFWORD)
- inst.instruction = (load_store == THUMB_LOAD
- ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
- else
- inst.instruction = (load_store == THUMB_LOAD
- ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
-
- inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
- }
-
- end_of_line (str);
-}
-
-static void
-do_t_nop (str)
- char * str;
-{
- /* Do nothing. */
- end_of_line (str);
- return;
-}
-
-/* Handle the Format 4 instructions that do not have equivalents in other
- formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
- BIC and MVN. */
-
-static void
-do_t_arit (str)
- char * str;
-{
- int Rd, Rs, Rn;
-
- skip_whitespace (str);
-
- if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
- || skip_past_comma (&str) == FAIL
- || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- if (skip_past_comma (&str) != FAIL)
- {
- /* Three operand format not allowed for TST, CMN, NEG and MVN.
- (It isn't allowed for CMP either, but that isn't handled by this
- function.) */
- if (inst.instruction == T_OPCODE_TST
- || inst.instruction == T_OPCODE_CMN
- || inst.instruction == T_OPCODE_NEG
- || inst.instruction == T_OPCODE_MVN)
- {
- inst.error = BAD_ARGS;
- return;
- }
-
- if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
- return;
-
- if (Rs != Rd)
- {
- inst.error = _("dest and source1 must be the same register");
- return;
- }
- Rs = Rn;
- }
-
- if (inst.instruction == T_OPCODE_MUL
- && Rs == Rd)
- as_tsktsk (_("Rs and Rd must be different in MUL"));
-
- inst.instruction |= Rd | (Rs << 3);
- end_of_line (str);
-}
-
-static void
-do_t_add (str)
- char * str;
-{
- thumb_add_sub (str, 0);
-}
-
-static void
-do_t_asr (str)
- char * str;
-{
- thumb_shift (str, THUMB_ASR);
-}
-
-static void
-do_t_branch9 (str)
- char * str;
-{
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
- inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
- inst.reloc.pc_rel = 1;
- end_of_line (str);
-}
-
-static void
-do_t_branch12 (str)
- char * str;
-{
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
- inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
- inst.reloc.pc_rel = 1;
- end_of_line (str);
-}
-
-/* Find the real, Thumb encoded start of a Thumb function. */
-
-static symbolS *
-find_real_start (symbolP)
- symbolS * symbolP;
-{
- char * real_start;
- const char * name = S_GET_NAME (symbolP);
- symbolS * new_target;
-
- /* This definiton must agree with the one in gcc/config/arm/thumb.c. */
-#define STUB_NAME ".real_start_of"
-
- if (name == NULL)
- abort ();
-
- /* Names that start with '.' are local labels, not function entry points.
- The compiler may generate BL instructions to these labels because it
- needs to perform a branch to a far away location. */
- if (name[0] == '.')
- return symbolP;
-
- real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
- sprintf (real_start, "%s%s", STUB_NAME, name);
-
- new_target = symbol_find (real_start);
-
- if (new_target == NULL)
- {
- as_warn ("Failed to find real start of function: %s\n", name);
- new_target = symbolP;
- }
-
- free (real_start);
-
- return new_target;
-}
-
-static void
-do_t_branch23 (str)
- char * str;
-{
- if (my_get_expression (& inst.reloc.exp, & str))
- return;
-
- inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
- inst.reloc.pc_rel = 1;
- end_of_line (str);
-
- /* If the destination of the branch is a defined symbol which does not have
- the THUMB_FUNC attribute, then we must be calling a function which has
- the (interfacearm) attribute. We look for the Thumb entry point to that
- function and change the branch to refer to that function instead. */
- if ( inst.reloc.exp.X_op == O_symbol
- && inst.reloc.exp.X_add_symbol != NULL
- && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
- && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
- inst.reloc.exp.X_add_symbol =
- find_real_start (inst.reloc.exp.X_add_symbol);
-}
-
-static void
-do_t_bx (str)
- char * str;
-{
- int reg;
-
- skip_whitespace (str);
-
- if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
- return;
-
- /* This sets THUMB_H2 from the top bit of reg. */
- inst.instruction |= reg << 3;
-
- /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
- should cause the alignment to be checked once it is known. This is
- because BX PC only works if the instruction is word aligned. */
-
- end_of_line (str);
-}
-
-static void
-do_t_compare (str)
- char * str;
-{
- thumb_mov_compare (str, THUMB_COMPARE);
-}
-
-static void
-do_t_ldmstm (str)
- char * str;
-{
- int Rb;
- long range;
-
- skip_whitespace (str);
-
- if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
- return;
-
- if (*str != '!')
- as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
- else
- str++;
-
- if (skip_past_comma (&str) == FAIL
- || (range = reg_list (&str)) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (inst.reloc.type != BFD_RELOC_NONE)
- {
- /* This really doesn't seem worth it. */
- inst.reloc.type = BFD_RELOC_NONE;
- inst.error = _("Expression too complex");
- return;
- }
-
- if (range & ~0xff)
- {
- inst.error = _("only lo-regs valid in load/store multiple");
- return;
- }
-
- inst.instruction |= (Rb << 8) | range;
- end_of_line (str);
-}
-
-static void
-do_t_ldr (str)
- char * str;
-{
- thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
-}
-
-static void
-do_t_ldrb (str)
- char * str;
-{
- thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
-}
-
-static void
-do_t_ldrh (str)
- char * str;
-{
- thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
-}
-
-static void
-do_t_lds (str)
- char * str;
-{
- int Rd, Rb, Ro;
-
- skip_whitespace (str);
-
- if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
- || skip_past_comma (&str) == FAIL
- || *str++ != '['
- || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
- || skip_past_comma (&str) == FAIL
- || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
- || *str++ != ']')
- {
- if (! inst.error)
- inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
- return;
- }
-
- inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
- end_of_line (str);
-}
-
-static void
-do_t_lsl (str)
- char * str;
-{
- thumb_shift (str, THUMB_LSL);
-}
-
-static void
-do_t_lsr (str)
- char * str;
-{
- thumb_shift (str, THUMB_LSR);
-}
-
-static void
-do_t_mov (str)
- char * str;
-{
- thumb_mov_compare (str, THUMB_MOVE);
-}
-
-static void
-do_t_push_pop (str)
- char * str;
-{
- long range;
-
- skip_whitespace (str);
-
- if ((range = reg_list (&str)) == FAIL)
- {
- if (! inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- if (inst.reloc.type != BFD_RELOC_NONE)
- {
- /* This really doesn't seem worth it. */
- inst.reloc.type = BFD_RELOC_NONE;
- inst.error = _("Expression too complex");
- return;
- }
-
- if (range & ~0xff)
- {
- if ((inst.instruction == T_OPCODE_PUSH
- && (range & ~0xff) == 1 << REG_LR)
- || (inst.instruction == T_OPCODE_POP
- && (range & ~0xff) == 1 << REG_PC))
- {
- inst.instruction |= THUMB_PP_PC_LR;
- range &= 0xff;
- }
- else
- {
- inst.error = _("invalid register list to push/pop instruction");
- return;
- }
- }
-
- inst.instruction |= range;
- end_of_line (str);
-}
-
-static void
-do_t_str (str)
- char * str;
-{
- thumb_load_store (str, THUMB_STORE, THUMB_WORD);
-}
-
-static void
-do_t_strb (str)
- char * str;
-{
- thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
-}
-
-static void
-do_t_strh (str)
- char * str;
-{
- thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
-}
-
-static void
-do_t_sub (str)
- char * str;
-{
- thumb_add_sub (str, 1);
-}
-
-static void
-do_t_swi (str)
- char * str;
-{
- skip_whitespace (str);
-
- if (my_get_expression (&inst.reloc.exp, &str))
- return;
-
- inst.reloc.type = BFD_RELOC_ARM_SWI;
- end_of_line (str);
- return;
-}
-
-static void
-do_t_adr (str)
- char * str;
-{
- int reg;
-
- /* This is a pseudo-op of the form "adr rd, label" to be converted
- into a relative address of the form "add rd, pc, #label-.-4". */
- skip_whitespace (str);
-
- /* Store Rd in temporary location inside instruction. */
- if ((reg = reg_required_here (&str, 4)) == FAIL
- || (reg > 7) /* For Thumb reg must be r0..r7. */
- || skip_past_comma (&str) == FAIL
- || my_get_expression (&inst.reloc.exp, &str))
- {
- if (!inst.error)
- inst.error = BAD_ARGS;
- return;
- }
-
- inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
- inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
- inst.reloc.pc_rel = 1;
- inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */
-
- end_of_line (str);
-}
-
-static void
-insert_reg (entry)
- int entry;
-{
- int len = strlen (reg_table[entry].name) + 2;
- char * buf = (char *) xmalloc (len);
- char * buf2 = (char *) xmalloc (len);
- int i = 0;
-
-#ifdef REGISTER_PREFIX
- buf[i++] = REGISTER_PREFIX;
-#endif
-
- strcpy (buf + i, reg_table[entry].name);
-
- for (i = 0; buf[i]; i++)
- buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
-
- buf2[i] = '\0';
-
- hash_insert (arm_reg_hsh, buf, (PTR) & reg_table[entry]);
- hash_insert (arm_reg_hsh, buf2, (PTR) & reg_table[entry]);
-}
-
-static void
-insert_reg_alias (str, regnum)
- char *str;
- int regnum;
-{
- struct reg_entry *new =
- (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
- char *name = xmalloc (strlen (str) + 1);
- strcpy (name, str);
-
- new->name = name;
- new->number = regnum;
-
- hash_insert (arm_reg_hsh, name, (PTR) new);
-}
-
-static void
-set_constant_flonums ()
-{
- int i;
-
- for (i = 0; i < NUM_FLOAT_VALS; i++)
- if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
- abort ();
-}
-
-void
-md_begin ()
-{
- unsigned mach;
- unsigned int i;
-
- if ( (arm_ops_hsh = hash_new ()) == NULL
- || (arm_tops_hsh = hash_new ()) == NULL
- || (arm_cond_hsh = hash_new ()) == NULL
- || (arm_shift_hsh = hash_new ()) == NULL
- || (arm_reg_hsh = hash_new ()) == NULL
- || (arm_psr_hsh = hash_new ()) == NULL)
- as_fatal (_("Virtual memory exhausted"));
-
- for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
- hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
- for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
- hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
- for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
- hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
- for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
- hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
- for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
- hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
-
- for (i = 0; reg_table[i].name; i++)
- insert_reg (i);
-
- set_constant_flonums ();
-
-#if defined OBJ_COFF || defined OBJ_ELF
- {
- unsigned int flags = 0;
-
- /* Set the flags in the private structure. */
- if (uses_apcs_26) flags |= F_APCS26;
- if (support_interwork) flags |= F_INTERWORK;
- if (uses_apcs_float) flags |= F_APCS_FLOAT;
- if (pic_code) flags |= F_PIC;
- if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
-
- bfd_set_private_flags (stdoutput, flags);
-
- /* We have run out flags in the COFF header to encode the
- status of ATPCS support, so instead we create a dummy,
- empty, debug section called .arm.atpcs. */
- if (atpcs)
- {
- asection * sec;
-
- sec = bfd_make_section (stdoutput, ".arm.atpcs");
-
- if (sec != NULL)
- {
- bfd_set_section_flags
- (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
- bfd_set_section_size (stdoutput, sec, 0);
- bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
- }
- }
- }
-#endif
-
- /* Record the CPU type as well. */
- switch (cpu_variant & ARM_CPU_MASK)
- {
- case ARM_2:
- mach = bfd_mach_arm_2;
- break;
-
- case ARM_3: /* Also ARM_250. */
- mach = bfd_mach_arm_2a;
- break;
-
- default:
- case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined. */
- mach = bfd_mach_arm_4;
- break;
-
- case ARM_7: /* Also ARM_6. */
- mach = bfd_mach_arm_3;
- break;
- }
-
- /* Catch special cases. */
- if (cpu_variant & ARM_EXT_XSCALE)
- mach = bfd_mach_arm_XScale;
- else if (cpu_variant & ARM_EXT_V5E)
- mach = bfd_mach_arm_5TE;
- else if (cpu_variant & ARM_EXT_V5)
- {
- if (cpu_variant & ARM_EXT_THUMB)
- mach = bfd_mach_arm_5T;
- else
- mach = bfd_mach_arm_5;
- }
- else if (cpu_variant & ARM_EXT_HALFWORD)
- {
- if (cpu_variant & ARM_EXT_THUMB)
- mach = bfd_mach_arm_4T;
- else
- mach = bfd_mach_arm_4;
- }
- else if (cpu_variant & ARM_EXT_LONGMUL)
- mach = bfd_mach_arm_3M;
-
- bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
-}
-
-/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
- for use in the a.out file, and stores them in the array pointed to by buf.
- This knows about the endian-ness of the target machine and does
- THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
- 2 (short) and 4 (long) Floating numbers are put out as a series of
- LITTLENUMS (shorts, here at least). */
-
-void
-md_number_to_chars (buf, val, n)
- char * buf;
- valueT val;
- int n;
-{
- if (target_big_endian)
- number_to_chars_bigendian (buf, val, n);
- else
- number_to_chars_littleendian (buf, val, n);
-}
-
-static valueT
-md_chars_to_number (buf, n)
- char * buf;
- int n;
-{
- valueT result = 0;
- unsigned char * where = (unsigned char *) buf;
-
- if (target_big_endian)
- {
- while (n--)
- {
- result <<= 8;
- result |= (*where++ & 255);
- }
- }
- else
- {
- while (n--)
- {
- result <<= 8;
- result |= (where[n] & 255);
- }
- }
-
- return result;
-}
-
-/* Turn a string in input_line_pointer into a floating point constant
- of type TYPE, and store the appropriate bytes in *LITP. The number
- of LITTLENUMS emitted is stored in *SIZEP. An error message is
- returned, or NULL on OK.
-
- Note that fp constants aren't represent in the normal way on the ARM.
- In big endian mode, things are as expected. However, in little endian
- mode fp constants are big-endian word-wise, and little-endian byte-wise
- within the words. For example, (double) 1.1 in big endian mode is
- the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
- the byte sequence 99 99 f1 3f 9a 99 99 99.
-
- ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
-
-char *
-md_atof (type, litP, sizeP)
- char type;
- char * litP;
- int * sizeP;
-{
- int prec;
- LITTLENUM_TYPE words[MAX_LITTLENUMS];
- char *t;
- int i;
-
- switch (type)
- {
- case 'f':
- case 'F':
- case 's':
- case 'S':
- prec = 2;
- break;
-
- case 'd':
- case 'D':
- case 'r':
- case 'R':
- prec = 4;
- break;
-
- case 'x':
- case 'X':
- prec = 6;
- break;
-
- case 'p':
- case 'P':
- prec = 6;
- break;
-
- default:
- *sizeP = 0;
- return _("Bad call to MD_ATOF()");
- }
-
- t = atof_ieee (input_line_pointer, type, words);
- if (t)
- input_line_pointer = t;
- *sizeP = prec * 2;
-
- if (target_big_endian)
- {
- for (i = 0; i < prec; i++)
- {
- md_number_to_chars (litP, (valueT) words[i], 2);
- litP += 2;
- }
- }
- else
- {
- /* For a 4 byte float the order of elements in `words' is 1 0. For an
- 8 byte float the order is 1 0 3 2. */
- for (i = 0; i < prec; i += 2)
- {
- md_number_to_chars (litP, (valueT) words[i + 1], 2);
- md_number_to_chars (litP + 2, (valueT) words[i], 2);
- litP += 4;
- }
- }
-
- return 0;
-}
-
-/* The knowledge of the PC's pipeline offset is built into the insns
- themselves. */
-
-long
-md_pcrel_from (fixP)
- fixS * fixP;
-{
- if (fixP->fx_addsy
- && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
- && fixP->fx_subsy == NULL)
- return 0;
-
- if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
- {
- /* PC relative addressing on the Thumb is slightly odd
- as the bottom two bits of the PC are forced to zero
- for the calculation. */
- return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
- }
-
-#ifdef TE_WINCE
- /* The pattern was adjusted to accomodate CE's off-by-one fixups,
- so we un-adjust here to compensate for the accomodation. */
- return fixP->fx_where + fixP->fx_frag->fr_address + 8;
-#else
- return fixP->fx_where + fixP->fx_frag->fr_address;
-#endif
-}
-
-/* Round up a section size to the appropriate boundary. */
-
-valueT
-md_section_align (segment, size)
- segT segment ATTRIBUTE_UNUSED;
- valueT size;
-{
-#ifdef OBJ_ELF
- return size;
-#else
- /* Round all sects to multiple of 4. */
- return (size + 3) & ~3;
-#endif
-}
-
-/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
- Otherwise we have no need to default values of symbols. */
-
-symbolS *
-md_undefined_symbol (name)
- char * name ATTRIBUTE_UNUSED;
-{
-#ifdef OBJ_ELF
- if (name[0] == '_' && name[1] == 'G'
- && streq (name, GLOBAL_OFFSET_TABLE_NAME))
- {
- if (!GOT_symbol)
- {
- if (symbol_find (name))
- as_bad ("GOT already in the symbol table");
-
- GOT_symbol = symbol_new (name, undefined_section,
- (valueT) 0, & zero_address_frag);
- }
-
- return GOT_symbol;
- }
-#endif
-
- return 0;
-}
-
-/* arm_reg_parse () := if it looks like a register, return its token and
- advance the pointer. */
-
-static int
-arm_reg_parse (ccp)
- register char ** ccp;
-{
- char * start = * ccp;
- char c;
- char * p;
- struct reg_entry * reg;
-
-#ifdef REGISTER_PREFIX
- if (*start != REGISTER_PREFIX)
- return FAIL;
- p = start + 1;
-#else
- p = start;
-#ifdef OPTIONAL_REGISTER_PREFIX
- if (*p == OPTIONAL_REGISTER_PREFIX)
- p++, start++;
-#endif
-#endif
- if (!isalpha (*p) || !is_name_beginner (*p))
- return FAIL;
-
- c = *p++;
- while (isalpha (c) || isdigit (c) || c == '_')
- c = *p++;
-
- *--p = 0;
- reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
- *p = c;
-
- if (reg)
- {
- *ccp = p;
- return reg->number;
- }
-
- return FAIL;
-}
-
-int
-md_apply_fix3 (fixP, val, seg)
- fixS * fixP;
- valueT * val;
- segT seg;
-{
- offsetT value = * val;
- offsetT newval;
- unsigned int newimm;
- unsigned long temp;
- int sign;
- char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
- arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
-
- assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
-
- /* Note whether this will delete the relocation. */
-#if 0
- /* Patch from REarnshaw to JDavis (disabled for the moment, since it
- doesn't work fully.) */
- if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
- && !fixP->fx_pcrel)
-#else
- if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
-#endif
- fixP->fx_done = 1;
-
- /* If this symbol is in a different section then we need to leave it for
- the linker to deal with. Unfortunately, md_pcrel_from can't tell,
- so we have to undo it's effects here. */
- if (fixP->fx_pcrel)
- {
- if (fixP->fx_addsy != NULL
- && S_IS_DEFINED (fixP->fx_addsy)
- && S_GET_SEGMENT (fixP->fx_addsy) != seg)
- {
- if (target_oabi
- && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
- || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
- ))
- value = 0;
- else
- value += md_pcrel_from (fixP);
- }
- }
-
- /* Remember value for emit_reloc. */
- fixP->fx_addnumber = value;
-
- switch (fixP->fx_r_type)
- {
- case BFD_RELOC_ARM_IMMEDIATE:
- newimm = validate_immediate (value);
- temp = md_chars_to_number (buf, INSN_SIZE);
-
- /* If the instruction will fail, see if we can fix things up by
- changing the opcode. */
- if (newimm == (unsigned int) FAIL
- && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
- {
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("invalid constant (%lx) after fixup"),
- (unsigned long) value);
- break;
- }
-
- newimm |= (temp & 0xfffff000);
- md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
- break;
-
- case BFD_RELOC_ARM_ADRL_IMMEDIATE:
- {
- unsigned int highpart = 0;
- unsigned int newinsn = 0xe1a00000; /* nop. */
- newimm = validate_immediate (value);
- temp = md_chars_to_number (buf, INSN_SIZE);
-
- /* If the instruction will fail, see if we can fix things up by
- changing the opcode. */
- if (newimm == (unsigned int) FAIL
- && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
- {
- /* No ? OK - try using two ADD instructions to generate
- the value. */
- newimm = validate_immediate_twopart (value, & highpart);
-
- /* Yes - then make sure that the second instruction is
- also an add. */
- if (newimm != (unsigned int) FAIL)
- newinsn = temp;
- /* Still No ? Try using a negated value. */
- else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
- temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
- /* Otherwise - give up. */
- else
- {
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Unable to compute ADRL instructions for PC offset of 0x%lx"),
- value);
- break;
- }
-
- /* Replace the first operand in the 2nd instruction (which
- is the PC) with the destination register. We have
- already added in the PC in the first instruction and we
- do not want to do it again. */
- newinsn &= ~ 0xf0000;
- newinsn |= ((newinsn & 0x0f000) << 4);
- }
-
- newimm |= (temp & 0xfffff000);
- md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
-
- highpart |= (newinsn & 0xfffff000);
- md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
- }
- break;
-
- case BFD_RELOC_ARM_OFFSET_IMM:
- sign = value >= 0;
-
- if (value < 0)
- value = - value;
-
- if (validate_offset_imm (value, 0) == FAIL)
- {
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("bad immediate value for offset (%ld)"),
- (long) value);
- break;
- }
-
- newval = md_chars_to_number (buf, INSN_SIZE);
- newval &= 0xff7ff000;
- newval |= value | (sign ? INDEX_UP : 0);
- md_number_to_chars (buf, newval, INSN_SIZE);
- break;
-
- case BFD_RELOC_ARM_OFFSET_IMM8:
- case BFD_RELOC_ARM_HWLITERAL:
- sign = value >= 0;
-
- if (value < 0)
- value = - value;
-
- if (validate_offset_imm (value, 1) == FAIL)
- {
- if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("invalid literal constant: pool needs to be closer"));
- else
- as_bad (_("bad immediate value for half-word offset (%ld)"),
- (long) value);
- break;
- }
-
- newval = md_chars_to_number (buf, INSN_SIZE);
- newval &= 0xff7ff0f0;
- newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
- md_number_to_chars (buf, newval, INSN_SIZE);
- break;
-
- case BFD_RELOC_ARM_LITERAL:
- sign = value >= 0;
-
- if (value < 0)
- value = - value;
-
- if (validate_offset_imm (value, 0) == FAIL)
- {
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("invalid literal constant: pool needs to be closer"));
- break;
- }
-
- newval = md_chars_to_number (buf, INSN_SIZE);
- newval &= 0xff7ff000;
- newval |= value | (sign ? INDEX_UP : 0);
- md_number_to_chars (buf, newval, INSN_SIZE);
- break;
-
- case BFD_RELOC_ARM_SHIFT_IMM:
- newval = md_chars_to_number (buf, INSN_SIZE);
- if (((unsigned long) value) > 32
- || (value == 32
- && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
- {
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("shift expression is too large"));
- break;
- }
-
- if (value == 0)
- /* Shifts of zero must be done as lsl. */
- newval &= ~0x60;
- else if (value == 32)
- value = 0;
- newval &= 0xfffff07f;
- newval |= (value & 0x1f) << 7;
- md_number_to_chars (buf, newval, INSN_SIZE);
- break;
-
- case BFD_RELOC_ARM_SWI:
- if (arm_data->thumb_mode)
- {
- if (((unsigned long) value) > 0xff)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid swi expression"));
- newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
- newval |= value;
- md_number_to_chars (buf, newval, THUMB_SIZE);
- }
- else
- {
- if (((unsigned long) value) > 0x00ffffff)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid swi expression"));
- newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
- newval |= value;
- md_number_to_chars (buf, newval, INSN_SIZE);
- }
- break;
-
- case BFD_RELOC_ARM_MULTI:
- if (((unsigned long) value) > 0xffff)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid expression in load/store multiple"));
- newval = value | md_chars_to_number (buf, INSN_SIZE);
- md_number_to_chars (buf, newval, INSN_SIZE);
- break;
-
- case BFD_RELOC_ARM_PCREL_BRANCH:
- newval = md_chars_to_number (buf, INSN_SIZE);
-
- /* Sign-extend a 24-bit number. */
-#define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
-
-#ifdef OBJ_ELF
- if (! target_oabi)
- value = fixP->fx_offset;
-#endif
-
- /* We are going to store value (shifted right by two) in the
- instruction, in a 24 bit, signed field. Thus we need to check
- that none of the top 8 bits of the shifted value (top 7 bits of
- the unshifted, unsigned value) are set, or that they are all set. */
- if ((value & ~ ((offsetT) 0x1ffffff)) != 0
- && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
- {
-#ifdef OBJ_ELF
- /* Normally we would be stuck at this point, since we cannot store
- the absolute address that is the destination of the branch in the
- 24 bits of the branch instruction. If however, we happen to know
- that the destination of the branch is in the same section as the
- branch instruciton itself, then we can compute the relocation for
- ourselves and not have to bother the linker with it.
-
- FIXME: The tests for OBJ_ELF and ! target_oabi are only here
- because I have not worked out how to do this for OBJ_COFF or
- target_oabi. */
- if (! target_oabi
- && fixP->fx_addsy != NULL
- && S_IS_DEFINED (fixP->fx_addsy)
- && S_GET_SEGMENT (fixP->fx_addsy) == seg)
- {
- /* Get pc relative value to go into the branch. */
- value = * val;
-
- /* Permit a backward branch provided that enough bits
- are set. Allow a forwards branch, provided that
- enough bits are clear. */
- if ( (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
- || (value & ~ ((offsetT) 0x1ffffff)) == 0)
- fixP->fx_done = 1;
- }
-
- if (! fixP->fx_done)
-#endif
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("gas can't handle same-section branch dest >= 0x04000000"));
- }
-
- value >>= 2;
- value += SEXT24 (newval);
-
- if ( (value & ~ ((offsetT) 0xffffff)) != 0
- && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("out of range branch"));
-
- newval = (value & 0x00ffffff) | (newval & 0xff000000);
- md_number_to_chars (buf, newval, INSN_SIZE);
- break;
-
- case BFD_RELOC_ARM_PCREL_BLX:
- {
- offsetT hbit;
- newval = md_chars_to_number (buf, INSN_SIZE);
-
-#ifdef OBJ_ELF
- if (! target_oabi)
- value = fixP->fx_offset;
-#endif
- hbit = (value >> 1) & 1;
- value = (value >> 2) & 0x00ffffff;
- value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
- newval = value | (newval & 0xfe000000) | (hbit << 24);
- md_number_to_chars (buf, newval, INSN_SIZE);
- }
- break;
-
- case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
- newval = md_chars_to_number (buf, THUMB_SIZE);
- {
- addressT diff = (newval & 0xff) << 1;
- if (diff & 0x100)
- diff |= ~0xff;
-
- value += diff;
- if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Branch out of range"));
- newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
- }
- md_number_to_chars (buf, newval, THUMB_SIZE);
- break;
-
- case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
- newval = md_chars_to_number (buf, THUMB_SIZE);
- {
- addressT diff = (newval & 0x7ff) << 1;
- if (diff & 0x800)
- diff |= ~0x7ff;
-
- value += diff;
- if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Branch out of range"));
- newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
- }
- md_number_to_chars (buf, newval, THUMB_SIZE);
- break;
-
- case BFD_RELOC_THUMB_PCREL_BLX:
- case BFD_RELOC_THUMB_PCREL_BRANCH23:
- {
- offsetT newval2;
- addressT diff;
-
- newval = md_chars_to_number (buf, THUMB_SIZE);
- newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
- diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
- if (diff & 0x400000)
- diff |= ~0x3fffff;
-#ifdef OBJ_ELF
- value = fixP->fx_offset;
-#endif
- value += diff;
- if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Branch with link out of range"));
-
- newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
- newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
- if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
- /* Remove bit zero of the adjusted offset. Bit zero can only be
- set if the upper insn is at a half-word boundary, since the
- destination address, an ARM instruction, must always be on a
- word boundary. The semantics of the BLX (1) instruction, however,
- are that bit zero in the offset must always be zero, and the
- corresponding bit one in the target address will be set from bit
- one of the source address. */
- newval2 &= ~1;
- md_number_to_chars (buf, newval, THUMB_SIZE);
- md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
- }
- break;
-
- case BFD_RELOC_8:
- if (fixP->fx_done || fixP->fx_pcrel)
- md_number_to_chars (buf, value, 1);
-#ifdef OBJ_ELF
- else if (!target_oabi)
- {
- value = fixP->fx_offset;
- md_number_to_chars (buf, value, 1);
- }
-#endif
- break;
-
- case BFD_RELOC_16:
- if (fixP->fx_done || fixP->fx_pcrel)
- md_number_to_chars (buf, value, 2);
-#ifdef OBJ_ELF
- else if (!target_oabi)
- {
- value = fixP->fx_offset;
- md_number_to_chars (buf, value, 2);
- }
-#endif
- break;
-
-#ifdef OBJ_ELF
- case BFD_RELOC_ARM_GOT32:
- case BFD_RELOC_ARM_GOTOFF:
- md_number_to_chars (buf, 0, 4);
- break;
-#endif
-
- case BFD_RELOC_RVA:
- case BFD_RELOC_32:
- if (fixP->fx_done || fixP->fx_pcrel)
- md_number_to_chars (buf, value, 4);
-#ifdef OBJ_ELF
- else if (!target_oabi)
- {
- value = fixP->fx_offset;
- md_number_to_chars (buf, value, 4);
- }
-#endif
- break;
-
-#ifdef OBJ_ELF
- case BFD_RELOC_ARM_PLT32:
- /* It appears the instruction is fully prepared at this point. */
- break;
-#endif
-
- case BFD_RELOC_ARM_GOTPC:
- md_number_to_chars (buf, value, 4);
- break;
-
- case BFD_RELOC_ARM_CP_OFF_IMM:
- sign = value >= 0;
- if (value < -1023 || value > 1023 || (value & 3))
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Illegal value for co-processor offset"));
- if (value < 0)
- value = -value;
- newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
- newval |= (value >> 2) | (sign ? INDEX_UP : 0);
- md_number_to_chars (buf, newval, INSN_SIZE);
- break;
-
- case BFD_RELOC_ARM_THUMB_OFFSET:
- newval = md_chars_to_number (buf, THUMB_SIZE);
- /* Exactly what ranges, and where the offset is inserted depends
- on the type of instruction, we can establish this from the
- top 4 bits. */
- switch (newval >> 12)
- {
- case 4: /* PC load. */
- /* Thumb PC loads are somewhat odd, bit 1 of the PC is
- forced to zero for these loads, so we will need to round
- up the offset if the instruction address is not word
- aligned (since the final address produced must be, and
- we can only describe word-aligned immediate offsets). */
-
- if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, target not word aligned (0x%08X)"),
- (unsigned int) (fixP->fx_frag->fr_address
- + fixP->fx_where + value));
-
- if ((value + 2) & ~0x3fe)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
-
- /* Round up, since pc will be rounded down. */
- newval |= (value + 2) >> 2;
- break;
-
- case 9: /* SP load/store. */
- if (value & ~0x3fc)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
- newval |= value >> 2;
- break;
-
- case 6: /* Word load/store. */
- if (value & ~0x7c)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
- newval |= value << 4; /* 6 - 2. */
- break;
-
- case 7: /* Byte load/store. */
- if (value & ~0x1f)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
- newval |= value << 6;
- break;
-
- case 8: /* Halfword load/store. */
- if (value & ~0x3e)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid offset, value too big (0x%08lX)"), value);
- newval |= value << 5; /* 6 - 1. */
- break;
-
- default:
- as_bad_where (fixP->fx_file, fixP->fx_line,
- "Unable to process relocation for thumb opcode: %lx",
- (unsigned long) newval);
- break;
- }
- md_number_to_chars (buf, newval, THUMB_SIZE);
- break;
-
- case BFD_RELOC_ARM_THUMB_ADD:
- /* This is a complicated relocation, since we use it for all of
- the following immediate relocations:
-
- 3bit ADD/SUB
- 8bit ADD/SUB
- 9bit ADD/SUB SP word-aligned
- 10bit ADD PC/SP word-aligned
-
- The type of instruction being processed is encoded in the
- instruction field:
-
- 0x8000 SUB
- 0x00F0 Rd
- 0x000F Rs
- */
- newval = md_chars_to_number (buf, THUMB_SIZE);
- {
- int rd = (newval >> 4) & 0xf;
- int rs = newval & 0xf;
- int subtract = newval & 0x8000;
-
- if (rd == REG_SP)
- {
- if (value & ~0x1fc)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid immediate for stack address calculation"));
- newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
- newval |= value >> 2;
- }
- else if (rs == REG_PC || rs == REG_SP)
- {
- if (subtract ||
- value & ~0x3fc)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid immediate for address calculation (value = 0x%08lX)"),
- (unsigned long) value);
- newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
- newval |= rd << 8;
- newval |= value >> 2;
- }
- else if (rs == rd)
- {
- if (value & ~0xff)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid 8bit immediate"));
- newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
- newval |= (rd << 8) | value;
- }
- else
- {
- if (value & ~0x7)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid 3bit immediate"));
- newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
- newval |= rd | (rs << 3) | (value << 6);
- }
- }
- md_number_to_chars (buf, newval, THUMB_SIZE);
- break;
-
- case BFD_RELOC_ARM_THUMB_IMM:
- newval = md_chars_to_number (buf, THUMB_SIZE);
- switch (newval >> 11)
- {
- case 0x04: /* 8bit immediate MOV. */
- case 0x05: /* 8bit immediate CMP. */
- if (value < 0 || value > 255)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Invalid immediate: %ld is too large"),
- (long) value);
- newval |= value;
- break;
-
- default:
- abort ();
- }
- md_number_to_chars (buf, newval, THUMB_SIZE);
- break;
-
- case BFD_RELOC_ARM_THUMB_SHIFT:
- /* 5bit shift value (0..31). */
- if (value < 0 || value > 31)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Illegal Thumb shift value: %ld"), (long) value);
- newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
- newval |= value << 6;
- md_number_to_chars (buf, newval, THUMB_SIZE);
- break;
-
- case BFD_RELOC_VTABLE_INHERIT:
- case BFD_RELOC_VTABLE_ENTRY:
- fixP->fx_done = 0;
- return 1;
-
- case BFD_RELOC_NONE:
- default:
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
- }
-
- return 1;
-}
-
-/* Translate internal representation of relocation info to BFD target
- format. */
-
-arelent *
-tc_gen_reloc (section, fixp)
- asection * section ATTRIBUTE_UNUSED;
- fixS * fixp;
-{
- arelent * reloc;
- bfd_reloc_code_real_type code;
-
- reloc = (arelent *) xmalloc (sizeof (arelent));
-
- reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
- *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
- reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
-
- /* @@ Why fx_addnumber sometimes and fx_offset other times? */
-#ifndef OBJ_ELF
- if (fixp->fx_pcrel == 0)
- reloc->addend = fixp->fx_offset;
- else
- reloc->addend = fixp->fx_offset = reloc->address;
-#else /* OBJ_ELF */
- reloc->addend = fixp->fx_offset;
-#endif
-
- switch (fixp->fx_r_type)
- {
- case BFD_RELOC_8:
- if (fixp->fx_pcrel)
- {
- code = BFD_RELOC_8_PCREL;
- break;
- }
-
- case BFD_RELOC_16:
- if (fixp->fx_pcrel)
- {
- code = BFD_RELOC_16_PCREL;
- break;
- }
-
- case BFD_RELOC_32:
- if (fixp->fx_pcrel)
- {
- code = BFD_RELOC_32_PCREL;
- break;
- }
-
- case BFD_RELOC_ARM_PCREL_BRANCH:
- case BFD_RELOC_ARM_PCREL_BLX:
- case BFD_RELOC_RVA:
- case BFD_RELOC_THUMB_PCREL_BRANCH9:
- case BFD_RELOC_THUMB_PCREL_BRANCH12:
- case BFD_RELOC_THUMB_PCREL_BRANCH23:
- case BFD_RELOC_THUMB_PCREL_BLX:
- case BFD_RELOC_VTABLE_ENTRY:
- case BFD_RELOC_VTABLE_INHERIT:
- code = fixp->fx_r_type;
- break;
-
- case BFD_RELOC_ARM_LITERAL:
- case BFD_RELOC_ARM_HWLITERAL:
- /* If this is called then the a literal has been referenced across
- a section boundary - possibly due to an implicit dump. */
- as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Literal referenced across section boundary (Implicit dump?)"));
- return NULL;
-
-#ifdef OBJ_ELF
- case BFD_RELOC_ARM_GOT32:
- case BFD_RELOC_ARM_GOTOFF:
- case BFD_RELOC_ARM_PLT32:
- code = fixp->fx_r_type;
- break;
-#endif
-
- case BFD_RELOC_ARM_IMMEDIATE:
- as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
- fixp->fx_r_type);
- return NULL;
-
- case BFD_RELOC_ARM_ADRL_IMMEDIATE:
- as_bad_where (fixp->fx_file, fixp->fx_line,
- _("ADRL used for a symbol not defined in the same file"));
- return NULL;
-
- case BFD_RELOC_ARM_OFFSET_IMM:
- as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
- fixp->fx_r_type);
- return NULL;
-
- default:
- {
- char * type;
-
- switch (fixp->fx_r_type)
- {
- case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
- case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
- case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
- case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
- case BFD_RELOC_ARM_SWI: type = "SWI"; break;
- case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
- case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
- case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
- case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
- case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
- case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
- default: type = _("<unknown>"); break;
- }
- as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Cannot represent %s relocation in this object file format"),
- type);
- return NULL;
- }
- }
-
-#ifdef OBJ_ELF
- if (code == BFD_RELOC_32_PCREL
- && GOT_symbol
- && fixp->fx_addsy == GOT_symbol)
- {
- code = BFD_RELOC_ARM_GOTPC;
- reloc->addend = fixp->fx_offset = reloc->address;
- }
-#endif
-
- reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
-
- if (reloc->howto == NULL)
- {
- as_bad_where (fixp->fx_file, fixp->fx_line,
- _("Can not represent %s relocation in this object file format"),
- bfd_get_reloc_code_name (code));
- return NULL;
- }
-
- /* HACK: Since arm ELF uses Rel instead of Rela, encode the
- vtable entry to be used in the relocation's section offset. */
- if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
- reloc->address = fixp->fx_offset;
-
- return reloc;
-}
-
-int
-md_estimate_size_before_relax (fragP, segtype)
- fragS * fragP ATTRIBUTE_UNUSED;
- segT segtype ATTRIBUTE_UNUSED;
-{
- as_fatal (_("md_estimate_size_before_relax\n"));
- return 1;
-}
-
-static void
-output_inst PARAMS ((void))
-{
- char * to = NULL;
-
- if (inst.error)
- {
- as_bad (inst.error);
- return;
- }
-
- to = frag_more (inst.size);
-
- if (thumb_mode && (inst.size > THUMB_SIZE))
- {
- assert (inst.size == (2 * THUMB_SIZE));
- md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
- md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
- }
- else if (inst.size > INSN_SIZE)
- {
- assert (inst.size == (2 * INSN_SIZE));
- md_number_to_chars (to, inst.instruction, INSN_SIZE);
- md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
- }
- else
- md_number_to_chars (to, inst.instruction, inst.size);
-
- if (inst.reloc.type != BFD_RELOC_NONE)
- fix_new_arm (frag_now, to - frag_now->fr_literal,
- inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
- inst.reloc.type);
-
-#ifdef OBJ_ELF
- dwarf2_emit_insn (inst.size);
-#endif
-}
-
-void
-md_assemble (str)
- char * str;
-{
- char c;
- char * p;
- char * q;
- char * start;
-
- /* Align the instruction.
- This may not be the right thing to do but ... */
-#if 0
- arm_align (2, 0);
-#endif
- listing_prev_line (); /* Defined in listing.h. */
-
- /* Align the previous label if needed. */
- if (last_label_seen != NULL)
- {
- symbol_set_frag (last_label_seen, frag_now);
- S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
- S_SET_SEGMENT (last_label_seen, now_seg);
- }
-
- memset (&inst, '\0', sizeof (inst));
- inst.reloc.type = BFD_RELOC_NONE;
-
- skip_whitespace (str);
-
- /* Scan up to the end of the op-code, which must end in white space or
- end of string. */
- for (start = p = str; *p != '\0'; p++)
- if (*p == ' ')
- break;
-
- if (p == str)
- {
- as_bad (_("No operator -- statement `%s'\n"), str);
- return;
- }
-
- if (thumb_mode)
- {
- CONST struct thumb_opcode * opcode;
-
- c = *p;
- *p = '\0';
- opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
- *p = c;
-
- if (opcode)
- {
- /* Check that this instruction is supported for this CPU. */
- if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
- {
- as_bad (_("selected processor does not support this opcode"));
- return;
- }
-
- inst.instruction = opcode->value;
- inst.size = opcode->size;
- (*opcode->parms) (p);
- output_inst ();
- return;
- }
- }
- else
- {
- CONST struct asm_opcode * opcode;
- unsigned long cond_code;
-
- inst.size = INSN_SIZE;
- /* P now points to the end of the opcode, probably white space, but we
- have to break the opcode up in case it contains condionals and flags;
- keep trying with progressively smaller basic instructions until one
- matches, or we run out of opcode. */
- q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
-
- for (; q != str; q--)
- {
- c = *q;
- *q = '\0';
-
- opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
- *q = c;
-
- if (opcode && opcode->template)
- {
- unsigned long flag_bits = 0;
- char * r;
-
- /* Check that this instruction is supported for this CPU. */
- if ((opcode->variants & cpu_variant) == 0)
- goto try_shorter;
-
- inst.instruction = opcode->value;
- if (q == p) /* Just a simple opcode. */
- {
- if (opcode->comp_suffix)
- {
- if (*opcode->comp_suffix != '\0')
- as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
- str, opcode->comp_suffix);
- else
- /* Not a conditional instruction. */
- (*opcode->parms) (q, 0);
- }
- else
- {
- /* A conditional instruction with default condition. */
- inst.instruction |= COND_ALWAYS;
- (*opcode->parms) (q, 0);
- }
- output_inst ();
- return;
- }
-
- /* Not just a simple opcode. Check if extra is a
- conditional. */
- r = q;
- if (p - r >= 2)
- {
- CONST struct asm_cond *cond;
- char d = *(r + 2);
-
- *(r + 2) = '\0';
- cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
- *(r + 2) = d;
- if (cond)
- {
- if (cond->value == 0xf0000000)
- as_tsktsk (
-_("Warning: Use of the 'nv' conditional is deprecated\n"));
-
- cond_code = cond->value;
- r += 2;
- }
- else
- cond_code = COND_ALWAYS;
- }
- else
- cond_code = COND_ALWAYS;
-
- /* Apply the conditional, or complain it's not allowed. */
- if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
- {
- /* Instruction isn't conditional. */
- if (cond_code != COND_ALWAYS)
- {
- as_bad (_("Opcode `%s' is unconditional\n"), str);
- return;
- }
- }
- else
- /* Instruction is conditional: set the condition into it. */
- inst.instruction |= cond_code;
-
- /* If there is a compulsory suffix, it should come here
- before any optional flags. */
- if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
- {
- CONST char *s = opcode->comp_suffix;
-
- while (*s)
- {
- inst.suffix++;
- if (*r == *s)
- break;
- s++;
- }
-
- if (*s == '\0')
- {
- as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
- str, opcode->comp_suffix);
- return;
- }
-
- r++;
- }
-
- /* The remainder, if any should now be flags for the instruction;
- Scan these checking each one found with the opcode. */
- if (r != p)
- {
- char d;
- CONST struct asm_flg *flag = opcode->flags;
-
- if (flag)
- {
- int flagno;
-
- d = *p;
- *p = '\0';
-
- for (flagno = 0; flag[flagno].template; flagno++)
- {
- if (streq (r, flag[flagno].template))
- {
- flag_bits |= flag[flagno].set_bits;
- break;
- }
- }
-
- *p = d;
- if (! flag[flagno].template)
- goto try_shorter;
- }
- else
- goto try_shorter;
- }
-
- (*opcode->parms) (p, flag_bits);
- output_inst ();
- return;
- }
-
- try_shorter:
- ;
- }
- }
-
- /* It wasn't an instruction, but it might be a register alias of the form
- alias .req reg. */
- q = p;
- skip_whitespace (q);
-
- c = *p;
- *p = '\0';
-
- if (*q && !strncmp (q, ".req ", 4))
- {
- int reg;
- char * copy_of_str;
- char * r;
-
-#ifdef IGNORE_OPCODE_CASE
- str = original_case_string;
-#endif
- copy_of_str = str;
-
- q += 4;
- skip_whitespace (q);
-
- for (r = q; *r != '\0'; r++)
- if (*r == ' ')
- break;
-
- if (r != q)
- {
- int regnum;
- char d = *r;
-
- *r = '\0';
- regnum = arm_reg_parse (& q);
- *r = d;
-
- reg = arm_reg_parse (& str);
-
- if (reg == FAIL)
- {
- if (regnum != FAIL)
- insert_reg_alias (str, regnum);
- else
- as_warn (_("register '%s' does not exist\n"), q);
- }
- else if (regnum != FAIL)
- {
- if (reg != regnum)
- as_warn (_("ignoring redefinition of register alias '%s'"),
- copy_of_str);
-
- /* Do not warn about redefinitions to the same alias. */
- }
- else
- as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
- copy_of_str, q);
- }
- else
- as_warn (_("ignoring incomplete .req pseuso op"));
-
- *p = c;
- return;
- }
-
- *p = c;
- as_bad (_("bad instruction `%s'"), start);
-}
-
-/* md_parse_option
- Invocation line includes a switch not recognized by the base assembler.
- See if it's a processor-specific option. These are:
- Cpu variants, the arm part is optional:
- -m[arm]1 Currently not supported.
- -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
- -m[arm]3 Arm 3 processor
- -m[arm]6[xx], Arm 6 processors
- -m[arm]7[xx][t][[d]m] Arm 7 processors
- -m[arm]8[10] Arm 8 processors
- -m[arm]9[20][tdmi] Arm 9 processors
- -mstrongarm[110[0]] StrongARM processors
- -mxscale XScale processors
- -m[arm]v[2345[t[e]]] Arm architectures
- -mall All (except the ARM1)
- FP variants:
- -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
- -mfpe-old (No float load/store multiples)
- -mno-fpu Disable all floating point instructions
- Run-time endian selection:
- -EB big endian cpu
- -EL little endian cpu
- ARM Procedure Calling Standard:
- -mapcs-32 32 bit APCS
- -mapcs-26 26 bit APCS
- -mapcs-float Pass floats in float regs
- -mapcs-reentrant Position independent code
- -mthumb-interwork Code supports Arm/Thumb interworking
- -matpcs ARM/Thumb Procedure Call Standard
- -moabi Old ELF ABI */
-
-CONST char * md_shortopts = "m:k";
-
-struct option md_longopts[] =
-{
-#ifdef ARM_BI_ENDIAN
-#define OPTION_EB (OPTION_MD_BASE + 0)
- {"EB", no_argument, NULL, OPTION_EB},
-#define OPTION_EL (OPTION_MD_BASE + 1)
- {"EL", no_argument, NULL, OPTION_EL},
-#ifdef OBJ_ELF
-#define OPTION_OABI (OPTION_MD_BASE +2)
- {"oabi", no_argument, NULL, OPTION_OABI},
-#endif
-#endif
- {NULL, no_argument, NULL, 0}
-};
-
-size_t md_longopts_size = sizeof (md_longopts);
-
-int
-md_parse_option (c, arg)
- int c;
- char * arg;
-{
- char * str = arg;
-
- switch (c)
- {
-#ifdef ARM_BI_ENDIAN
- case OPTION_EB:
- target_big_endian = 1;
- break;
- case OPTION_EL:
- target_big_endian = 0;
- break;
-#endif
-
- case 'm':
- switch (*str)
- {
- case 'f':
- if (streq (str, "fpa10"))
- cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
- else if (streq (str, "fpa11"))
- cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
- else if (streq (str, "fpe-old"))
- cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
- else
- goto bad;
- break;
-
- case 'n':
- if (streq (str, "no-fpu"))
- cpu_variant &= ~FPU_ALL;
- break;
-
-#ifdef OBJ_ELF
- case 'o':
- if (streq (str, "oabi"))
- target_oabi = true;
- break;
-#endif
-
- case 't':
- /* Limit assembler to generating only Thumb instructions: */
- if (streq (str, "thumb"))
- {
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_EXT_THUMB;
- cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
- thumb_mode = 1;
- }
- else if (streq (str, "thumb-interwork"))
- {
- if ((cpu_variant & ARM_EXT_THUMB) == 0)
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
-#if defined OBJ_COFF || defined OBJ_ELF
- support_interwork = true;
-#endif
- }
- else
- goto bad;
- break;
-
- default:
- if (streq (str, "all"))
- {
- cpu_variant = ARM_ALL | FPU_ALL;
- return 1;
- }
-#if defined OBJ_COFF || defined OBJ_ELF
- if (! strncmp (str, "apcs-", 5))
- {
- /* GCC passes on all command line options starting "-mapcs-..."
- to us, so we must parse them here. */
-
- str += 5;
-
- if (streq (str, "32"))
- {
- uses_apcs_26 = false;
- return 1;
- }
- else if (streq (str, "26"))
- {
- uses_apcs_26 = true;
- return 1;
- }
- else if (streq (str, "frame"))
- {
- /* Stack frames are being generated - does not affect
- linkage of code. */
- return 1;
- }
- else if (streq (str, "stack-check"))
- {
- /* Stack checking is being performed - does not affect
- linkage, but does require that the functions
- __rt_stkovf_split_small and __rt_stkovf_split_big be
- present in the final link. */
-
- return 1;
- }
- else if (streq (str, "float"))
- {
- /* Floating point arguments are being passed in the floating
- point registers. This does affect linking, since this
- version of the APCS is incompatible with the version that
- passes floating points in the integer registers. */
-
- uses_apcs_float = true;
- return 1;
- }
- else if (streq (str, "reentrant"))
- {
- /* Reentrant code has been generated. This does affect
- linking, since there is no point in linking reentrant/
- position independent code with absolute position code. */
- pic_code = true;
- return 1;
- }
-
- as_bad (_("Unrecognised APCS switch -m%s"), arg);
- return 0;
- }
-
- if (! strcmp (str, "atpcs"))
- {
- atpcs = true;
- return 1;
- }
-#endif
- /* Strip off optional "arm". */
- if (! strncmp (str, "arm", 3))
- str += 3;
-
- switch (*str)
- {
- case '1':
- if (streq (str, "1"))
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
- else
- goto bad;
- break;
-
- case '2':
- if (streq (str, "2"))
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
- else if (streq (str, "250"))
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
- else
- goto bad;
- break;
-
- case '3':
- if (streq (str, "3"))
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
- else
- goto bad;
- break;
-
- case '6':
- switch (strtol (str, NULL, 10))
- {
- case 6:
- case 60:
- case 600:
- case 610:
- case 620:
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
- break;
- default:
- goto bad;
- }
- break;
-
- case '7':
- /* Eat the processor name. */
- switch (strtol (str, & str, 10))
- {
- case 7:
- case 70:
- case 700:
- case 710:
- case 720:
- case 7100:
- case 7500:
- break;
- default:
- goto bad;
- }
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
- for (; *str; str++)
- {
- switch (*str)
- {
- case 't':
- cpu_variant |= ARM_ARCH_V4T;
- break;
-
- case 'm':
- cpu_variant |= ARM_EXT_LONGMUL;
- break;
-
- case 'f': /* fe => fp enabled cpu. */
- if (str[1] == 'e')
- ++ str;
- else
- goto bad;
-
- case 'c': /* Left over from 710c processor name. */
- case 'd': /* Debug. */
- case 'i': /* Embedded ICE. */
- /* Included for completeness in ARM processor naming. */
- break;
-
- default:
- goto bad;
- }
- }
- break;
-
- case '8':
- if (streq (str, "8") || streq (str, "810"))
- cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_8 | ARM_ARCH_V4;
- else
- goto bad;
- break;
-
- case '9':
- if (streq (str, "9"))
- cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_9 | ARM_ARCH_V4T;
- else if (streq (str, "920"))
- cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_9 | ARM_ARCH_V4;
- else if (streq (str, "920t"))
- cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_9 | ARM_ARCH_V4T;
- else if (streq (str, "9tdmi"))
- cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_9 | ARM_ARCH_V4T;
- else
- goto bad;
- break;
-
- case 's':
- if (streq (str, "strongarm")
- || streq (str, "strongarm110")
- || streq (str, "strongarm1100"))
- cpu_variant = (cpu_variant & ~ARM_ANY)
- | ARM_8 | ARM_ARCH_V4;
- else
- goto bad;
- break;
-
- case 'x':
- if (streq (str, "xscale"))
- cpu_variant = ARM_9 | ARM_ARCH_XSCALE;
- else
- goto bad;
- break;
-
- case 'v':
- /* Select variant based on architecture rather than
- processor. */
- switch (*++str)
- {
- case '2':
- switch (*++str)
- {
- case 'a':
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
- break;
- case 0:
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
- break;
- default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
- break;
- }
- break;
-
- case '3':
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
-
- switch (*++str)
- {
- case 'm': cpu_variant |= ARM_EXT_LONGMUL; break;
- case 0: break;
- default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
- break;
- }
- break;
-
- case '4':
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7 | ARM_ARCH_V4;
-
- switch (*++str)
- {
- case 't': cpu_variant |= ARM_EXT_THUMB; break;
- case 0: break;
- default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
- break;
- }
- break;
-
- case '5':
- cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_9 | ARM_ARCH_V5;
- switch (*++str)
- {
- case 't': cpu_variant |= ARM_EXT_THUMB; break;
- case 'e': cpu_variant |= ARM_EXT_V5E; break;
- case 0: break;
- default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
- break;
- }
- break;
-
- default:
- as_bad (_("Invalid architecture variant -m%s"), arg);
- break;
- }
- break;
-
- default:
- bad:
- as_bad (_("Invalid processor variant -m%s"), arg);
- return 0;
- }
- }
- break;
-
-#if defined OBJ_ELF || defined OBJ_COFF
- case 'k':
- pic_code = 1;
- break;
-#endif
-
- default:
- return 0;
- }
-
- return 1;
-}
-
-void
-md_show_usage (fp)
- FILE * fp;
-{
- fprintf (fp, _("\
- ARM Specific Assembler Options:\n\
- -m[arm][<processor name>] select processor variant\n\
- -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
- -mthumb only allow Thumb instructions\n\
- -mthumb-interwork mark the assembled code as supporting interworking\n\
- -mall allow any instruction\n\
- -mfpa10, -mfpa11 select floating point architecture\n\
- -mfpe-old don't allow floating-point multiple instructions\n\
- -mno-fpu don't allow any floating-point instructions.\n\
- -k generate PIC code.\n"));
-#if defined OBJ_COFF || defined OBJ_ELF
- fprintf (fp, _("\
- -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
- -matpcs use ARM/Thumb Procedure Calling Standard\n\
- -mapcs-float floating point args are passed in FP regs\n\
- -mapcs-reentrant the code is position independent/reentrant\n"));
-#endif
-#ifdef OBJ_ELF
- fprintf (fp, _("\
- -moabi support the old ELF ABI\n"));
-#endif
-#ifdef ARM_BI_ENDIAN
- fprintf (fp, _("\
- -EB assemble code for a big endian cpu\n\
- -EL assemble code for a little endian cpu\n"));
-#endif
-}
-
-/* We need to be able to fix up arbitrary expressions in some statements.
- This is so that we can handle symbols that are an arbitrary distance from
- the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
- which returns part of an address in a form which will be valid for
- a data instruction. We do this by pushing the expression into a symbol
- in the expr_section, and creating a fix for that. */
-
-static void
-fix_new_arm (frag, where, size, exp, pc_rel, reloc)
- fragS * frag;
- int where;
- short int size;
- expressionS * exp;
- int pc_rel;
- int reloc;
-{
- fixS * new_fix;
- arm_fix_data * arm_data;
-
- switch (exp->X_op)
- {
- case O_constant:
- case O_symbol:
- case O_add:
- case O_subtract:
- new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
- break;
-
- default:
- new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
- pc_rel, reloc);
- break;
- }
-
- /* Mark whether the fix is to a THUMB instruction, or an ARM
- instruction. */
- arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
- new_fix->tc_fix_data = (PTR) arm_data;
- arm_data->thumb_mode = thumb_mode;
-
- return;
-}
-
-/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
-
-void
-cons_fix_new_arm (frag, where, size, exp)
- fragS * frag;
- int where;
- int size;
- expressionS * exp;
-{
- bfd_reloc_code_real_type type;
- int pcrel = 0;
-
- /* Pick a reloc.
- FIXME: @@ Should look at CPU word size. */
- switch (size)
- {
- case 1:
- type = BFD_RELOC_8;
- break;
- case 2:
- type = BFD_RELOC_16;
- break;
- case 4:
- default:
- type = BFD_RELOC_32;
- break;
- case 8:
- type = BFD_RELOC_64;
- break;
- }
-
- fix_new_exp (frag, where, (int) size, exp, pcrel, type);
-}
-
-/* A good place to do this, although this was probably not intended
- for this kind of use. We need to dump the literal pool before
- references are made to a null symbol pointer. */
-
-void
-arm_cleanup ()
-{
- if (current_poolP == NULL)
- return;
-
- /* Put it at the end of text section. */
- subseg_set (text_section, 0);
- s_ltorg (0);
- listing_prev_line ();
-}
-
-void
-arm_start_line_hook ()
-{
- last_label_seen = NULL;
-}
-
-void
-arm_frob_label (sym)
- symbolS * sym;
-{
- last_label_seen = sym;
-
- ARM_SET_THUMB (sym, thumb_mode);
-
-#if defined OBJ_COFF || defined OBJ_ELF
- ARM_SET_INTERWORK (sym, support_interwork);
-#endif
-
- /* Note - do not allow local symbols (.Lxxx) to be labeled
- as Thumb functions. This is because these labels, whilst
- they exist inside Thumb code, are not the entry points for
- possible ARM->Thumb calls. Also, these labels can be used
- as part of a computed goto or switch statement. eg gcc
- can generate code that looks like this:
-
- ldr r2, [pc, .Laaa]
- lsl r3, r3, #2
- ldr r2, [r3, r2]
- mov pc, r2
-
- .Lbbb: .word .Lxxx
- .Lccc: .word .Lyyy
- ..etc...
- .Laaa: .word Lbbb
-
- The first instruction loads the address of the jump table.
- The second instruction converts a table index into a byte offset.
- The third instruction gets the jump address out of the table.
- The fourth instruction performs the jump.
-
- If the address stored at .Laaa is that of a symbol which has the
- Thumb_Func bit set, then the linker will arrange for this address
- to have the bottom bit set, which in turn would mean that the
- address computation performed by the third instruction would end
- up with the bottom bit set. Since the ARM is capable of unaligned
- word loads, the instruction would then load the incorrect address
- out of the jump table, and chaos would ensue. */
- if (label_is_thumb_function_name
- && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
- && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
- {
- /* When the address of a Thumb function is taken the bottom
- bit of that address should be set. This will allow
- interworking between Arm and Thumb functions to work
- correctly. */
-
- THUMB_SET_FUNC (sym, 1);
-
- label_is_thumb_function_name = false;
- }
-}
-
-/* Adjust the symbol table. This marks Thumb symbols as distinct from
- ARM ones. */
-
-void
-arm_adjust_symtab ()
-{
-#ifdef OBJ_COFF
- symbolS * sym;
-
- for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
- {
- if (ARM_IS_THUMB (sym))
- {
- if (THUMB_IS_FUNC (sym))
- {
- /* Mark the symbol as a Thumb function. */
- if ( S_GET_STORAGE_CLASS (sym) == C_STAT
- || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
- S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
-
- else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
- S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
- else
- as_bad (_("%s: unexpected function type: %d"),
- S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
- }
- else switch (S_GET_STORAGE_CLASS (sym))
- {
- case C_EXT:
- S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
- break;
- case C_STAT:
- S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
- break;
- case C_LABEL:
- S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
- break;
- default:
- /* Do nothing. */
- break;
- }
- }
-
- if (ARM_IS_INTERWORK (sym))
- coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
- }
-#endif
-#ifdef OBJ_ELF
- symbolS * sym;
- char bind;
-
- for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
- {
- if (ARM_IS_THUMB (sym))
- {
- elf_symbol_type * elf_sym;
-
- elf_sym = elf_symbol (symbol_get_bfdsym (sym));
- bind = ELF_ST_BIND (elf_sym);
-
- /* If it's a .thumb_func, declare it as so,
- otherwise tag label as .code 16. */
- if (THUMB_IS_FUNC (sym))
- elf_sym->internal_elf_sym.st_info =
- ELF_ST_INFO (bind, STT_ARM_TFUNC);
- else
- elf_sym->internal_elf_sym.st_info =
- ELF_ST_INFO (bind, STT_ARM_16BIT);
- }
- }
-#endif
-}
-
-int
-arm_data_in_code ()
-{
- if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
- {
- *input_line_pointer = '/';
- input_line_pointer += 5;
- *input_line_pointer = 0;
- return 1;
- }
-
- return 0;
-}
-
-char *
-arm_canonicalize_symbol_name (name)
- char * name;
-{
- int len;
-
- if (thumb_mode && (len = strlen (name)) > 5
- && streq (name + len - 5, "/data"))
- *(name + len - 5) = 0;
-
- return name;
-}
-
-boolean
-arm_validate_fix (fixP)
- fixS * fixP;
-{
- /* If the destination of the branch is a defined symbol which does not have
- the THUMB_FUNC attribute, then we must be calling a function which has
- the (interfacearm) attribute. We look for the Thumb entry point to that
- function and change the branch to refer to that function instead. */
- if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
- && fixP->fx_addsy != NULL
- && S_IS_DEFINED (fixP->fx_addsy)
- && ! THUMB_IS_FUNC (fixP->fx_addsy))
- {
- fixP->fx_addsy = find_real_start (fixP->fx_addsy);
- return true;
- }
-
- return false;
-}
-
-#ifdef OBJ_COFF
-/* This is a little hack to help the gas/arm/adrl.s test. It prevents
- local labels from being added to the output symbol table when they
- are used with the ADRL pseudo op. The ADRL relocation should always
- be resolved before the binbary is emitted, so it is safe to say that
- it is adjustable. */
-
-boolean
-arm_fix_adjustable (fixP)
- fixS * fixP;
-{
- if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
- return 1;
- return 0;
-}
-#endif
-#ifdef OBJ_ELF
-/* Relocations against Thumb function names must be left unadjusted,
- so that the linker can use this information to correctly set the
- bottom bit of their addresses. The MIPS version of this function
- also prevents relocations that are mips-16 specific, but I do not
- know why it does this.
-
- FIXME:
- There is one other problem that ought to be addressed here, but
- which currently is not: Taking the address of a label (rather
- than a function) and then later jumping to that address. Such
- addresses also ought to have their bottom bit set (assuming that
- they reside in Thumb code), but at the moment they will not. */
-
-boolean
-arm_fix_adjustable (fixP)
- fixS * fixP;
-{
- if (fixP->fx_addsy == NULL)
- return 1;
-
- /* Prevent all adjustments to global symbols. */
- if (S_IS_EXTERN (fixP->fx_addsy))
- return 0;
-
- if (S_IS_WEAK (fixP->fx_addsy))
- return 0;
-
- if (THUMB_IS_FUNC (fixP->fx_addsy)
- && fixP->fx_subsy == NULL)
- return 0;
-
- /* We need the symbol name for the VTABLE entries. */
- if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
- || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
- return 0;
-
- return 1;
-}
-
-const char *
-elf32_arm_target_format ()
-{
- if (target_big_endian)
- {
- if (target_oabi)
- return "elf32-bigarm-oabi";
- else
- return "elf32-bigarm";
- }
- else
- {
- if (target_oabi)
- return "elf32-littlearm-oabi";
- else
- return "elf32-littlearm";
- }
-}
-
-void
-armelf_frob_symbol (symp, puntp)
- symbolS * symp;
- int * puntp;
-{
- elf_frob_symbol (symp, puntp);
-}
-
-int
-arm_force_relocation (fixp)
- struct fix * fixp;
-{
- if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
- || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
- || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
- || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
- || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
- || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
- return 1;
-
- return 0;
-}
-
-static bfd_reloc_code_real_type
-arm_parse_reloc ()
-{
- char id [16];
- char * ip;
- unsigned int i;
- static struct
- {
- char * str;
- int len;
- bfd_reloc_code_real_type reloc;
- }
- reloc_map[] =
- {
-#define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
- MAP ("(got)", BFD_RELOC_ARM_GOT32),
- MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
- /* ScottB: Jan 30, 1998 - Added support for parsing "var(PLT)"
- branch instructions generated by GCC for PLT relocs. */
- MAP ("(plt)", BFD_RELOC_ARM_PLT32),
- { NULL, 0, BFD_RELOC_UNUSED }
-#undef MAP
- };
-
- for (i = 0, ip = input_line_pointer;
- i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
- i++, ip++)
- id[i] = tolower (*ip);
-
- for (i = 0; reloc_map[i].str; i++)
- if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
- break;
-
- input_line_pointer += reloc_map[i].len;
-
- return reloc_map[i].reloc;
-}
-
-static void
-s_arm_elf_cons (nbytes)
- int nbytes;
-{
- expressionS exp;
-
-#ifdef md_flush_pending_output
- md_flush_pending_output ();
-#endif
-
- if (is_it_end_of_statement ())
- {
- demand_empty_rest_of_line ();
- return;
- }
-
-#ifdef md_cons_align
- md_cons_align (nbytes);
-#endif
-
- do
- {
- bfd_reloc_code_real_type reloc;
-
- expression (& exp);
-
- if (exp.X_op == O_symbol
- && * input_line_pointer == '('
- && (reloc = arm_parse_reloc ()) != BFD_RELOC_UNUSED)
- {
- reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
- int size = bfd_get_reloc_size (howto);
-
- if (size > nbytes)
- as_bad ("%s relocations do not fit in %d bytes",
- howto->name, nbytes);
- else
- {
- register char *p = frag_more ((int) nbytes);
- int offset = nbytes - size;
-
- fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
- &exp, 0, reloc);
- }
- }
- else
- emit_expr (&exp, (unsigned int) nbytes);
- }
- while (*input_line_pointer++ == ',');
-
- /* Put terminator back into stream. */
- input_line_pointer --;
- demand_empty_rest_of_line ();
-}
-
-#endif /* OBJ_ELF */
-
-/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
- of an rs_align_code fragment. */
-
-void
-arm_handle_align (fragP)
- fragS *fragP;
-{
- static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
- static char const thumb_noop[2] = { 0xc0, 0x46 };
- static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
- static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
-
- int bytes, fix, noop_size;
- char * p;
- const char * noop;
-
- if (fragP->fr_type != rs_align_code)
- return;
-
- bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
- p = fragP->fr_literal + fragP->fr_fix;
- fix = 0;
-
- if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
- bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
-
- if (fragP->tc_frag_data)
- {
- if (target_big_endian)
- noop = thumb_bigend_noop;
- else
- noop = thumb_noop;
- noop_size = sizeof (thumb_noop);
- }
- else
- {
- if (target_big_endian)
- noop = arm_bigend_noop;
- else
- noop = arm_noop;
- noop_size = sizeof (arm_noop);
- }
-
- if (bytes & (noop_size - 1))
- {
- fix = bytes & (noop_size - 1);
- memset (p, 0, fix);
- p += fix;
- bytes -= fix;
- }
-
- while (bytes >= noop_size)
- {
- memcpy (p, noop, noop_size);
- p += noop_size;
- bytes -= noop_size;
- fix += noop_size;
- }
-
- fragP->fr_fix += fix;
- fragP->fr_var = noop_size;
-}
-
-/* Called from md_do_align. Used to create an alignment
- frag in a code section. */
-
-void
-arm_frag_align_code (n, max)
- int n;
- int max;
-{
- char * p;
-
- /* We assume that there will never be a requirment
- to support alignments greater than 32 bytes. */
- if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
- as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
-
- p = frag_var (rs_align_code,
- MAX_MEM_FOR_RS_ALIGN_CODE,
- 1,
- (relax_substateT) max,
- (symbolS *) NULL,
- (offsetT) n,
- (char *) NULL);
- *p = 0;
-
-}
-
-/* Perform target specific initialisation of a frag. */
-
-void
-arm_init_frag (fragP)
- fragS *fragP;
-{
- /* Record whether this frag is in an ARM or a THUMB area. */
- fragP->tc_frag_data = thumb_mode;
-}
diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am
index 5cd20f8..4d85018 100644
--- a/gas/doc/Makefile.am
+++ b/gas/doc/Makefile.am
@@ -65,14 +65,17 @@ MAINTAINERCLEANFILES = gasver.texi
# Maintenance
+# We need it for the taz target in ../../Makefile.in.
+info: $(MANS)
+
# Build the man page from the texinfo file
# The sed command removes the no-adjust Nroff command so that
# the man output looks standard.
-$(srcdir)/as.1: $(srcdir)/as.texinfo
- touch $(srcdir)/as.1
+as.1: $(srcdir)/as.texinfo
+ touch $@
-$(TEXI2POD) $(MANCONF) < $(srcdir)/as.texinfo > as.pod
-($(POD2MAN) as.pod | \
- sed -e '/^.if n .na/d' > $(srcdir)/as.1.T$$$$ && \
- mv -f $(srcdir)/as.1.T$$$$ $(srcdir)/as.1) || \
- (rm -f $(srcdir)/as.1.T$$$$ && exit 1)
-
+ sed -e '/^.if n .na/d' > $@.T$$$$ && \
+ mv -f $@.T$$$$ $@) || \
+ (rm -f $@.T$$$$ && exit 1)
+ rm -f as.pod
diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in
index 674e17f..90ebe51 100644
--- a/gas/doc/Makefile.in
+++ b/gas/doc/Makefile.in
@@ -183,7 +183,7 @@ DIST_COMMON = Makefile.am Makefile.in
DISTFILES = $(DIST_COMMON) $(SOURCES) $(HEADERS) $(TEXINFOS) $(EXTRA_DIST)
-TAR = tar
+TAR = gtar
GZIP_ENV = --best
all: all-redirect
.SUFFIXES:
@@ -457,16 +457,20 @@ as.dvi: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
# Maintenance
+# We need it for the taz target in ../../Makefile.in.
+info: $(MANS)
+
# Build the man page from the texinfo file
# The sed command removes the no-adjust Nroff command so that
# the man output looks standard.
-$(srcdir)/as.1: $(srcdir)/as.texinfo
- touch $(srcdir)/as.1
+as.1: $(srcdir)/as.texinfo
+ touch $@
-$(TEXI2POD) $(MANCONF) < $(srcdir)/as.texinfo > as.pod
-($(POD2MAN) as.pod | \
- sed -e '/^.if n .na/d' > $(srcdir)/as.1.T$$$$ && \
- mv -f $(srcdir)/as.1.T$$$$ $(srcdir)/as.1) || \
- (rm -f $(srcdir)/as.1.T$$$$ && exit 1)
+ sed -e '/^.if n .na/d' > $@.T$$$$ && \
+ mv -f $@.T$$$$ $@) || \
+ (rm -f $@.T$$$$ && exit 1)
+ rm -f as.pod
# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
diff --git a/gas/doc/as.1 b/gas/doc/as.1
deleted file mode 100644
index 28ba51f..0000000
--- a/gas/doc/as.1
+++ /dev/null
@@ -1,724 +0,0 @@
-.\" Automatically generated by Pod::Man version 1.02
-.\" Tue Jun 12 18:27:35 2001
-.\"
-.\" Standard preamble:
-.\" ======================================================================
-.de Sh \" Subsection heading
-.br
-.if t .Sp
-.ne 5
-.PP
-\fB\\$1\fR
-.PP
-..
-.de Sp \" Vertical space (when we can't use .PP)
-.if t .sp .5v
-.if n .sp
-..
-.de Ip \" List item
-.br
-.ie \\n(.$>=3 .ne \\$3
-.el .ne 3
-.IP "\\$1" \\$2
-..
-.de Vb \" Begin verbatim text
-.ft CW
-.nf
-.ne \\$1
-..
-.de Ve \" End verbatim text
-.ft R
-
-.fi
-..
-.\" Set up some character translations and predefined strings. \*(-- will
-.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left
-.\" double quote, and \*(R" will give a right double quote. | will give a
-.\" real vertical bar. \*(C+ will give a nicer C++. Capital omega is used
-.\" to do unbreakable dashes and therefore won't be available. \*(C` and
-.\" \*(C' expand to `' in nroff, nothing in troff, for use with C<>
-.tr \(*W-|\(bv\*(Tr
-.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p'
-.ie n \{\
-. ds -- \(*W-
-. ds PI pi
-. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
-. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
-. ds L" ""
-. ds R" ""
-. ds C` `
-. ds C' '
-'br\}
-.el\{\
-. ds -- \|\(em\|
-. ds PI \(*p
-. ds L" ``
-. ds R" ''
-'br\}
-.\"
-.\" If the F register is turned on, we'll generate index entries on stderr
-.\" for titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and
-.\" index entries marked with X<> in POD. Of course, you'll have to process
-.\" the output yourself in some meaningful fashion.
-.if \nF \{\
-. de IX
-. tm Index:\\$1\t\\n%\t"\\$2"
-. .
-. nr % 0
-. rr F
-.\}
-.\"
-.\" For nroff, turn off justification. Always turn off hyphenation; it
-.\" makes way too many mistakes in technical documents.
-.hy 0
-.\"
-.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2).
-.\" Fear. Run. Save yourself. No user-serviceable parts.
-.bd B 3
-. \" fudge factors for nroff and troff
-.if n \{\
-. ds #H 0
-. ds #V .8m
-. ds #F .3m
-. ds #[ \f1
-. ds #] \fP
-.\}
-.if t \{\
-. ds #H ((1u-(\\\\n(.fu%2u))*.13m)
-. ds #V .6m
-. ds #F 0
-. ds #[ \&
-. ds #] \&
-.\}
-. \" simple accents for nroff and troff
-.if n \{\
-. ds ' \&
-. ds ` \&
-. ds ^ \&
-. ds , \&
-. ds ~ ~
-. ds /
-.\}
-.if t \{\
-. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
-. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
-. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u'
-. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u'
-. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u'
-. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u'
-.\}
-. \" troff and (daisy-wheel) nroff accents
-.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V'
-.ds 8 \h'\*(#H'\(*b\h'-\*(#H'
-.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#]
-.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H'
-.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u'
-.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#]
-.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#]
-.ds ae a\h'-(\w'a'u*4/10)'e
-.ds Ae A\h'-(\w'A'u*4/10)'E
-. \" corrections for vroff
-.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u'
-.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u'
-. \" for low resolution devices (crt and lpr)
-.if \n(.H>23 .if \n(.V>19 \
-\{\
-. ds : e
-. ds 8 ss
-. ds o a
-. ds d- d\h'-1'\(ga
-. ds D- D\h'-1'\(hy
-. ds th \o'bp'
-. ds Th \o'LP'
-. ds ae ae
-. ds Ae AE
-.\}
-.rm #[ #] #H #V #F C
-.\" ======================================================================
-.\"
-.IX Title "AS 1"
-.TH AS 1 "binutils-2.11.90" "2001-06-12" "GNU"
-.UC
-.SH "NAME"
-\&\s-1AS\s0 \- the portable \s-1GNU\s0 assembler.
-.SH "SYNOPSIS"
-.IX Header "SYNOPSIS"
-as [ \-a[cdhlns][=file] ] [ \-D ] [ \-\-defsym \fIsym\fR=\fIval\fR ]
- [ \-f ] [ \-\-gstabs ] [ \-\-gdwarf2 ] [ \-\-help ] [ \-I \fIdir\fR ]
- [ \-J ] [ \-K ] [ \-L ]
- [ \-\-listing\*(--lhs-width=NUM ][ \-\-listing-lhs-width2=NUM ]
- [ \-\-listing-rhs-width=NUM ][ \-\-listing-cont-lines=NUM ]
- [ \-\-keep-locals ] [ \-o \fIobjfile\fR ] [ \-R ] [ \-\-statistics ] [ \-v ]
- [ \-version ] [ \-\-version ] [ \-W ] [ \-\-warn ] [ \-\-fatal-warnings ]
- [ \-w ] [ \-x ] [ \-Z ] [ \-\-target-help ]
- [ \-marc[5|6|7|8] ]
- [ \-EB | \-EL ]
- [ \-m[arm]1 | \-m[arm]2 | \-m[arm]250 | \-m[arm]3 |
- \-m[arm]6 | \-m[arm]60 | \-m[arm]600 | \-m[arm]610 |
- \-m[arm]620 | \-m[arm]7[t][[d]m[i]][fe] | \-m[arm]70 |
- \-m[arm]700 | \-m[arm]710[c] | \-m[arm]7100 |
- \-m[arm]7500 | \-m[arm]8 | \-m[arm]810 | \-m[arm]9 |
- \-m[arm]920 | \-m[arm]920t | \-m[arm]9tdmi |
- \-mstrongarm | \-mstrongarm110 | \-mstrongarm1100 ]
- [ \-m[arm]v2 | \-m[arm]v2a | \-m[arm]v3 | \-m[arm]v3m |
- \-m[arm]v4 | \-m[arm]v4t | \-m[arm]v5 | \-[arm]v5t |
- \-[arm]v5te ]
- [ \-mthumb | \-mall ]
- [ \-mfpa10 | \-mfpa11 | \-mfpe-old | \-mno-fpu ]
- [ \-EB | \-EL ]
- [ \-mapcs-32 | \-mapcs-26 | \-mapcs-float |
- \-mapcs-reentrant ]
- [ \-mthumb-interwork ] [ \-moabi ] [ \-k ]
- [ \-O ]
- [ \-O | \-n | \-N ]
- [ \-mb | \-me ]
- [ \-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite
- \-Av8plus | \-Av8plusa | \-Av9 | \-Av9a ]
- [ \-xarch=v8plus | \-xarch=v8plusa ] [ \-bump ]
- [ \-32 | \-64 ]
- [ \-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB |
- \-AKC | \-AMC ]
- [ \-b ] [ \-no-relax ]
- [ \-\-m32rx | \-\-[no-]warn-explicit-parallel-conflicts |
- \-\-W[n]p ]
- [ \-l ] [ \-m68000 | \-m68010 | \-m68020 | ... ]
- [ \-jsri2bsr ] [ \-sifilter ] [ \-relax ]
- [ \-mcpu=[210|340] ]
- [ \-m68hc11 | \-m68hc12 ]
- [ \-\-force-long-branchs ] [ \-\-short-branchs ]
- [ \-\-strict-direct-mode ] [ \-\-print-insn-syntax ]
- [ \-\-print-opcodes ] [ \-\-generate-example ]
- [ \-nocpp ] [ \-EL ] [ \-EB ] [ \-G \fInum\fR ] [ \-mcpu=\fI\s-1CPU\s0\fR ]
- [ \-mips1 ] [ \-mips2 ] [ \-mips3 ] [ \-mips4 ] [ \-mips5 ]
- [ \-mips32 ] [ \-mips64 ]
- [ \-m4650 ] [ \-no-m4650 ]
- [ \-\-trap ] [ \-\-break ] [ \-n ]
- [ \-\-emulation=\fIname\fR ]
- [ \*(-- | \fIfiles\fR ... ]
-.SH "DESCRIPTION"
-.IX Header "DESCRIPTION"
-\&\s-1GNU\s0 \f(CW\*(C`as\*(C'\fR is really a family of assemblers.
-If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you
-should find a fairly similar environment when you use it on another
-architecture. Each version has much in common with the others,
-including object file formats, most assembler directives (often called
-\&\fIpseudo-ops\fR) and assembler syntax.
-.PP
-\&\f(CW\*(C`as\*(C'\fR is primarily intended to assemble the output of the
-\&\s-1GNU\s0 C compiler for use by the linker
-\&. Nevertheless, we've tried to make \f(CW\*(C`as\*(C'\fR
-assemble correctly everything that other assemblers for the same
-machine would assemble.
-Any exceptions are documented explicitly.
-This doesn't mean \f(CW\*(C`as\*(C'\fR always uses the same syntax as another
-assembler for the same architecture; for example, we know of several
-incompatible versions of 680x0 assembly language syntax.
-.PP
-Each time you run \f(CW\*(C`as\*(C'\fR it assembles exactly one source
-program. The source program is made up of one or more files.
-(The standard input is also a file.)
-.PP
-You give \f(CW\*(C`as\*(C'\fR a command line that has zero or more input file
-names. The input files are read (from left file name to right). A
-command line argument (in any position) that has no special meaning
-is taken to be an input file name.
-.PP
-If you give \f(CW\*(C`as\*(C'\fR no file names it attempts to read one input file
-from the \f(CW\*(C`as\*(C'\fR standard input, which is normally your terminal. You
-may have to type \fBctl-D\fR to tell \f(CW\*(C`as\*(C'\fR there is no more program
-to assemble.
-.PP
-Use \fB\--\fR if you need to explicitly name the standard input file
-in your command line.
-.PP
-If the source is empty, \f(CW\*(C`as\*(C'\fR produces a small, empty object
-file.
-.PP
-\&\f(CW\*(C`as\*(C'\fR may write warnings and error messages to the standard error
-file (usually your terminal). This should not happen when a compiler
-runs \f(CW\*(C`as\*(C'\fR automatically. Warnings report an assumption made so
-that \f(CW\*(C`as\*(C'\fR could keep assembling a flawed program; errors report a
-grave problem that stops the assembly.
-.PP
-If you are invoking \f(CW\*(C`as\*(C'\fR via the \s-1GNU\s0 C compiler (version 2),
-you can use the \fB\-Wa\fR option to pass arguments through to the assembler.
-The assembler arguments must be separated from each other (and the \fB\-Wa\fR)
-by commas. For example:
-.PP
-.Vb 1
-\& gcc -c -g -O -Wa,-alh,-L file.c
-.Ve
-This passes two options to the assembler: \fB\-alh\fR (emit a listing to
-standard output with with high-level and assembly source) and \fB\-L\fR (retain
-local symbols in the symbol table).
-.PP
-Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler
-command-line options are automatically passed to the assembler by the compiler.
-(You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see
-precisely what options it passes to each compilation pass, including the
-assembler.)
-.SH "OPTIONS"
-.IX Header "OPTIONS"
-.Ip "\f(CW\*(C`\-a[cdhlmns]\*(C'\fR" 4
-.IX Item "-a[cdhlmns]"
-Turn on listings, in any of a variety of ways:
-.RS 4
-.Ip "\f(CW\*(C`\-ac\*(C'\fR" 4
-.IX Item "-ac"
-omit false conditionals
-.Ip "\f(CW\*(C`\-ad\*(C'\fR" 4
-.IX Item "-ad"
-omit debugging directives
-.Ip "\f(CW\*(C`\-ah\*(C'\fR" 4
-.IX Item "-ah"
-include high-level source
-.Ip "\f(CW\*(C`\-al\*(C'\fR" 4
-.IX Item "-al"
-include assembly
-.Ip "\f(CW\*(C`\-am\*(C'\fR" 4
-.IX Item "-am"
-include macro expansions
-.Ip "\f(CW\*(C`\-an\*(C'\fR" 4
-.IX Item "-an"
-omit forms processing
-.Ip "\f(CW\*(C`\-as\*(C'\fR" 4
-.IX Item "-as"
-include symbols
-.Ip "\f(CW\*(C`=file\*(C'\fR" 4
-.IX Item "=file"
-set the name of the listing file
-.RE
-.RS 4
-.Sp
-You may combine these options; for example, use \fB\-aln\fR for assembly
-listing without forms processing. The \fB=file\fR option, if used, must be
-the last one. By itself, \fB\-a\fR defaults to \fB\-ahls\fR.
-.RE
-.Ip "\f(CW\*(C`\-D\*(C'\fR" 4
-.IX Item "-D"
-Ignored. This option is accepted for script compatibility with calls to
-other assemblers.
-.Ip "\f(CW\*(C`\-\-defsym \f(CIsym\f(CW=\f(CIvalue\f(CW\*(C'\fR" 4
-.IX Item "--defsym sym=value"
-Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file.
-\&\fIvalue\fR must be an integer constant. As in C, a leading \fB0x\fR
-indicates a hexadecimal value, and a leading \fB0\fR indicates an octal value.
-.Ip "\f(CW\*(C`\-f\*(C'\fR" 4
-.IX Item "-f"
-``fast''\-\-\-skip whitespace and comment preprocessing (assume source is
-compiler output).
-.Ip "\f(CW\*(C`\-\-gstabs\*(C'\fR" 4
-.IX Item "--gstabs"
-Generate stabs debugging information for each assembler line. This
-may help debugging assembler code, if the debugger can handle it.
-.Ip "\f(CW\*(C`\-\-gdwarf2\*(C'\fR" 4
-.IX Item "--gdwarf2"
-Generate \s-1DWARF2\s0 debugging information for each assembler line. This
-may help debugging assembler code, if the debugger can handle it. Note \- this
-option is only supported by some targets, not all of them.
-.Ip "\f(CW\*(C`\-\-help\*(C'\fR" 4
-.IX Item "--help"
-Print a summary of the command line options and exit.
-.Ip "\f(CW\*(C`\-\-target\-help\*(C'\fR" 4
-.IX Item "--target-help"
-Print a summary of all target specific options and exit.
-.Ip "\f(CW\*(C`\-I \f(CIdir\f(CW\*(C'\fR" 4
-.IX Item "-I dir"
-Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives.
-.Ip "\f(CW\*(C`\-J\*(C'\fR" 4
-.IX Item "-J"
-Don't warn about signed overflow.
-.Ip "\f(CW\*(C`\-K\*(C'\fR" 4
-.IX Item "-K"
-This option is accepted but has no effect on the \s-1TARGET\s0 family.
-.Ip "\f(CW\*(C`\-L\*(C'\fR" 4
-.IX Item "-L"
-.Ip "\f(CW\*(C`\-\-keep\-locals\*(C'\fR" 4
-.IX Item "--keep-locals"
-Keep (in the symbol table) local symbols. On traditional a.out systems
-these start with \fBL\fR, but different systems have different local
-label prefixes.
-.Ip "\f(CW\*(C`\-\-listing\-lhs\-width=\f(CInumber\f(CW\*(C'\fR" 4
-.IX Item "--listing-lhs-width=number"
-Set the maximum width, in words, of the output data column for an assembler
-listing to \fInumber\fR.
-.Ip "\f(CW\*(C`\-\-listing\-lhs\-width2=\f(CInumber\f(CW\*(C'\fR" 4
-.IX Item "--listing-lhs-width2=number"
-Set the maximum width, in words, of the output data column for continuation
-lines in an assembler listing to \fInumber\fR.
-.Ip "\f(CW\*(C`\-\-listing\-rhs\-width=\f(CInumber\f(CW\*(C'\fR" 4
-.IX Item "--listing-rhs-width=number"
-Set the maximum width of an input source line, as displayed in a listing, to
-\&\fInumber\fR bytes.
-.Ip "\f(CW\*(C`\-\-listing\-cont\-lines=\f(CInumber\f(CW\*(C'\fR" 4
-.IX Item "--listing-cont-lines=number"
-Set the maximum number of lines printed in a listing for a single line of input
-to \fInumber\fR + 1.
-.Ip "\f(CW\*(C`\-o \f(CIobjfile\f(CW\*(C'\fR" 4
-.IX Item "-o objfile"
-Name the object-file output from \f(CW\*(C`as\*(C'\fR \fIobjfile\fR.
-.Ip "\f(CW\*(C`\-R\*(C'\fR" 4
-.IX Item "-R"
-Fold the data section into the text section.
-.Ip "\f(CW\*(C`\-\-statistics\*(C'\fR" 4
-.IX Item "--statistics"
-Print the maximum space (in bytes) and total time (in seconds) used by
-assembly.
-.Ip "\f(CW\*(C`\-\-strip\-local\-absolute\*(C'\fR" 4
-.IX Item "--strip-local-absolute"
-Remove local absolute symbols from the outgoing symbol table.
-.Ip "\f(CW\*(C`\-v\*(C'\fR" 4
-.IX Item "-v"
-.Ip "\f(CW\*(C`\-version\*(C'\fR" 4
-.IX Item "-version"
-Print the \f(CW\*(C`as\*(C'\fR version.
-.Ip "\f(CW\*(C`\-\-version\*(C'\fR" 4
-.IX Item "--version"
-Print the \f(CW\*(C`as\*(C'\fR version and exit.
-.Ip "\f(CW\*(C`\-W\*(C'\fR" 4
-.IX Item "-W"
-.Ip "\f(CW\*(C`\-\-no\-warn\*(C'\fR" 4
-.IX Item "--no-warn"
-Suppress warning messages.
-.Ip "\f(CW\*(C`\-\-fatal\-warnings\*(C'\fR" 4
-.IX Item "--fatal-warnings"
-Treat warnings as errors.
-.Ip "\f(CW\*(C`\-\-warn\*(C'\fR" 4
-.IX Item "--warn"
-Don't suppress warning messages or treat them as errors.
-.Ip "\f(CW\*(C`\-w\*(C'\fR" 4
-.IX Item "-w"
-Ignored.
-.Ip "\f(CW\*(C`\-x\*(C'\fR" 4
-.IX Item "-x"
-Ignored.
-.Ip "\f(CW\*(C`\-Z\*(C'\fR" 4
-.IX Item "-Z"
-Generate an object file even after errors.
-.Ip "\f(CW\*(C`\-\- | \f(CIfiles\f(CW ...\*(C'\fR" 4
-.IX Item "-- | files ..."
-Standard input, or source files to assemble.
-.PP
-The following options are available when as is configured for
-an \s-1ARC\s0 processor.
-.Ip "\f(CW\*(C`\-marc[5|6|7|8]\*(C'\fR" 4
-.IX Item "-marc[5|6|7|8]"
-This option selects the core processor variant.
-.Ip "\f(CW\*(C`\-EB | \-EL\*(C'\fR" 4
-.IX Item "-EB | -EL"
-Select either big-endian (\-EB) or little-endian (\-EL) output.
-.PP
-The following options are available when as is configured for the \s-1ARM\s0
-processor family.
-.Ip "\f(CW\*(C`\-m[arm][1|2|3|6|7|8|9][...] \*(C'\fR" 4
-.IX Item "-m[arm][1|2|3|6|7|8|9][...] "
-Specify which \s-1ARM\s0 processor variant is the target.
-.Ip "\f(CW\*(C`\-m[arm]v[2|2a|3|3m|4|4t|5|5t]\*(C'\fR" 4
-.IX Item "-m[arm]v[2|2a|3|3m|4|4t|5|5t]"
-Specify which \s-1ARM\s0 architecture variant is used by the target.
-.Ip "\f(CW\*(C`\-mthumb | \-mall\*(C'\fR" 4
-.IX Item "-mthumb | -mall"
-Enable or disable Thumb only instruction decoding.
-.Ip "\f(CW\*(C`\-mfpa10 | \-mfpa11 | \-mfpe\-old | \-mno\-fpu\*(C'\fR" 4
-.IX Item "-mfpa10 | -mfpa11 | -mfpe-old | -mno-fpu"
-Select which Floating Point architecture is the target.
-.Ip "\f(CW\*(C`\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant | \-moabi\*(C'\fR" 4
-.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant | -moabi"
-Select which procedure calling convention is in use.
-.Ip "\f(CW\*(C`\-EB | \-EL\*(C'\fR" 4
-.IX Item "-EB | -EL"
-Select either big-endian (\-EB) or little-endian (\-EL) output.
-.Ip "\f(CW\*(C`\-mthumb\-interwork\*(C'\fR" 4
-.IX Item "-mthumb-interwork"
-Specify that the code has been generated with interworking between Thumb and
-\&\s-1ARM\s0 code in mind.
-.Ip "\f(CW\*(C`\-k\*(C'\fR" 4
-.IX Item "-k"
-Specify that \s-1PIC\s0 code has been generated.
-.PP
-The following options are available when as is configured for
-a D10V processor.
-.Ip "\f(CW\*(C`\-O\*(C'\fR" 4
-.IX Item "-O"
-Optimize output by parallelizing instructions.
-.PP
-The following options are available when as is configured for a D30V
-processor.
-.Ip "\f(CW\*(C`\-O\*(C'\fR" 4
-.IX Item "-O"
-Optimize output by parallelizing instructions.
-.Ip "\f(CW\*(C`\-n\*(C'\fR" 4
-.IX Item "-n"
-Warn when nops are generated.
-.Ip "\f(CW\*(C`\-N\*(C'\fR" 4
-.IX Item "-N"
-Warn when a nop after a 32\-bit multiply instruction is generated.
-.PP
-The following options are available when as is configured for the
-Intel 80960 processor.
-.Ip "\f(CW\*(C`\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\*(C'\fR" 4
-.IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC"
-Specify which variant of the 960 architecture is the target.
-.Ip "\f(CW\*(C`\-b\*(C'\fR" 4
-.IX Item "-b"
-Add code to collect statistics about branches taken.
-.Ip "\f(CW\*(C`\-no\-relax\*(C'\fR" 4
-.IX Item "-no-relax"
-Do not alter compare-and-branch instructions for long displacements;
-error if necessary.
-.PP
-The following options are available when as is configured for the
-Mitsubishi M32R series.
-.Ip "\f(CW\*(C`\-\-m32rx\*(C'\fR" 4
-.IX Item "--m32rx"
-Specify which processor in the M32R family is the target. The default
-is normally the M32R, but this option changes it to the M32RX.
-.Ip "\f(CW\*(C`\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\*(C'\fR" 4
-.IX Item "--warn-explicit-parallel-conflicts or --Wp"
-Produce warning messages when questionable parallel constructs are
-encountered.
-.Ip "\f(CW\*(C`\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\*(C'\fR" 4
-.IX Item "--no-warn-explicit-parallel-conflicts or --Wnp"
-Do not produce warning messages when questionable parallel constructs are
-encountered.
-.PP
-The following options are available when as is configured for the
-Motorola 68000 series.
-.Ip "\f(CW\*(C`\-l\*(C'\fR" 4
-.IX Item "-l"
-Shorten references to undefined symbols, to one word instead of two.
-.Ip "\f(CW\*(C`\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\*(C'\fR" 4
-.IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030"
-.Ip "\f(CW\*(C`| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\*(C'\fR" 4
-.IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332"
-.Ip "\f(CW\*(C`| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\*(C'\fR" 4
-.IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200"
-Specify what processor in the 68000 family is the target. The default
-is normally the 68020, but this can be changed at configuration time.
-.Ip "\f(CW\*(C`\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\*(C'\fR" 4
-.IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882"
-The target machine does (or does not) have a floating-point coprocessor.
-The default is to assume a coprocessor for 68020, 68030, and cpu32. Although
-the basic 68000 is not compatible with the 68881, a combination of the
-two can be specified, since it's possible to do emulation of the
-coprocessor instructions with the main processor.
-.Ip "\f(CW\*(C`\-m68851 | \-mno\-68851\*(C'\fR" 4
-.IX Item "-m68851 | -mno-68851"
-The target machine does (or does not) have a memory-management
-unit coprocessor. The default is to assume an \s-1MMU\s0 for 68020 and up.
-.PP
-For details about the \s-1PDP-11\s0 machine dependent features options,
-see \f(CW@ref\fR{PDP-11\-Options}.
-.Ip "\f(CW\*(C`\-mpic | \-mno\-pic\*(C'\fR" 4
-.IX Item "-mpic | -mno-pic"
-Generate position-independent (or position-dependent) code. The
-default is \f(CW\*(C`\-mpic\*(C'\fR.
-.Ip "\f(CW\*(C`\-mall\*(C'\fR" 4
-.IX Item "-mall"
-.Ip "\f(CW\*(C`\-mall\-extensions\*(C'\fR" 4
-.IX Item "-mall-extensions"
-Enable all instruction set extensions. This is the default.
-.Ip "\f(CW\*(C`\-mno\-extensions\*(C'\fR" 4
-.IX Item "-mno-extensions"
-Disable all instruction set extensions.
-.Ip "\f(CW\*(C`\-m\f(CIextension\f(CW | \-mno\-\f(CIextension\f(CW\*(C'\fR" 4
-.IX Item "-mextension | -mno-extension"
-Enable (or disable) a particular instruction set extension.
-.Ip "\f(CW\*(C`\-m\f(CIcpu\f(CW\*(C'\fR" 4
-.IX Item "-mcpu"
-Enable the instruction set extensions supported by a particular \s-1CPU\s0, and
-disable all other extensions.
-.Ip "\f(CW\*(C`\-m\f(CImachine\f(CW\*(C'\fR" 4
-.IX Item "-mmachine"
-Enable the instruction set extensions supported by a particular machine
-model, and disable all other extensions.
-.PP
-The following options are available when as is configured for
-a picoJava processor.
-.Ip "\f(CW\*(C`\-mb\*(C'\fR" 4
-.IX Item "-mb"
-Generate ``big endian'' format output.
-.Ip "\f(CW\*(C`\-ml\*(C'\fR" 4
-.IX Item "-ml"
-Generate ``little endian'' format output.
-.PP
-The following options are available when as is configured for the
-Motorola 68HC11 or 68HC12 series.
-.Ip "\f(CW\*(C`\-m68hc11 | \-m68hc12\*(C'\fR" 4
-.IX Item "-m68hc11 | -m68hc12"
-Specify what processor is the target. The default is
-defined by the configuration option when building the assembler.
-.Ip "\f(CW\*(C`\-\-force\-long\-branchs\*(C'\fR" 4
-.IX Item "--force-long-branchs"
-Relative branches are turned into absolute ones. This concerns
-conditional branches, unconditional branches and branches to a
-sub routine.
-.Ip "\f(CW\*(C`\-S | \-\-short\-branchs\*(C'\fR" 4
-.IX Item "-S | --short-branchs"
-Do not turn relative branchs into absolute ones
-when the offset is out of range.
-.Ip "\f(CW\*(C`\-\-strict\-direct\-mode\*(C'\fR" 4
-.IX Item "--strict-direct-mode"
-Do not turn the direct addressing mode into extended addressing mode
-when the instruction does not support direct addressing mode.
-.Ip "\f(CW\*(C`\-\-print\-insn\-syntax\*(C'\fR" 4
-.IX Item "--print-insn-syntax"
-Print the syntax of instruction in case of error.
-.Ip "\f(CW\*(C`\-\-print\-opcodes\*(C'\fR" 4
-.IX Item "--print-opcodes"
-print the list of instructions with syntax and then exit.
-.Ip "\f(CW\*(C`\-\-generate\-example\*(C'\fR" 4
-.IX Item "--generate-example"
-print an example of instruction for each possible instruction and then exit.
-This option is only useful for testing \f(CW\*(C`as\*(C'\fR.
-.PP
-The following options are available when \f(CW\*(C`as\*(C'\fR is configured
-for the \s-1SPARC\s0 architecture:
-.Ip "\f(CW\*(C`\-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite\*(C'\fR" 4
-.IX Item "-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite"
-.Ip "\f(CW\*(C`\-Av8plus | \-Av8plusa | \-Av9 | \-Av9a\*(C'\fR" 4
-.IX Item "-Av8plus | -Av8plusa | -Av9 | -Av9a"
-Explicitly select a variant of the \s-1SPARC\s0 architecture.
-.Sp
-\&\fB\-Av8plus\fR and \fB\-Av8plusa\fR select a 32 bit environment.
-\&\fB\-Av9\fR and \fB\-Av9a\fR select a 64 bit environment.
-.Sp
-\&\fB\-Av8plusa\fR and \fB\-Av9a\fR enable the \s-1SPARC\s0 V9 instruction set with
-UltraSPARC extensions.
-.Ip "\f(CW\*(C`\-xarch=v8plus | \-xarch=v8plusa\*(C'\fR" 4
-.IX Item "-xarch=v8plus | -xarch=v8plusa"
-For compatibility with the Solaris v9 assembler. These options are
-equivalent to \-Av8plus and \-Av8plusa, respectively.
-.Ip "\f(CW\*(C`\-bump\*(C'\fR" 4
-.IX Item "-bump"
-Warn when the assembler switches to another architecture.
-.PP
-The following options are available when as is configured for
-a \s-1MIPS\s0 processor.
-.Ip "\f(CW\*(C`\-G \f(CInum\f(CW\*(C'\fR" 4
-.IX Item "-G num"
-This option sets the largest size of an object that can be referenced
-implicitly with the \f(CW\*(C`gp\*(C'\fR register. It is only accepted for targets that
-use \s-1ECOFF\s0 format, such as a DECstation running Ultrix. The default value is 8.
-.Ip "\f(CW\*(C`\-EB\*(C'\fR" 4
-.IX Item "-EB"
-Generate ``big endian'' format output.
-.Ip "\f(CW\*(C`\-EL\*(C'\fR" 4
-.IX Item "-EL"
-Generate ``little endian'' format output.
-.Ip "\f(CW\*(C`\-mips1\*(C'\fR" 4
-.IX Item "-mips1"
-.Ip "\f(CW\*(C`\-mips2\*(C'\fR" 4
-.IX Item "-mips2"
-.Ip "\f(CW\*(C`\-mips3\*(C'\fR" 4
-.IX Item "-mips3"
-.Ip "\f(CW\*(C`\-mips4\*(C'\fR" 4
-.IX Item "-mips4"
-.Ip "\f(CW\*(C`\-mips32\*(C'\fR" 4
-.IX Item "-mips32"
-Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level.
-\&\fB\-mips1\fR corresponds to the R2000 and R3000 processors,
-\&\fB\-mips2\fR to the R6000 processor, and \fB\-mips3\fR to the R4000
-processor.
-\&\fB\-mips5\fR, \fB\-mips32\fR, and \fB\-mips64\fR correspond
-to generic \s-1MIPS\s0 V, \s-1MIPS32\s0, and \s-1MIPS64\s0 \s-1ISA\s0
-processors, respectively.
-.Ip "\f(CW\*(C`\-m4650\*(C'\fR" 4
-.IX Item "-m4650"
-.Ip "\f(CW\*(C`\-no\-m4650\*(C'\fR" 4
-.IX Item "-no-m4650"
-Generate code for the \s-1MIPS\s0 R4650 chip. This tells the assembler to accept
-the \fBmad\fR and \fBmadu\fR instruction, and to not schedule \fBnop\fR
-instructions around accesses to the \fB\s-1HI\s0\fR and \fB\s-1LO\s0\fR registers.
-\&\fB\-no-m4650\fR turns off this option.
-.Ip "\f(CW\*(C`\-mcpu=\f(CI\s\-1CPU\s0\f(CW\*(C'\fR" 4
-.IX Item "-mcpu=CPU"
-Generate code for a particular \s-1MIPS\s0 cpu. It is exactly equivalent to
-\&\fB\-m\fR\fIcpu\fR, except that there are more value of \fIcpu\fR
-understood.
-.Ip "\f(CW\*(C`\-\-emulation=\f(CIname\f(CW\*(C'\fR" 4
-.IX Item "--emulation=name"
-This option causes \f(CW\*(C`as\*(C'\fR to emulate \f(CW\*(C`as\*(C'\fR configured
-for some other target, in all respects, including output format (choosing
-between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate
-debugging information or store symbol table information, and default
-endianness. The available configuration names are: \fBmipsecoff\fR,
-\&\fBmipself\fR, \fBmipslecoff\fR, \fBmipsbecoff\fR, \fBmipslelf\fR,
-\&\fBmipsbelf\fR. The first two do not alter the default endianness from that
-of the primary target for which the assembler was configured; the others change
-the default to little- or big-endian as indicated by the \fBb\fR or \fBl\fR
-in the name. Using \fB\-EB\fR or \fB\-EL\fR will override the endianness
-selection in any case.
-.Sp
-This option is currently supported only when the primary target
-\&\f(CW\*(C`as\*(C'\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target.
-Furthermore, the primary target or others specified with
-\&\fB\*(--enable-targets=...\fR at configuration time must include support for
-the other format, if both are to be available. For example, the Irix 5
-configuration includes support for both.
-.Sp
-Eventually, this option will support more configurations, with more
-fine-grained control over the assembler's behavior, and will be supported for
-more processors.
-.Ip "\f(CW\*(C`\-nocpp\*(C'\fR" 4
-.IX Item "-nocpp"
-\&\f(CW\*(C`as\*(C'\fR ignores this option. It is accepted for compatibility with
-the native tools.
-.Ip "\f(CW\*(C`\-\-trap\*(C'\fR" 4
-.IX Item "--trap"
-.Ip "\f(CW\*(C`\-\-no\-trap\*(C'\fR" 4
-.IX Item "--no-trap"
-.Ip "\f(CW\*(C`\-\-break\*(C'\fR" 4
-.IX Item "--break"
-.Ip "\f(CW\*(C`\-\-no\-break\*(C'\fR" 4
-.IX Item "--no-break"
-Control how to deal with multiplication overflow and division by zero.
-\&\fB\*(--trap\fR or \fB\*(--no-break\fR (which are synonyms) take a trap exception
-(and only work for Instruction Set Architecture level 2 and higher);
-\&\fB\*(--break\fR or \fB\*(--no-trap\fR (also synonyms, and the default) take a
-break exception.
-.Ip "\f(CW\*(C`\-n\*(C'\fR" 4
-.IX Item "-n"
-When this option is used, \f(CW\*(C`as\*(C'\fR will issue a warning every
-time it generates a nop instruction from a macro.
-.PP
-The following options are available when as is configured for
-an MCore processor.
-.Ip "\f(CW\*(C`\-jsri2bsr\*(C'\fR" 4
-.IX Item "-jsri2bsr"
-.Ip "\f(CW\*(C`\-nojsri2bsr\*(C'\fR" 4
-.IX Item "-nojsri2bsr"
-Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation. By default this is enabled.
-The command line option \fB\-nojsri2bsr\fR can be used to disable it.
-.Ip "\f(CW\*(C`\-sifilter\*(C'\fR" 4
-.IX Item "-sifilter"
-.Ip "\f(CW\*(C`\-nosifilter\*(C'\fR" 4
-.IX Item "-nosifilter"
-Enable or disable the silicon filter behaviour. By default this is disabled.
-The default can be overridden by the \fB\-sifilter\fR command line option.
-.Ip "\f(CW\*(C`\-relax\*(C'\fR" 4
-.IX Item "-relax"
-Alter jump instructions for long displacements.
-.Ip "\f(CW\*(C`\-mcpu=[210|340]\*(C'\fR" 4
-.IX Item "-mcpu=[210|340]"
-Select the cpu type on the target hardware. This controls which instructions
-can be assembled.
-.Ip "\f(CW\*(C`\-EB\*(C'\fR" 4
-.IX Item "-EB"
-Assemble for a big endian target.
-.Ip "\f(CW\*(C`\-EL\*(C'\fR" 4
-.IX Item "-EL"
-Assemble for a little endian target.
-.SH "SEE ALSO"
-.IX Header "SEE ALSO"
-\&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.
-.SH "COPYRIGHT"
-.IX Header "COPYRIGHT"
-Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001 Free Software Foundation, Inc.
-.PP
-Permission is granted to copy, distribute and/or modify this document
-under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1
-or any later version published by the Free Software Foundation;
-with no Invariant Sections, with no Front-Cover Texts, and with no
-Back-Cover Texts. A copy of the license is included in the
-section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".
diff --git a/gas/po/POTFILES.in b/gas/po/POTFILES.in
index 11518ed..d103832 100644
--- a/gas/po/POTFILES.in
+++ b/gas/po/POTFILES.in
@@ -92,6 +92,8 @@ config/tc-mn10300.c
config/tc-mn10300.h
config/tc-ns32k.c
config/tc-ns32k.h
+config/tc-openrisc.c
+config/tc-openrisc.h
config/tc-pdp11.c
config/tc-pdp11.h
config/tc-pj.c
diff --git a/gas/po/gas.pot b/gas/po/gas.pot
index 14ec278..23b2e24 100644
--- a/gas/po/gas.pot
+++ b/gas/po/gas.pot
@@ -6,7 +6,7 @@
msgid ""
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2001-04-27 15:23+0100\n"
+"POT-Creation-Date: 2001-06-13 12:54+0100\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
@@ -95,144 +95,142 @@ msgid ""
" \t m include macro expansions\n"
" \t n omit forms processing\n"
" \t s include symbols\n"
-" \t L include line debug statistics (if "
-"applicable)\n"
" \t =FILE list to FILE (must be last sub-option)\n"
msgstr ""
-#: as.c:238
+#: as.c:237
msgid " -D produce assembler debugging messages\n"
msgstr ""
-#: as.c:240
+#: as.c:239
msgid " --defsym SYM=VAL define symbol SYM to given value\n"
msgstr ""
-#: as.c:256
+#: as.c:255
#, c-format
msgid " emulate output (default %s)\n"
msgstr ""
-#: as.c:260
+#: as.c:259
msgid " -f skip whitespace and comment preprocessing\n"
msgstr ""
-#: as.c:262
+#: as.c:261
msgid " --gstabs generate stabs debugging information\n"
msgstr ""
-#: as.c:264
+#: as.c:263
msgid " --gdwarf2 generate DWARF2 debugging information\n"
msgstr ""
-#: as.c:266
+#: as.c:265
msgid " --help show this message and exit\n"
msgstr ""
-#: as.c:268
+#: as.c:267
msgid " --target-help show target specific options\n"
msgstr ""
-#: as.c:270
+#: as.c:269
msgid ""
" -I DIR add DIR to search list for .include directives\n"
msgstr ""
-#: as.c:272
+#: as.c:271
msgid " -J don't warn about signed overflow\n"
msgstr ""
-#: as.c:274
+#: as.c:273
msgid ""
" -K warn when differences altered for long "
"displacements\n"
msgstr ""
-#: as.c:276
+#: as.c:275
msgid " -L,--keep-locals keep local symbols (e.g. starting with `L')\n"
msgstr ""
-#: as.c:278
+#: as.c:277
msgid " -M,--mri assemble in MRI compatibility mode\n"
msgstr ""
-#: as.c:280
+#: as.c:279
msgid ""
" --MD FILE write dependency information in FILE (default "
"none)\n"
msgstr ""
-#: as.c:282
+#: as.c:281
msgid " -nocpp ignored\n"
msgstr ""
-#: as.c:284
+#: as.c:283
msgid ""
" -o OBJFILE name the object-file output OBJFILE (default "
"a.out)\n"
msgstr ""
-#: as.c:286
+#: as.c:285
msgid " -R fold data section into text section\n"
msgstr ""
-#: as.c:288
+#: as.c:287
msgid ""
" --statistics print various measured statistics from execution\n"
msgstr ""
-#: as.c:290
+#: as.c:289
msgid " --strip-local-absolute strip local absolute symbols\n"
msgstr ""
-#: as.c:292
+#: as.c:291
msgid ""
" --traditional-format Use same format as native assembler when possible\n"
msgstr ""
-#: as.c:294
+#: as.c:293
msgid " --version print assembler version number and exit\n"
msgstr ""
-#: as.c:296
+#: as.c:295
msgid " -W --no-warn suppress warnings\n"
msgstr ""
-#: as.c:298
+#: as.c:297
msgid " --warn don't suppress warnings\n"
msgstr ""
-#: as.c:300
+#: as.c:299
msgid " --fatal-warnings treat warnings as errors\n"
msgstr ""
-#: as.c:302
+#: as.c:301
msgid ""
" --itbl INSTTBL extend instruction set to include instructions\n"
" matching the specifications defined in file "
"INSTTBL\n"
msgstr ""
-#: as.c:305
+#: as.c:304
msgid " -w ignored\n"
msgstr ""
-#: as.c:307
+#: as.c:306
msgid " -X ignored\n"
msgstr ""
-#: as.c:309
+#: as.c:308
msgid " -Z generate object file even after errors\n"
msgstr ""
-#: as.c:311
+#: as.c:310
msgid ""
" --listing-lhs-width set the width in words of the output data column "
"of\n"
" the listing\n"
msgstr ""
-#: as.c:314
+#: as.c:313
msgid ""
" --listing-lhs-width2 set the width in words of the continuation lines\n"
" of the output data column; ignored if smaller "
@@ -240,106 +238,106 @@ msgid ""
" the width of the first line\n"
msgstr ""
-#: as.c:318
+#: as.c:317
msgid ""
" --listing-rhs-width set the max width in characters of the lines from\n"
" the source file\n"
msgstr ""
-#: as.c:321
+#: as.c:320
msgid ""
" --listing-cont-lines set the maximum number of continuation lines used\n"
" for the output data column of the listing\n"
msgstr ""
-#: as.c:328 gasp.c:3527
+#: as.c:327 gasp.c:3527
#, c-format
msgid "Report bugs to %s\n"
msgstr ""
#. This output is intended to follow the GNU standards document.
-#: as.c:528
+#: as.c:527
#, c-format
msgid "GNU assembler %s\n"
msgstr ""
-#: as.c:529
+#: as.c:528
msgid "Copyright 2001 Free Software Foundation, Inc.\n"
msgstr ""
-#: as.c:530 gasp.c:3621
+#: as.c:529 gasp.c:3621
msgid ""
"This program is free software; you may redistribute it under the terms of\n"
"the GNU General Public License. This program has absolutely no warranty.\n"
msgstr ""
-#: as.c:533
+#: as.c:532
#, c-format
msgid "This assembler was configured for a target of `%s'.\n"
msgstr ""
-#: as.c:540
+#: as.c:539
msgid "multiple emulation names specified"
msgstr ""
-#: as.c:542
+#: as.c:541
msgid "emulations not handled in this configuration"
msgstr ""
-#: as.c:547
+#: as.c:546
#, c-format
msgid "alias = %s\n"
msgstr ""
-#: as.c:548
+#: as.c:547
#, c-format
msgid "canonical = %s\n"
msgstr ""
-#: as.c:549
+#: as.c:548
#, c-format
msgid "cpu-type = %s\n"
msgstr ""
-#: as.c:551
+#: as.c:550
#, c-format
msgid "format = %s\n"
msgstr ""
-#: as.c:554
+#: as.c:553
#, c-format
msgid "bfd-target = %s\n"
msgstr ""
-#: as.c:567
+#: as.c:566
msgid "bad defsym; format is --defsym name=value"
msgstr ""
-#: as.c:591
+#: as.c:590
msgid "No file name following -t option\n"
msgstr ""
-#: as.c:607
+#: as.c:606
#, c-format
msgid "Failed to read instruction table %s\n"
msgstr ""
-#: as.c:724
+#: as.c:723
#, c-format
msgid "invalid listing option `%c'"
msgstr ""
-#: as.c:923
+#: as.c:922
#, c-format
msgid "%d warnings, treating warnings as errors"
msgstr ""
-#: as.c:954
+#: as.c:953
#, c-format
msgid "%s: total time in assembly: %ld.%06ld\n"
msgstr ""
-#: as.c:957
+#: as.c:956
#, c-format
msgid "%s: data size %ld\n"
msgstr ""
@@ -349,7 +347,7 @@ msgstr ""
#. * This should never happen.
#.
#: atof-generic.c:437 config/tc-a29k.c:544 config/tc-i860.c:340
-#: config/tc-i860.c:832 config/tc-m68k.c:3190 config/tc-m68k.c:3219
+#: config/tc-i860.c:832 config/tc-m68k.c:3180 config/tc-m68k.c:3209
#: config/tc-sparc.c:2544
msgid "failed sanity check."
msgstr ""
@@ -428,17 +426,17 @@ msgstr ""
msgid "Attempt to put an undefined symbol into set %s"
msgstr ""
-#: config/obj-aout.c:197 config/obj-coff.c:1247 config/obj-elf.c:1773
+#: config/obj-aout.c:197 config/obj-coff.c:1252 config/obj-elf.c:1773
#: ecoff.c:3648
#, c-format
msgid "Symbol `%s' can not be both weak and common"
msgstr ""
-#: config/obj-aout.c:255 config/obj-coff.c:1983
+#: config/obj-aout.c:255 config/obj-coff.c:1987
msgid "unresolved relocation"
msgstr ""
-#: config/obj-aout.c:257 config/obj-coff.c:1985
+#: config/obj-aout.c:257 config/obj-coff.c:1989
#, c-format
msgid "bad relocation: symbol `%s' not in symbol table"
msgstr ""
@@ -448,7 +446,7 @@ msgstr ""
msgid "%s: bad type for weak symbol"
msgstr ""
-#: config/obj-aout.c:458 config/obj-coff.c:2914 write.c:1933
+#: config/obj-aout.c:458 config/obj-coff.c:2917 write.c:1932
#, c-format
msgid "%s: global symbols not supported in common sections"
msgstr ""
@@ -473,170 +471,170 @@ msgid "Inserting \"%s\" into structure table failed: %s"
msgstr ""
#. Zero is used as an end marker in the file.
-#: config/obj-coff.c:452
+#: config/obj-coff.c:456
msgid "Line numbers must be positive integers\n"
msgstr ""
-#: config/obj-coff.c:485 config/obj-coff.c:2329
+#: config/obj-coff.c:490 config/obj-coff.c:2332
msgid ".ln pseudo-op inside .def/.endef: ignored."
msgstr ""
-#: config/obj-coff.c:528 ecoff.c:3284
+#: config/obj-coff.c:533 ecoff.c:3284
msgid ".loc outside of .text"
msgstr ""
-#: config/obj-coff.c:535
+#: config/obj-coff.c:540
msgid ".loc pseudo-op inside .def/.endef: ignored."
msgstr ""
-#: config/obj-coff.c:623 config/obj-coff.c:2386
+#: config/obj-coff.c:628 config/obj-coff.c:2389
msgid ".def pseudo-op used inside of .def/.endef: ignored."
msgstr ""
-#: config/obj-coff.c:669 config/obj-coff.c:2438
+#: config/obj-coff.c:674 config/obj-coff.c:2441
msgid ".endef pseudo-op used outside of .def/.endef: ignored."
msgstr ""
-#: config/obj-coff.c:707
+#: config/obj-coff.c:712
#, c-format
msgid "`%s' symbol without preceding function"
msgstr ""
-#: config/obj-coff.c:794 config/obj-coff.c:2513
+#: config/obj-coff.c:799 config/obj-coff.c:2516
#, c-format
msgid "unexpected storage class %d"
msgstr ""
-#: config/obj-coff.c:907 config/obj-coff.c:2620
+#: config/obj-coff.c:912 config/obj-coff.c:2623
msgid ".dim pseudo-op used outside of .def/.endef: ignored."
msgstr ""
-#: config/obj-coff.c:927 config/obj-coff.c:2640
+#: config/obj-coff.c:932 config/obj-coff.c:2643
msgid "badly formed .dim directive ignored"
msgstr ""
-#: config/obj-coff.c:978 config/obj-coff.c:2703
+#: config/obj-coff.c:983 config/obj-coff.c:2706
msgid ".size pseudo-op used outside of .def/.endef ignored."
msgstr ""
-#: config/obj-coff.c:994 config/obj-coff.c:2719
+#: config/obj-coff.c:999 config/obj-coff.c:2722
msgid ".scl pseudo-op used outside of .def/.endef ignored."
msgstr ""
-#: config/obj-coff.c:1012 config/obj-coff.c:2737
+#: config/obj-coff.c:1017 config/obj-coff.c:2740
msgid ".tag pseudo-op used outside of .def/.endef ignored."
msgstr ""
-#: config/obj-coff.c:1031 config/obj-coff.c:2755
+#: config/obj-coff.c:1036 config/obj-coff.c:2758
#, c-format
msgid "tag not found for .tag %s"
msgstr ""
-#: config/obj-coff.c:1046 config/obj-coff.c:2770
+#: config/obj-coff.c:1051 config/obj-coff.c:2773
msgid ".type pseudo-op used outside of .def/.endef ignored."
msgstr ""
-#: config/obj-coff.c:1068 config/obj-coff.c:2792
+#: config/obj-coff.c:1073 config/obj-coff.c:2795
msgid ".val pseudo-op used outside of .def/.endef ignored."
msgstr ""
-#: config/obj-coff.c:1208 config/obj-coff.c:2987
+#: config/obj-coff.c:1213 config/obj-coff.c:2990
msgid "mismatched .eb"
msgstr ""
-#: config/obj-coff.c:1226 config/obj-coff.c:3027
+#: config/obj-coff.c:1231 config/obj-coff.c:3030
msgid "C_EFCN symbol out of scope"
msgstr ""
#. STYP_INFO
#. STYP_LIB
#. STYP_OVER
-#: config/obj-coff.c:1448
+#: config/obj-coff.c:1453
#, c-format
msgid "unsupported section attribute '%c'"
msgstr ""
-#: config/obj-coff.c:1453 config/obj-coff.c:3728 config/tc-ppc.c:3925
+#: config/obj-coff.c:1458 config/obj-coff.c:3734 config/tc-ppc.c:3945
#, c-format
msgid "unknown section attribute '%c'"
msgstr ""
-#: config/obj-coff.c:1483 config/tc-ppc.c:3943 read.c:2520
+#: config/obj-coff.c:1488 config/tc-ppc.c:3963 read.c:2520
#, c-format
msgid "error setting flags for \"%s\": %s"
msgstr ""
-#: config/obj-coff.c:1494 config/obj-elf.c:727
+#: config/obj-coff.c:1499 config/obj-elf.c:727
#, c-format
msgid "Ignoring changed section attributes for %s"
msgstr ""
-#: config/obj-coff.c:1630
+#: config/obj-coff.c:1635
#, c-format
msgid "0x%lx: \"%s\" type = %ld, class = %d, segment = %d\n"
msgstr ""
-#: config/obj-coff.c:1810 config/obj-ieee.c:69
+#: config/obj-coff.c:1815 config/obj-ieee.c:69
msgid "Out of step\n"
msgstr ""
-#: config/obj-coff.c:2245
+#: config/obj-coff.c:2248
msgid "bfd_coff_swap_scnhdr_out failed"
msgstr ""
-#: config/obj-coff.c:2470
+#: config/obj-coff.c:2473
msgid "`.bf' symbol without preceding function\n"
msgstr ""
-#: config/obj-coff.c:3424 config/obj-ieee.c:507 output-file.c:52
+#: config/obj-coff.c:3427 config/obj-ieee.c:507 output-file.c:52
#: output-file.c:119
#, c-format
msgid "FATAL: Can't create %s"
msgstr ""
-#: config/obj-coff.c:3602
+#: config/obj-coff.c:3608
#, c-format
msgid "Can't close %s: %s"
msgstr ""
-#: config/obj-coff.c:3636
+#: config/obj-coff.c:3642
#, c-format
msgid "Too many new sections; can't add \"%s\""
msgstr ""
-#: config/obj-coff.c:4043 config/tc-m88k.c:1258 config/tc-sparc.c:3532
+#: config/obj-coff.c:4049 config/tc-m88k.c:1258 config/tc-sparc.c:3538
msgid "Expected comma after name"
msgstr ""
-#: config/obj-coff.c:4049 read.c:1956
+#: config/obj-coff.c:4055 read.c:1956
msgid "Missing size expression"
msgstr ""
-#: config/obj-coff.c:4055
+#: config/obj-coff.c:4061
#, c-format
msgid "lcomm length (%d.) <0! Ignored."
msgstr ""
-#: config/obj-coff.c:4083 read.c:2190
+#: config/obj-coff.c:4089 read.c:2190
#, c-format
msgid "Symbol %s already defined"
msgstr ""
-#: config/obj-coff.c:4178 config/tc-i960.c:3215
+#: config/obj-coff.c:4184 config/tc-i960.c:3215
#, c-format
msgid "No 'bal' entry point for leafproc %s"
msgstr ""
-#: config/obj-coff.c:4257 write.c:2639
+#: config/obj-coff.c:4263 write.c:2648
#, c-format
msgid "Negative of non-absolute symbol %s"
msgstr ""
-#: config/obj-coff.c:4278 write.c:2653
+#: config/obj-coff.c:4284 write.c:2662
msgid "callj to difference of 2 symbols"
msgstr ""
-#: config/obj-coff.c:4324
+#: config/obj-coff.c:4330
#, c-format
msgid "Can't emit reloc {- %s-seg symbol \"%s\"} @ file address %ld."
msgstr ""
@@ -644,16 +642,16 @@ msgstr ""
#. This is a COBR instruction. They have only a 13-bit
#. displacement and are only to be used for local branches:
#. flag as error, don't generate relocation.
-#: config/obj-coff.c:4413 config/tc-i960.c:3235 write.c:2797
+#: config/obj-coff.c:4419 config/tc-i960.c:3235 write.c:2806
msgid "can't use COBR format with external label"
msgstr ""
-#: config/obj-coff.c:4492
+#: config/obj-coff.c:4498
#, c-format
msgid "Value of %ld too large for field of %d bytes at 0x%lx"
msgstr ""
-#: config/obj-coff.c:4506 write.c:2887
+#: config/obj-coff.c:4512 write.c:2896
#, c-format
msgid "Signed .word overflow; switch may be too large; %ld at 0x%lx"
msgstr ""
@@ -666,35 +664,35 @@ msgstr ""
msgid "Can't set register masks"
msgstr ""
-#: config/obj-elf.c:308 config/tc-sparc.c:3675 config/tc-v850.c:259
+#: config/obj-elf.c:308 config/tc-sparc.c:3681 config/tc-v850.c:260
msgid "Expected comma after symbol-name"
msgstr ""
-#: config/obj-elf.c:315 config/tc-sparc.c:3685
+#: config/obj-elf.c:315 config/tc-sparc.c:3691
#, c-format
msgid ".COMMon length (%d.) <0! Ignored."
msgstr ""
-#: config/obj-elf.c:325 config/tc-alpha.c:4332 config/tc-sparc.c:3695
-#: config/tc-v850.c:282
+#: config/obj-elf.c:325 config/tc-alpha.c:4332 config/tc-sparc.c:3701
+#: config/tc-v850.c:283
msgid "Ignoring attempt to re-define symbol"
msgstr ""
-#: config/obj-elf.c:333 config/tc-sparc.c:3703 config/tc-v850.c:292
+#: config/obj-elf.c:333 config/tc-sparc.c:3709 config/tc-v850.c:293
#, c-format
msgid "Length of .comm \"%s\" is already %ld. Not changed to %d."
msgstr ""
-#: config/obj-elf.c:356 config/tc-v850.c:319
+#: config/obj-elf.c:356 config/tc-v850.c:320
msgid "Common alignment negative; 0 assumed"
msgstr ""
#: config/obj-elf.c:375 config/tc-m32r.c:1287 config/tc-ppc.c:1518
-#: config/tc-v850.c:382
+#: config/tc-v850.c:383
msgid "Common alignment not a power of 2"
msgstr ""
-#: config/obj-elf.c:438 config/tc-sparc.c:3827 config/tc-v850.c:564
+#: config/obj-elf.c:438 config/tc-sparc.c:3833 config/tc-v850.c:565
#, c-format
msgid "bad .common segment %s"
msgstr ""
@@ -982,13 +980,13 @@ msgstr ""
msgid "unhandled stab type %d"
msgstr ""
-#: config/tc-a29k.c:160 config/tc-sparc.c:3879
+#: config/tc-a29k.c:160 config/tc-sparc.c:3885
msgid "Unknown segment type"
msgstr ""
#. Probably a memory allocation problem? Give up now.
-#: config/tc-a29k.c:330 config/tc-hppa.c:1443 config/tc-mips.c:1031
-#: config/tc-mips.c:1073 config/tc-sparc.c:847
+#: config/tc-a29k.c:330 config/tc-hppa.c:1443 config/tc-mips.c:1039
+#: config/tc-mips.c:1081 config/tc-sparc.c:847
msgid "Broken assembler. No assembly attempted."
msgstr ""
@@ -996,8 +994,8 @@ msgstr ""
#: config/tc-d30v.c:552 config/tc-h8300.c:296 config/tc-h8500.c:284
#: config/tc-mcore.c:655 config/tc-mn10200.c:955 config/tc-mn10300.c:1337
#: config/tc-ppc.c:1974 config/tc-s390.c:1030 config/tc-sh.c:848
-#: config/tc-tic80.c:282 config/tc-v850.c:2076 config/tc-w65.c:242
-#: config/tc-z8k.c:336
+#: config/tc-tic80.c:282 config/tc-v850.c:2073 config/tc-w65.c:242
+#: config/tc-z8k.c:334
msgid "missing operand"
msgstr ""
@@ -1068,10 +1066,10 @@ msgstr ""
msgid "syntax error"
msgstr ""
-#: config/tc-alpha.c:1020 config/tc-arm.c:6640 config/tc-h8300.c:1373
+#: config/tc-alpha.c:1020 config/tc-arm.c:6651 config/tc-h8300.c:1373
#: config/tc-h8500.c:1187 config/tc-hppa.c:3996 config/tc-i860.c:931
-#: config/tc-m68hc11.c:484 config/tc-m68k.c:4194 config/tc-m88k.c:1106
-#: config/tc-ns32k.c:1664 config/tc-sparc.c:2831 config/tc-z8k.c:1334
+#: config/tc-m68hc11.c:486 config/tc-m68k.c:4199 config/tc-m88k.c:1106
+#: config/tc-ns32k.c:1664 config/tc-sparc.c:2831 config/tc-z8k.c:1312
msgid "Bad call to MD_ATOF()"
msgstr ""
@@ -1112,7 +1110,7 @@ msgstr ""
msgid "type %d reloc done?\n"
msgstr ""
-#: config/tc-alpha.c:1375 config/tc-alpha.c:1382 config/tc-mips.c:7373
+#: config/tc-alpha.c:1375 config/tc-alpha.c:1382 config/tc-mips.c:7399
msgid "Used $at without \".set noat\""
msgstr ""
@@ -1168,8 +1166,8 @@ msgstr ""
#: config/tc-alpha.c:2441 config/tc-d10v.c:622 config/tc-d30v.c:640
#: config/tc-mn10200.c:1010 config/tc-mn10300.c:1408 config/tc-ppc.c:1940
#: config/tc-ppc.c:2048 config/tc-ppc.c:2060 config/tc-s390.c:1040
-#: config/tc-s390.c:1093 config/tc-v850.c:1856 config/tc-v850.c:1879
-#: config/tc-v850.c:2099
+#: config/tc-s390.c:1093 config/tc-v850.c:1853 config/tc-v850.c:1876
+#: config/tc-v850.c:2096
msgid "too many fixups"
msgstr ""
@@ -1219,7 +1217,7 @@ msgstr ""
msgid "bignum invalid; zero assumed"
msgstr ""
-#: config/tc-alpha.c:3089 expr.c:86 read.c:3174 read.c:3507 read.c:4405
+#: config/tc-alpha.c:3089 expr.c:86 read.c:3174 read.c:3507 read.c:4406
msgid "floating point number invalid; zero assumed"
msgstr ""
@@ -1236,13 +1234,13 @@ msgstr ""
msgid "bad instruction format for lda !%s!%ld"
msgstr ""
-#: config/tc-alpha.c:4303 config/tc-ppc.c:1467 config/tc-ppc.c:3689
+#: config/tc-alpha.c:4303 config/tc-ppc.c:1467 config/tc-ppc.c:3709
#: read.c:1369
#, c-format
msgid ".COMMon length (%ld.) <0! Ignored."
msgstr ""
-#: config/tc-alpha.c:4341 config/tc-alpha.c:4350 config/tc-ppc.c:3726
+#: config/tc-alpha.c:4341 config/tc-alpha.c:4350 config/tc-ppc.c:3746
#: read.c:1393
#, c-format
msgid "Length of .comm \"%s\" is already %ld. Not changed to %ld."
@@ -1333,7 +1331,7 @@ msgstr ""
msgid "Bad .fmask directive"
msgstr ""
-#: config/tc-alpha.c:5237 config/tc-arm.c:1593 read.c:2150 read.c:2745
+#: config/tc-alpha.c:5237 config/tc-arm.c:1604 read.c:2150 read.c:2745
#: stabs.c:472
#, c-format
msgid "Expected comma after name \"%s\""
@@ -1374,651 +1372,651 @@ msgstr ""
msgid "Chose GP value of %lx\n"
msgstr ""
-#: config/tc-arc.c:1609 config/tc-arm.c:7552
+#: config/tc-arc.c:1615 config/tc-arm.c:7563
msgid "md_estimate_size_before_relax\n"
msgstr ""
-#: config/tc-arc.c:1621
+#: config/tc-arc.c:1627
msgid "md_convert_frag\n"
msgstr ""
-#: config/tc-arm.c:1289
+#: config/tc-arm.c:1300
msgid "Literal Pool Overflow"
msgstr ""
-#: config/tc-arm.c:1431
+#: config/tc-arm.c:1442
msgid "Invalid syntax for .req directive."
msgstr ""
-#: config/tc-arm.c:1506 config/tc-mips.c:9937 read.c:2035
+#: config/tc-arm.c:1517 config/tc-mips.c:9979 read.c:2035
#, c-format
msgid "Alignment too large: %d. assumed."
msgstr ""
-#: config/tc-arm.c:1509 read.c:2040
+#: config/tc-arm.c:1520 read.c:2040
msgid "Alignment negative. 0 assumed."
msgstr ""
-#: config/tc-arm.c:1643 config/tc-m32r.c:418 read.c:2803 read.c:4872
+#: config/tc-arm.c:1654 config/tc-m32r.c:418 read.c:2803 read.c:4884
#, c-format
msgid "symbol `%s' already defined"
msgstr ""
-#: config/tc-arm.c:1714
+#: config/tc-arm.c:1725
msgid "selected processor does not support THUMB opcodes"
msgstr ""
-#: config/tc-arm.c:1727
+#: config/tc-arm.c:1738
msgid "selected processor does not support ARM opcodes"
msgstr ""
-#: config/tc-arm.c:1739
+#: config/tc-arm.c:1750
#, c-format
msgid "invalid instruction size selected (%d)"
msgstr ""
-#: config/tc-arm.c:1774
+#: config/tc-arm.c:1785
#, c-format
msgid "invalid operand to .code directive (%d) (expecting 16 or 32)"
msgstr ""
-#: config/tc-arm.c:1785
+#: config/tc-arm.c:1796
msgid "Garbage following instruction"
msgstr ""
#. In the few cases where we might be able to accept something else
#. this error can be overridden.
-#: config/tc-arm.c:1835
+#: config/tc-arm.c:1846
#, c-format
msgid "Register expected, not '%.100s'"
msgstr ""
#. In the few cases where we might be able to accept
#. something else this error can be overridden.
-#: config/tc-arm.c:1907
+#: config/tc-arm.c:1918
msgid "flag for {c}psr instruction expected"
msgstr ""
-#: config/tc-arm.c:1937
+#: config/tc-arm.c:1948
msgid "Illegal co-processor number"
msgstr ""
-#: config/tc-arm.c:1944
+#: config/tc-arm.c:1955
msgid "Bad or missing co-processor number"
msgstr ""
-#: config/tc-arm.c:1968 config/tc-arm.c:3054 config/tc-arm.c:3246
+#: config/tc-arm.c:1979 config/tc-arm.c:3065 config/tc-arm.c:3257
msgid "bad or missing expression"
msgstr ""
-#: config/tc-arm.c:1974
+#: config/tc-arm.c:1985
msgid "immediate co-processor expression too large"
msgstr ""
#. In the few cases where we might be able to accept something else
#. this error can be overridden.
-#: config/tc-arm.c:1999
+#: config/tc-arm.c:2010
msgid "Co-processor register expected"
msgstr ""
#. In the few cases where we might be able to accept something else
#. this error can be overridden.
-#: config/tc-arm.c:2023
+#: config/tc-arm.c:2034
msgid "Floating point register expected"
msgstr ""
-#: config/tc-arm.c:2040
+#: config/tc-arm.c:2051
msgid "immediate expression expected"
msgstr ""
-#: config/tc-arm.c:2055
+#: config/tc-arm.c:2066
msgid "co-processor address must be word aligned"
msgstr ""
-#: config/tc-arm.c:2061
+#: config/tc-arm.c:2072
msgid "offset too large"
msgstr ""
-#: config/tc-arm.c:2109
+#: config/tc-arm.c:2120
msgid "pc may not be used in post-increment"
msgstr ""
-#: config/tc-arm.c:2125 config/tc-arm.c:2578 config/tc-arm.c:3438
-#: config/tc-arm.c:4372
+#: config/tc-arm.c:2136 config/tc-arm.c:2589 config/tc-arm.c:3449
+#: config/tc-arm.c:4383
msgid "pre-indexed expression expected"
msgstr ""
-#: config/tc-arm.c:2138 config/tc-arm.c:2591 config/tc-arm.c:3449
-#: config/tc-arm.c:4384 config/tc-arm.c:4730
+#: config/tc-arm.c:2149 config/tc-arm.c:2602 config/tc-arm.c:3460
+#: config/tc-arm.c:4395 config/tc-arm.c:4741
msgid "missing ]"
msgstr ""
-#: config/tc-arm.c:2148
+#: config/tc-arm.c:2159
msgid "pc may not be used with write-back"
msgstr ""
-#: config/tc-arm.c:2203
+#: config/tc-arm.c:2214
msgid "comma expected after register name"
msgstr ""
-#: config/tc-arm.c:2222
+#: config/tc-arm.c:2233
msgid "{C|S}PSR expected"
msgstr ""
-#: config/tc-arm.c:2250
+#: config/tc-arm.c:2261
msgid "comma missing after psr flags"
msgstr ""
-#: config/tc-arm.c:2267 config/tc-arm.c:2277
+#: config/tc-arm.c:2278 config/tc-arm.c:2288
msgid "only a register or immediate value can follow a psr flag"
msgstr ""
-#: config/tc-arm.c:2284
+#: config/tc-arm.c:2295
msgid "immediate value cannot be used to set this field"
msgstr ""
-#: config/tc-arm.c:2301 config/tc-arm.c:3673 config/tc-arm.c:3939
-#: config/tc-arm.c:3959
+#: config/tc-arm.c:2312 config/tc-arm.c:3684 config/tc-arm.c:3950
+#: config/tc-arm.c:3970
msgid "Invalid constant"
msgstr ""
-#: config/tc-arm.c:2351
+#: config/tc-arm.c:2362
msgid "rdhi, rdlo and rm must all be different"
msgstr ""
-#: config/tc-arm.c:2407
+#: config/tc-arm.c:2418
msgid "rd and rm should be different in mul"
msgstr ""
-#: config/tc-arm.c:2463
+#: config/tc-arm.c:2474
msgid "rd and rm should be different in mla"
msgstr ""
-#: config/tc-arm.c:2512
+#: config/tc-arm.c:2523
#, c-format
msgid "acc0 expected, not '%.100s'"
msgstr ""
-#: config/tc-arm.c:2695
+#: config/tc-arm.c:2706
msgid "rdhi and rdlo must be different"
msgstr ""
-#: config/tc-arm.c:2815
+#: config/tc-arm.c:2826
msgid "Warning: Instruction unpredictable when using r15"
msgstr ""
-#: config/tc-arm.c:3063 config/tc-arm.c:3255 config/tc-arm.c:5517
-#: config/tc-arm.c:5550 config/tc-arm.c:5560
+#: config/tc-arm.c:3074 config/tc-arm.c:3266 config/tc-arm.c:5528
+#: config/tc-arm.c:5561 config/tc-arm.c:5571
msgid "immediate value out of range"
msgstr ""
-#: config/tc-arm.c:3403
+#: config/tc-arm.c:3414
msgid "'[' expected after PLD mnemonic"
msgstr ""
-#: config/tc-arm.c:3428 config/tc-arm.c:3458
+#: config/tc-arm.c:3439 config/tc-arm.c:3469
msgid "writeback used in preload instruction"
msgstr ""
#. Deny all knowledge.
-#: config/tc-arm.c:3506
+#: config/tc-arm.c:3517
#, c-format
msgid "bad instruction '%.100s'"
msgstr ""
-#: config/tc-arm.c:3530
+#: config/tc-arm.c:3541
msgid "Destination register must be even"
msgstr ""
-#: config/tc-arm.c:3536
+#: config/tc-arm.c:3547
msgid "r12 or r14 not allowed here"
msgstr ""
-#: config/tc-arm.c:3544
+#: config/tc-arm.c:3555
msgid "pre/post-indexing used when modified address register is destination"
msgstr ""
-#: config/tc-arm.c:3657
+#: config/tc-arm.c:3668
msgid "bad_segment"
msgstr ""
-#: config/tc-arm.c:3703 config/tc-arm.c:3714
+#: config/tc-arm.c:3714 config/tc-arm.c:3725
msgid "Shift expression expected"
msgstr ""
-#: config/tc-arm.c:3738
+#: config/tc-arm.c:3749
msgid "shift requires register or #expression"
msgstr ""
-#: config/tc-arm.c:3739
+#: config/tc-arm.c:3750
msgid "shift requires #expression"
msgstr ""
-#: config/tc-arm.c:3769
+#: config/tc-arm.c:3780
msgid "Shift of 0 ignored."
msgstr ""
-#: config/tc-arm.c:3775
+#: config/tc-arm.c:3786
msgid "Invalid immediate shift"
msgstr ""
-#: config/tc-arm.c:3930 config/tc-arm.c:4414
+#: config/tc-arm.c:3941 config/tc-arm.c:4425
msgid "Constant expression expected"
msgstr ""
-#: config/tc-arm.c:3972
+#: config/tc-arm.c:3983
msgid "Register or shift expression expected"
msgstr ""
-#: config/tc-arm.c:4025
+#: config/tc-arm.c:4036
msgid "Invalid floating point immediate expression"
msgstr ""
-#: config/tc-arm.c:4029
+#: config/tc-arm.c:4040
msgid "Floating point register or immediate expression expected"
msgstr ""
-#: config/tc-arm.c:4198
+#: config/tc-arm.c:4209
msgid "address offset too large"
msgstr ""
-#: config/tc-arm.c:4275
+#: config/tc-arm.c:4286
msgid "Processor does not support halfwords or signed bytes"
msgstr ""
-#: config/tc-arm.c:4296
+#: config/tc-arm.c:4307
msgid "Address expected"
msgstr ""
-#: config/tc-arm.c:4328 config/tc-arm.c:4359
+#: config/tc-arm.c:4339 config/tc-arm.c:4370
#, c-format
msgid "Rn and Rd must be different in %s"
msgstr ""
-#: config/tc-arm.c:4332 config/tc-arm.c:4348 config/tc-arm.c:4393
+#: config/tc-arm.c:4343 config/tc-arm.c:4359 config/tc-arm.c:4404
#, c-format
msgid "%s register same as write-back base"
msgstr ""
-#: config/tc-arm.c:4334 config/tc-arm.c:4350 config/tc-arm.c:4395
+#: config/tc-arm.c:4345 config/tc-arm.c:4361 config/tc-arm.c:4406
msgid "destination"
msgstr ""
-#: config/tc-arm.c:4334 config/tc-arm.c:4350 config/tc-arm.c:4395
+#: config/tc-arm.c:4345 config/tc-arm.c:4361 config/tc-arm.c:4406
msgid "source"
msgstr ""
-#: config/tc-arm.c:4434
+#: config/tc-arm.c:4445
msgid "literal pool insertion failed"
msgstr ""
-#: config/tc-arm.c:4473
+#: config/tc-arm.c:4484
msgid "Pre-increment instruction with translate"
msgstr ""
-#: config/tc-arm.c:4514
+#: config/tc-arm.c:4525
msgid "Bad range in register list"
msgstr ""
-#: config/tc-arm.c:4522 config/tc-arm.c:4531 config/tc-arm.c:4573
+#: config/tc-arm.c:4533 config/tc-arm.c:4542 config/tc-arm.c:4584
#, c-format
msgid "Warning: Duplicated register (r%d) in register list"
msgstr ""
-#: config/tc-arm.c:4534
+#: config/tc-arm.c:4545
msgid "Warning: Register range not in ascending order"
msgstr ""
-#: config/tc-arm.c:4546
+#: config/tc-arm.c:4557
msgid "Missing `}'"
msgstr ""
-#: config/tc-arm.c:4562
+#: config/tc-arm.c:4573
msgid "invalid register mask"
msgstr ""
-#: config/tc-arm.c:4583 config/tc-avr.c:852 config/tc-cris.c:3009
-#: config/tc-d10v.c:1561 config/tc-d30v.c:1865 config/tc-mips.c:3231
-#: config/tc-mips.c:4163 config/tc-mips.c:4964 config/tc-mips.c:5510
-#: config/tc-ppc.c:4855 config/tc-v850.c:2385
+#: config/tc-arm.c:4594 config/tc-avr.c:852 config/tc-cris.c:3009
+#: config/tc-d10v.c:1561 config/tc-d30v.c:1865 config/tc-mips.c:3247
+#: config/tc-mips.c:4183 config/tc-mips.c:4984 config/tc-mips.c:5530
+#: config/tc-ppc.c:4873 config/tc-v850.c:2377
msgid "expression too complex"
msgstr ""
-#: config/tc-arm.c:4622
+#: config/tc-arm.c:4633
msgid "r15 not allowed as base register"
msgstr ""
-#: config/tc-arm.c:4690 config/tc-arm.c:4704
+#: config/tc-arm.c:4701 config/tc-arm.c:4715
msgid "r15 not allowed in swap"
msgstr ""
-#: config/tc-arm.c:4802
+#: config/tc-arm.c:4813
msgid "Use of r15 in bx in ARM mode is not really useful"
msgstr ""
-#: config/tc-arm.c:5058 config/tc-v850.c:1959 config/tc-v850.c:1980
+#: config/tc-arm.c:5069 config/tc-v850.c:1956 config/tc-v850.c:1977
msgid "constant expression expected"
msgstr ""
-#: config/tc-arm.c:5064
+#: config/tc-arm.c:5075
msgid "Constant value required for number of registers"
msgstr ""
-#: config/tc-arm.c:5072
+#: config/tc-arm.c:5083
msgid "number of registers must be in the range [1:4]"
msgstr ""
-#: config/tc-arm.c:5133
+#: config/tc-arm.c:5144
msgid "R15 not allowed as base register with write-back"
msgstr ""
-#: config/tc-arm.c:5381
+#: config/tc-arm.c:5392
msgid "lo register required"
msgstr ""
-#: config/tc-arm.c:5389
+#: config/tc-arm.c:5400
msgid "hi register required"
msgstr ""
-#: config/tc-arm.c:5459
+#: config/tc-arm.c:5470
msgid "dest and source1 must be the same register"
msgstr ""
-#: config/tc-arm.c:5466
+#: config/tc-arm.c:5477
msgid "subtract valid only on lo regs"
msgstr ""
-#: config/tc-arm.c:5490
+#: config/tc-arm.c:5501
msgid "invalid Hi register with immediate"
msgstr ""
-#: config/tc-arm.c:5528
+#: config/tc-arm.c:5539
msgid "invalid immediate value for stack adjust"
msgstr ""
-#: config/tc-arm.c:5539
+#: config/tc-arm.c:5550
msgid "invalid immediate for address calculation"
msgstr ""
-#: config/tc-arm.c:5626
+#: config/tc-arm.c:5637
msgid "source1 and dest must be same register"
msgstr ""
-#: config/tc-arm.c:5660
+#: config/tc-arm.c:5671
msgid "Invalid immediate for shift"
msgstr ""
-#: config/tc-arm.c:5739
+#: config/tc-arm.c:5750
msgid "only lo regs allowed with immediate"
msgstr ""
-#: config/tc-arm.c:5758
+#: config/tc-arm.c:5769
msgid "invalid immediate"
msgstr ""
-#: config/tc-arm.c:5812
+#: config/tc-arm.c:5823
msgid "expected ']'"
msgstr ""
-#: config/tc-arm.c:5879
+#: config/tc-arm.c:5890
msgid "byte or halfword not valid for base register"
msgstr ""
-#: config/tc-arm.c:5884
+#: config/tc-arm.c:5895
msgid "R15 based store not allowed"
msgstr ""
-#: config/tc-arm.c:5889
+#: config/tc-arm.c:5900
msgid "Invalid base register for register offset"
msgstr ""
-#: config/tc-arm.c:5907
+#: config/tc-arm.c:5918
msgid "invalid offset"
msgstr ""
-#: config/tc-arm.c:5918
+#: config/tc-arm.c:5929
msgid "invalid base register in load/store"
msgstr ""
-#: config/tc-arm.c:5942
+#: config/tc-arm.c:5953
msgid "Invalid offset"
msgstr ""
-#: config/tc-arm.c:6017
+#: config/tc-arm.c:6028
msgid "dest and source1 one must be the same register"
msgstr ""
-#: config/tc-arm.c:6025
+#: config/tc-arm.c:6036
msgid "Rs and Rd must be different in MUL"
msgstr ""
-#: config/tc-arm.c:6169
+#: config/tc-arm.c:6180
msgid ""
"Inserted missing '!': load/store multiple always writes back base register"
msgstr ""
-#: config/tc-arm.c:6185 config/tc-arm.c:6285
+#: config/tc-arm.c:6196 config/tc-arm.c:6296
msgid "Expression too complex"
msgstr ""
-#: config/tc-arm.c:6191
+#: config/tc-arm.c:6202
msgid "only lo-regs valid in load/store multiple"
msgstr ""
-#: config/tc-arm.c:6237
+#: config/tc-arm.c:6248
msgid "Syntax: ldrs[b] Rd, [Rb, Ro]"
msgstr ""
-#: config/tc-arm.c:6301
+#: config/tc-arm.c:6312
msgid "invalid register list to push/pop instruction"
msgstr ""
-#: config/tc-arm.c:6443 config/tc-cris.c:684
+#: config/tc-arm.c:6454 config/tc-cris.c:684
msgid "Virtual memory exhausted"
msgstr ""
-#: config/tc-arm.c:6846
+#: config/tc-arm.c:6857
#, c-format
msgid "invalid constant (%lx) after fixup"
msgstr ""
-#: config/tc-arm.c:6882
+#: config/tc-arm.c:6893
#, c-format
msgid "Unable to compute ADRL instructions for PC offset of 0x%lx"
msgstr ""
-#: config/tc-arm.c:6912
+#: config/tc-arm.c:6923
#, c-format
msgid "bad immediate value for offset (%ld)"
msgstr ""
-#: config/tc-arm.c:6934 config/tc-arm.c:6956
+#: config/tc-arm.c:6945 config/tc-arm.c:6967
msgid "invalid literal constant: pool needs to be closer"
msgstr ""
-#: config/tc-arm.c:6936
+#: config/tc-arm.c:6947
#, c-format
msgid "bad immediate value for half-word offset (%ld)"
msgstr ""
-#: config/tc-arm.c:6973
+#: config/tc-arm.c:6984
msgid "shift expression is too large"
msgstr ""
-#: config/tc-arm.c:6992 config/tc-arm.c:7001
+#: config/tc-arm.c:7003 config/tc-arm.c:7012
msgid "Invalid swi expression"
msgstr ""
-#: config/tc-arm.c:7011
+#: config/tc-arm.c:7022
msgid "Invalid expression in load/store multiple"
msgstr ""
-#: config/tc-arm.c:7064
+#: config/tc-arm.c:7075
msgid "gas can't handle same-section branch dest >= 0x04000000"
msgstr ""
-#: config/tc-arm.c:7073
+#: config/tc-arm.c:7084
msgid "out of range branch"
msgstr ""
-#: config/tc-arm.c:7106 config/tc-arm.c:7122 config/tc-mips.c:9764
+#: config/tc-arm.c:7117 config/tc-arm.c:7133 config/tc-mips.c:9806
msgid "Branch out of range"
msgstr ""
-#: config/tc-arm.c:7145
+#: config/tc-arm.c:7156
msgid "Branch with link out of range"
msgstr ""
-#: config/tc-arm.c:7221
+#: config/tc-arm.c:7232
msgid "Illegal value for co-processor offset"
msgstr ""
-#: config/tc-arm.c:7245
+#: config/tc-arm.c:7256
#, c-format
msgid "Invalid offset, target not word aligned (0x%08X)"
msgstr ""
-#: config/tc-arm.c:7251 config/tc-arm.c:7260 config/tc-arm.c:7267
-#: config/tc-arm.c:7274 config/tc-arm.c:7281
+#: config/tc-arm.c:7262 config/tc-arm.c:7271 config/tc-arm.c:7278
+#: config/tc-arm.c:7285 config/tc-arm.c:7292
#, c-format
msgid "Invalid offset, value too big (0x%08lX)"
msgstr ""
-#: config/tc-arm.c:7320
+#: config/tc-arm.c:7331
msgid "Invalid immediate for stack address calculation"
msgstr ""
-#: config/tc-arm.c:7329
+#: config/tc-arm.c:7340
#, c-format
msgid "Invalid immediate for address calculation (value = 0x%08lX)"
msgstr ""
-#: config/tc-arm.c:7339
+#: config/tc-arm.c:7350
msgid "Invalid 8bit immediate"
msgstr ""
-#: config/tc-arm.c:7347
+#: config/tc-arm.c:7358
msgid "Invalid 3bit immediate"
msgstr ""
-#: config/tc-arm.c:7363
+#: config/tc-arm.c:7374
#, c-format
msgid "Invalid immediate: %ld is too large"
msgstr ""
-#: config/tc-arm.c:7378
+#: config/tc-arm.c:7389
#, c-format
msgid "Illegal Thumb shift value: %ld"
msgstr ""
-#: config/tc-arm.c:7392 config/tc-mn10300.c:1929
+#: config/tc-arm.c:7403 config/tc-mn10300.c:1972
#, c-format
msgid "Bad relocation fixup type (%d)"
msgstr ""
-#: config/tc-arm.c:7465
+#: config/tc-arm.c:7476
msgid "Literal referenced across section boundary (Implicit dump?)"
msgstr ""
-#: config/tc-arm.c:7478
+#: config/tc-arm.c:7489
#, c-format
msgid "Internal_relocation (type %d) not fixed up (IMMEDIATE)"
msgstr ""
-#: config/tc-arm.c:7484
+#: config/tc-arm.c:7495
msgid "ADRL used for a symbol not defined in the same file"
msgstr ""
-#: config/tc-arm.c:7489
+#: config/tc-arm.c:7500
#, c-format
msgid "Internal_relocation (type %d) not fixed up (OFFSET_IMM)"
msgstr ""
-#: config/tc-arm.c:7510 config/tc-cris.c:2944 config/tc-mcore.c:2109
-#: config/tc-ns32k.c:2375
+#: config/tc-arm.c:7521 config/tc-cris.c:2944 config/tc-mcore.c:2104
+#: config/tc-ns32k.c:2363
msgid "<unknown>"
msgstr ""
-#: config/tc-arm.c:7513
+#: config/tc-arm.c:7524
#, c-format
msgid "Cannot represent %s relocation in this object file format"
msgstr ""
-#: config/tc-arm.c:7534 config/tc-mips.c:11282 config/tc-sh.c:3196
+#: config/tc-arm.c:7545 config/tc-mips.c:11315 config/tc-sh.c:3198
#, c-format
msgid "Can not represent %s relocation in this object file format"
msgstr ""
-#: config/tc-arm.c:7631
+#: config/tc-arm.c:7642
#, c-format
msgid "No operator -- statement `%s'\n"
msgstr ""
-#: config/tc-arm.c:7649
+#: config/tc-arm.c:7660
msgid "selected processor does not support this opcode"
msgstr ""
-#: config/tc-arm.c:7695
+#: config/tc-arm.c:7706
#, c-format
msgid "Opcode `%s' must have suffix from list: <%s>"
msgstr ""
-#: config/tc-arm.c:7726
+#: config/tc-arm.c:7737
msgid "Warning: Use of the 'nv' conditional is deprecated\n"
msgstr ""
-#: config/tc-arm.c:7743
+#: config/tc-arm.c:7754
#, c-format
msgid "Opcode `%s' is unconditional\n"
msgstr ""
-#: config/tc-arm.c:7767
+#: config/tc-arm.c:7778
#, c-format
msgid "Opcode `%s' must have suffix from <%s>\n"
msgstr ""
-#: config/tc-arm.c:7858
+#: config/tc-arm.c:7869
#, c-format
msgid "register '%s' does not exist\n"
msgstr ""
-#: config/tc-arm.c:7863
+#: config/tc-arm.c:7874
#, c-format
msgid "ignoring redefinition of register alias '%s'"
msgstr ""
-#: config/tc-arm.c:7869
+#: config/tc-arm.c:7880
#, c-format
msgid ""
"ignoring redefinition of register alias '%s' to non-existant register '%s'"
msgstr ""
-#: config/tc-arm.c:7873
+#: config/tc-arm.c:7884
msgid "ignoring incomplete .req pseuso op"
msgstr ""
-#: config/tc-arm.c:7880
+#: config/tc-arm.c:7891
#, c-format
msgid "bad instruction `%s'"
msgstr ""
-#: config/tc-arm.c:8055
+#: config/tc-arm.c:8066
#, c-format
msgid "Unrecognised APCS switch -m%s"
msgstr ""
-#: config/tc-arm.c:8212 config/tc-arm.c:8225 config/tc-arm.c:8238
-#: config/tc-arm.c:8251 config/tc-arm.c:8257
+#: config/tc-arm.c:8223 config/tc-arm.c:8236 config/tc-arm.c:8249
+#: config/tc-arm.c:8262 config/tc-arm.c:8268
#, c-format
msgid "Invalid architecture variant -m%s"
msgstr ""
-#: config/tc-arm.c:8264
+#: config/tc-arm.c:8275
#, c-format
msgid "Invalid processor variant -m%s"
msgstr ""
-#: config/tc-arm.c:8287
+#: config/tc-arm.c:8298
msgid ""
" ARM Specific Assembler Options:\n"
" -m[arm][<processor name>] select processor variant\n"
@@ -2034,7 +2032,7 @@ msgid ""
" -k generate PIC code.\n"
msgstr ""
-#: config/tc-arm.c:8299
+#: config/tc-arm.c:8310
msgid ""
" -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to "
"use\n"
@@ -2043,23 +2041,23 @@ msgid ""
" -mapcs-reentrant the code is position independent/reentrant\n"
msgstr ""
-#: config/tc-arm.c:8306
+#: config/tc-arm.c:8317
msgid " -moabi support the old ELF ABI\n"
msgstr ""
-#: config/tc-arm.c:8310
+#: config/tc-arm.c:8321
msgid ""
" -EB assemble code for a big endian cpu\n"
" -EL assemble code for a little endian cpu\n"
msgstr ""
-#: config/tc-arm.c:8494
+#: config/tc-arm.c:8505
#, c-format
msgid "%s: unexpected function type: %d"
msgstr ""
-#: config/tc-arm.c:8857
-msgid "alignments in code section > 32 not supported."
+#: config/tc-arm.c:8871
+msgid "alignments greater than 32 bytes not supported in .text sections."
msgstr ""
#: config/tc-avr.c:185
@@ -2099,8 +2097,8 @@ msgid "redefinition of mcu type `%s' to `%s'"
msgstr ""
#: config/tc-avr.c:372 config/tc-d10v.c:314 config/tc-d30v.c:366
-#: config/tc-mips.c:8806 config/tc-mn10200.c:376 config/tc-pj.c:356
-#: config/tc-ppc.c:4519 config/tc-sh.c:2068 config/tc-v850.c:1291
+#: config/tc-mips.c:8836 config/tc-mn10200.c:376 config/tc-pj.c:356
+#: config/tc-ppc.c:4538 config/tc-sh.c:2070 config/tc-v850.c:1292
msgid "bad call to md_atof"
msgstr ""
@@ -2194,15 +2192,15 @@ msgid "only constant expression allowed"
msgstr ""
#: config/tc-avr.c:1060 config/tc-d10v.c:1496 config/tc-d30v.c:1807
-#: config/tc-mn10200.c:1255 config/tc-mn10300.c:1799 config/tc-ppc.c:5162
-#: config/tc-v850.c:2301
+#: config/tc-mn10200.c:1255 config/tc-mn10300.c:1800 config/tc-ppc.c:5180
+#: config/tc-v850.c:2296
#, c-format
msgid "reloc %d not supported by object file format"
msgstr ""
#: config/tc-avr.c:1084 config/tc-d10v.c:1103 config/tc-d10v.c:1117
#: config/tc-h8300.c:1239 config/tc-h8500.c:1088 config/tc-mcore.c:988
-#: config/tc-pj.c:265 config/tc-sh.c:1650 config/tc-z8k.c:1205
+#: config/tc-pj.c:265 config/tc-sh.c:1650 config/tc-z8k.c:1183
msgid "can't find opcode "
msgstr ""
@@ -2447,7 +2445,7 @@ msgstr ""
#: config/tc-d10v.c:531 config/tc-d30v.c:550 config/tc-mn10200.c:952
#: config/tc-mn10300.c:1334 config/tc-ppc.c:1972 config/tc-s390.c:1028
-#: config/tc-tic80.c:278 config/tc-v850.c:2073
+#: config/tc-tic80.c:278 config/tc-v850.c:2070
msgid "illegal operand"
msgstr ""
@@ -2516,7 +2514,7 @@ msgstr ""
msgid "bad opcode or operands"
msgstr ""
-#: config/tc-d10v.c:1354 config/tc-m68k.c:4301
+#: config/tc-d10v.c:1354 config/tc-m68k.c:4303
msgid "value out of range"
msgstr ""
@@ -2679,16 +2677,17 @@ msgstr ""
msgid " FR30 specific command line options:\n"
msgstr ""
-#: config/tc-fr30.c:143
+#: config/tc-fr30.c:143 config/tc-openrisc.c:151
#, c-format
msgid "Instruction %s not allowed in a delay slot."
msgstr ""
-#: config/tc-fr30.c:381 config/tc-m32r.c:1557
+#: config/tc-fr30.c:383 config/tc-m32r.c:1558
msgid "Addend to unresolved symbol not on word boundary."
msgstr ""
-#: config/tc-fr30.c:539 config/tc-i960.c:773 config/tc-m32r.c:1866
+#: config/tc-fr30.c:541 config/tc-i960.c:773 config/tc-m32r.c:1867
+#: config/tc-openrisc.c:469
msgid "Bad call to md_atof()"
msgstr ""
@@ -2764,8 +2763,8 @@ msgstr ""
msgid "invalid operands"
msgstr ""
-#: config/tc-h8300.c:1250 config/tc-h8500.c:1094 config/tc-mips.c:8001
-#: config/tc-sh.c:1887 config/tc-w65.c:734 config/tc-z8k.c:1215
+#: config/tc-h8300.c:1250 config/tc-h8500.c:1094 config/tc-mips.c:8030
+#: config/tc-sh.c:1887 config/tc-w65.c:734 config/tc-z8k.c:1193
msgid "unknown opcode"
msgstr ""
@@ -2773,25 +2772,25 @@ msgstr ""
msgid "mismatch between opcode size and operand size"
msgstr ""
-#: config/tc-h8300.c:1307 config/tc-h8500.c:1121 config/tc-sh.c:2023
-#: config/tc-w65.c:764 config/tc-z8k.c:1268
+#: config/tc-h8300.c:1307 config/tc-h8500.c:1121 config/tc-sh.c:2025
+#: config/tc-w65.c:764 config/tc-z8k.c:1246
msgid "call to tc_crawl_symbol_chain \n"
msgstr ""
-#: config/tc-h8300.c:1321 config/tc-h8500.c:1135 config/tc-sh.c:2030
-#: config/tc-w65.c:778 config/tc-z8k.c:1282
+#: config/tc-h8300.c:1321 config/tc-h8500.c:1135 config/tc-sh.c:2032
+#: config/tc-w65.c:778 config/tc-z8k.c:1260
msgid "call to tc_headers_hook \n"
msgstr ""
-#: config/tc-h8300.c:1412 config/tc-h8500.c:1225 config/tc-z8k.c:1396
+#: config/tc-h8300.c:1412 config/tc-h8500.c:1225 config/tc-z8k.c:1374
msgid "call to tc_aout_fix_to_chars \n"
msgstr ""
-#: config/tc-h8300.c:1422 config/tc-z8k.c:1406
+#: config/tc-h8300.c:1422 config/tc-z8k.c:1384
msgid "call to md_convert_frag \n"
msgstr ""
-#: config/tc-h8300.c:1467 config/tc-z8k.c:1487
+#: config/tc-h8300.c:1467 config/tc-z8k.c:1465
msgid "call tomd_estimate_size_before_relax \n"
msgstr ""
@@ -2857,7 +2856,7 @@ msgstr ""
#: config/tc-hppa.c:1403 config/tc-hppa.c:6895 config/tc-hppa.c:6901
#: config/tc-hppa.c:6907 config/tc-hppa.c:6913 config/tc-mn10300.c:926
-#: config/tc-mn10300.c:2103
+#: config/tc-mn10300.c:2162
msgid "could not set architecture and machine"
msgstr ""
@@ -3105,7 +3104,7 @@ msgstr ""
msgid ".REG expression must be a register"
msgstr ""
-#: config/tc-hppa.c:6498 read.c:4736
+#: config/tc-hppa.c:6498 read.c:4748
msgid "bad or irreducible absolute expression; zero assumed"
msgstr ""
@@ -3289,11 +3288,11 @@ msgstr ""
msgid "no such architecture modifier: `%s'"
msgstr ""
-#: config/tc-i386.c:823 config/tc-i386.c:4590
+#: config/tc-i386.c:823 config/tc-i386.c:4627
msgid "Unknown architecture"
msgstr ""
-#: config/tc-i386.c:858 config/tc-i386.c:881 config/tc-m68k.c:3816
+#: config/tc-i386.c:858 config/tc-i386.c:881 config/tc-m68k.c:3821
#, c-format
msgid "Internal Error: Can't hash %s: %s"
msgstr ""
@@ -3302,7 +3301,7 @@ msgstr ""
msgid "There are no unsigned pc-relative relocations"
msgstr ""
-#: config/tc-i386.c:1141 config/tc-i386.c:4746
+#: config/tc-i386.c:1141 config/tc-i386.c:4783
#, c-format
msgid "can not do %d byte pc-relative relocation"
msgstr ""
@@ -3312,295 +3311,300 @@ msgstr ""
msgid "can not do %s %d byte relocation"
msgstr ""
-#: config/tc-i386.c:1269 config/tc-i386.c:1362
+#: config/tc-i386.c:1265 config/tc-i386.c:1359
#, c-format
msgid "no such instruction: `%s'"
msgstr ""
-#: config/tc-i386.c:1278
+#: config/tc-i386.c:1275 config/tc-i386.c:1391
#, c-format
msgid "invalid character %s in mnemonic"
msgstr ""
-#: config/tc-i386.c:1285
+#: config/tc-i386.c:1282
msgid "expecting prefix; got nothing"
msgstr ""
-#: config/tc-i386.c:1287
+#: config/tc-i386.c:1284
msgid "expecting mnemonic; got nothing"
msgstr ""
-#: config/tc-i386.c:1305
+#: config/tc-i386.c:1302
#, c-format
msgid "redundant %s prefix"
msgstr ""
-#: config/tc-i386.c:1373
+#: config/tc-i386.c:1402
#, c-format
msgid "`%s' is not supported on `%s'"
msgstr ""
-#: config/tc-i386.c:1378
+#: config/tc-i386.c:1407
msgid "use .code16 to ensure correct addressing mode"
msgstr ""
-#: config/tc-i386.c:1386
+#: config/tc-i386.c:1415
#, c-format
msgid "expecting string instruction after `%s'"
msgstr ""
-#: config/tc-i386.c:1407
+#: config/tc-i386.c:1436
#, c-format
msgid "invalid character %s before operand %d"
msgstr ""
-#: config/tc-i386.c:1421
+#: config/tc-i386.c:1450
#, c-format
msgid "unbalanced parenthesis in operand %d."
msgstr ""
-#: config/tc-i386.c:1424
+#: config/tc-i386.c:1453
#, c-format
msgid "unbalanced brackets in operand %d."
msgstr ""
-#: config/tc-i386.c:1433
+#: config/tc-i386.c:1462
#, c-format
msgid "invalid character %s in operand %d"
msgstr ""
-#: config/tc-i386.c:1460
+#: config/tc-i386.c:1489
#, c-format
msgid "spurious operands; (%d operands/instruction max)"
msgstr ""
-#: config/tc-i386.c:1483
+#: config/tc-i386.c:1512
msgid "expecting operand after ','; got nothing"
msgstr ""
-#: config/tc-i386.c:1488
+#: config/tc-i386.c:1517
msgid "expecting operand before ','; got nothing"
msgstr ""
#. We found no match.
-#: config/tc-i386.c:1832
+#: config/tc-i386.c:1861
#, c-format
msgid "suffix or operands invalid for `%s'"
msgstr ""
-#: config/tc-i386.c:1843
+#: config/tc-i386.c:1872
#, c-format
msgid "indirect %s without `*'"
msgstr ""
#. Warn them that a data or address size prefix doesn't
#. affect assembly of the next line of code.
-#: config/tc-i386.c:1851
+#: config/tc-i386.c:1880
#, c-format
msgid "stand-alone `%s' prefix"
msgstr ""
-#: config/tc-i386.c:1887 config/tc-i386.c:1902
+#: config/tc-i386.c:1916 config/tc-i386.c:1931
msgid "`%s' operand %d must use `%%es' segment"
msgstr ""
-#: config/tc-i386.c:1917
+#: config/tc-i386.c:1946
msgid "Extended register `%%%s' available only in 64bit mode."
msgstr ""
#. Prohibit these changes in the 64bit mode, since
#. the lowering is more complicated.
-#: config/tc-i386.c:1988 config/tc-i386.c:2042 config/tc-i386.c:2057
-#: config/tc-i386.c:2085 config/tc-i386.c:2113
+#: config/tc-i386.c:2017 config/tc-i386.c:2071 config/tc-i386.c:2086
+#: config/tc-i386.c:2114 config/tc-i386.c:2142
msgid "Incorrect register `%%%s' used with`%c' suffix"
msgstr ""
-#: config/tc-i386.c:1994 config/tc-i386.c:2047 config/tc-i386.c:2118
+#: config/tc-i386.c:2023 config/tc-i386.c:2076 config/tc-i386.c:2147
msgid "using `%%%s' instead of `%%%s' due to `%c' suffix"
msgstr ""
-#: config/tc-i386.c:2010 config/tc-i386.c:2028 config/tc-i386.c:2072
-#: config/tc-i386.c:2099
+#: config/tc-i386.c:2039 config/tc-i386.c:2057 config/tc-i386.c:2101
+#: config/tc-i386.c:2128
msgid "`%%%s' not allowed with `%s%c'"
msgstr ""
-#: config/tc-i386.c:2159
+#: config/tc-i386.c:2188
msgid "no instruction mnemonic suffix given; can't determine immediate size"
msgstr ""
-#: config/tc-i386.c:2185
+#: config/tc-i386.c:2214
#, c-format
msgid ""
"no instruction mnemonic suffix given; can't determine immediate size %x %c"
msgstr ""
-#: config/tc-i386.c:2210
+#: config/tc-i386.c:2239
msgid ""
"no instruction mnemonic suffix given and no register operands; can't size "
"instruction"
msgstr ""
-#: config/tc-i386.c:2258
+#: config/tc-i386.c:2287
msgid "64bit operations available only in 64bit modes."
msgstr ""
#. Reversed arguments on faddp, fsubp, etc.
-#: config/tc-i386.c:2326
+#: config/tc-i386.c:2355
msgid "translating to `%s %%%s,%%%s'"
msgstr ""
#. Extraneous `l' suffix on fp insn.
-#: config/tc-i386.c:2333
+#: config/tc-i386.c:2362
msgid "translating to `%s %%%s'"
msgstr ""
-#: config/tc-i386.c:2606
+#: config/tc-i386.c:2635
msgid "you can't `pop %%cs'"
msgstr ""
#. UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.
-#: config/tc-i386.c:2639
+#: config/tc-i386.c:2668
#, c-format
msgid "translating to `%sp'"
msgstr ""
-#: config/tc-i386.c:2682
+#: config/tc-i386.c:2711
msgid ""
"Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"
msgstr ""
-#: config/tc-i386.c:2729 config/tc-i386.c:2803 config/tc-i386.c:2850
+#: config/tc-i386.c:2770 config/tc-i386.c:2850 config/tc-i386.c:2886
msgid "skipping prefixes on this instruction"
msgstr ""
-#: config/tc-i386.c:2871
+#: config/tc-i386.c:2906
msgid "16-bit jump out of range"
msgstr ""
-#: config/tc-i386.c:2880
+#: config/tc-i386.c:2915
#, c-format
msgid "can't handle non absolute segment in `%s'"
msgstr ""
-#: config/tc-i386.c:3184
+#: config/tc-i386.c:3208
#, c-format
msgid "@%s reloc is not supported in %s bit mode"
msgstr ""
-#: config/tc-i386.c:3260
+#: config/tc-i386.c:3284
msgid "only 1 or 2 immediate operands are allowed"
msgstr ""
-#: config/tc-i386.c:3283 config/tc-i386.c:3491
+#: config/tc-i386.c:3307 config/tc-i386.c:3495
#, c-format
msgid "junk `%s' after expression"
msgstr ""
#. Missing or bad expr becomes absolute 0.
-#: config/tc-i386.c:3294
+#: config/tc-i386.c:3318
#, c-format
msgid "missing or invalid immediate expression `%s' taken as 0"
msgstr ""
-#: config/tc-i386.c:3325 config/tc-i386.c:3524
+#: config/tc-i386.c:3349 config/tc-i386.c:3556
#, c-format
msgid "unimplemented segment %s in operand"
msgstr ""
-#: config/tc-i386.c:3327 config/tc-i386.c:3526
+#: config/tc-i386.c:3351 config/tc-i386.c:3558
#, c-format
msgid "unimplemented segment type %d in operand"
msgstr ""
-#: config/tc-i386.c:3371 config/tc-i386.c:5505
+#: config/tc-i386.c:3395 config/tc-i386.c:5542
#, c-format
msgid "expecting scale factor of 1, 2, 4, or 8: got `%s'"
msgstr ""
-#: config/tc-i386.c:3378
+#: config/tc-i386.c:3402
#, c-format
msgid "scale factor of %d without an index register"
msgstr ""
+#: config/tc-i386.c:3515
+#, c-format
+msgid "bad expression used with @%s"
+msgstr ""
+
#. Missing or bad expr becomes absolute 0.
-#: config/tc-i386.c:3505
+#: config/tc-i386.c:3537
#, c-format
msgid "missing or invalid displacement expression `%s' taken as 0"
msgstr ""
-#: config/tc-i386.c:3611
+#: config/tc-i386.c:3643
#, c-format
msgid "`%s' is not a valid base/index expression"
msgstr ""
-#: config/tc-i386.c:3615
+#: config/tc-i386.c:3647
#, c-format
msgid "`%s' is not a valid %s bit base/index expression"
msgstr ""
-#: config/tc-i386.c:3690
+#: config/tc-i386.c:3722
#, c-format
msgid "bad memory operand `%s'"
msgstr ""
-#: config/tc-i386.c:3705
+#: config/tc-i386.c:3737
#, c-format
msgid "junk `%s' after register"
msgstr ""
-#: config/tc-i386.c:3714 config/tc-i386.c:3829 config/tc-i386.c:3867
+#: config/tc-i386.c:3746 config/tc-i386.c:3861 config/tc-i386.c:3899
#, c-format
msgid "bad register name `%s'"
msgstr ""
-#: config/tc-i386.c:3722
+#: config/tc-i386.c:3754
msgid "immediate operand illegal with absolute jump"
msgstr ""
-#: config/tc-i386.c:3744
+#: config/tc-i386.c:3776
#, c-format
msgid "too many memory references for `%s'"
msgstr ""
-#: config/tc-i386.c:3822
+#: config/tc-i386.c:3854
#, c-format
msgid "expecting `,' or `)' after index register in `%s'"
msgstr ""
-#: config/tc-i386.c:3846
+#: config/tc-i386.c:3878
#, c-format
msgid "expecting `)' after scale factor in `%s'"
msgstr ""
-#: config/tc-i386.c:3853
+#: config/tc-i386.c:3885
#, c-format
msgid "expecting index register or scale factor after `,'; got '%c'"
msgstr ""
-#: config/tc-i386.c:3860
+#: config/tc-i386.c:3892
#, c-format
msgid "expecting `,' or `)' after base register in `%s'"
msgstr ""
#. It's not a memory operand; argh!
-#: config/tc-i386.c:3901
+#: config/tc-i386.c:3933
#, c-format
msgid "invalid char %s beginning operand %d `%s'"
msgstr ""
-#: config/tc-i386.c:4080
+#: config/tc-i386.c:4117
msgid "long jump required"
msgstr ""
-#: config/tc-i386.c:4386
+#: config/tc-i386.c:4423
msgid "Bad call to md_atof ()"
msgstr ""
-#: config/tc-i386.c:4543
+#: config/tc-i386.c:4580
msgid "No compiled in support for x86_64"
msgstr ""
-#: config/tc-i386.c:4564
+#: config/tc-i386.c:4601
msgid ""
" -Q ignored\n"
" -V print assembler version number\n"
@@ -3609,63 +3613,63 @@ msgid ""
" -s ignored\n"
msgstr ""
-#: config/tc-i386.c:4571
+#: config/tc-i386.c:4608
msgid " -q quieten some warnings\n"
msgstr ""
-#: config/tc-i386.c:4630 config/tc-s390.c:1561
+#: config/tc-i386.c:4667 config/tc-s390.c:1561
msgid "GOT already in symbol table"
msgstr ""
-#: config/tc-i386.c:4760
+#: config/tc-i386.c:4797
#, c-format
msgid "can not do %d byte relocation"
msgstr ""
-#: config/tc-i386.c:4811 config/tc-s390.c:1888
+#: config/tc-i386.c:4848 config/tc-s390.c:1888
#, c-format
msgid "cannot represent relocation type %s"
msgstr ""
-#: config/tc-i386.c:5107
+#: config/tc-i386.c:5144
#, c-format
msgid "too many memory references for '%s'"
msgstr ""
-#: config/tc-i386.c:5270
+#: config/tc-i386.c:5307
#, c-format
msgid "Unknown operand modifier `%s'\n"
msgstr ""
-#: config/tc-i386.c:5477
+#: config/tc-i386.c:5514
#, c-format
msgid "`%s' is not a valid segment register"
msgstr ""
-#: config/tc-i386.c:5487 config/tc-i386.c:5608
+#: config/tc-i386.c:5524 config/tc-i386.c:5645
msgid "Register scaling only allowed in memory operands."
msgstr ""
-#: config/tc-i386.c:5518
+#: config/tc-i386.c:5555
msgid "Too many register references in memory operand.\n"
msgstr ""
-#: config/tc-i386.c:5587
+#: config/tc-i386.c:5624
#, c-format
msgid "Syntax error. Expecting a constant. Got `%s'.\n"
msgstr ""
-#: config/tc-i386.c:5657
+#: config/tc-i386.c:5694
#, c-format
msgid "Unrecognized token '%s'"
msgstr ""
-#: config/tc-i386.c:5674
+#: config/tc-i386.c:5711
#, c-format
msgid "Unexpected token `%s'\n"
msgstr ""
-#: config/tc-i386.c:5818
+#: config/tc-i386.c:5855
#, c-format
msgid "Unrecognized token `%s'\n"
msgstr ""
@@ -3674,7 +3678,7 @@ msgstr ""
msgid "Unknown temporary pseudo register"
msgstr ""
-#: config/tc-i860.c:181 config/tc-mips.c:1028
+#: config/tc-i860.c:181 config/tc-mips.c:1036
#, c-format
msgid "internal error: can't hash `%s': %s\n"
msgstr ""
@@ -3936,95 +3940,95 @@ msgstr ""
msgid "callj to difference of two symbols"
msgstr ""
-#: config/tc-ia64.c:998
+#: config/tc-ia64.c:1020
msgid "Unwind directive not followed by an instruction."
msgstr ""
-#: config/tc-ia64.c:4272
+#: config/tc-ia64.c:4297
msgid "Register name expected"
msgstr ""
-#: config/tc-ia64.c:4277 config/tc-ia64.c:4563
+#: config/tc-ia64.c:4302 config/tc-ia64.c:4588
msgid "Comma expected"
msgstr ""
-#: config/tc-ia64.c:4285
+#: config/tc-ia64.c:4310
msgid "Register value annotation ignored"
msgstr ""
-#: config/tc-ia64.c:4309
+#: config/tc-ia64.c:4334
msgid "Directive invalid within a bundle"
msgstr ""
-#: config/tc-ia64.c:4376
+#: config/tc-ia64.c:4401
msgid "Missing predicate relation type"
msgstr ""
-#: config/tc-ia64.c:4392
+#: config/tc-ia64.c:4417
msgid "Unrecognized predicate relation type"
msgstr ""
-#: config/tc-ia64.c:4412 config/tc-ia64.c:4437
+#: config/tc-ia64.c:4437 config/tc-ia64.c:4462
msgid "Predicate register expected"
msgstr ""
-#: config/tc-ia64.c:4424
+#: config/tc-ia64.c:4449
msgid "Duplicate predicate register ignored"
msgstr ""
-#: config/tc-ia64.c:4446
+#: config/tc-ia64.c:4471
msgid "Bad register range"
msgstr ""
-#: config/tc-ia64.c:4474
+#: config/tc-ia64.c:4499
msgid "Predicate source and target required"
msgstr ""
-#: config/tc-ia64.c:4476 config/tc-ia64.c:4488
+#: config/tc-ia64.c:4501 config/tc-ia64.c:4513
msgid "Use of p0 is not valid in this context"
msgstr ""
-#: config/tc-ia64.c:4483
+#: config/tc-ia64.c:4508
msgid "At least two PR arguments expected"
msgstr ""
-#: config/tc-ia64.c:4497
+#: config/tc-ia64.c:4522
msgid "At least one PR argument expected"
msgstr ""
-#: config/tc-ia64.c:4533
+#: config/tc-ia64.c:4558
#, c-format
msgid "Inserting \"%s\" into entry hint table failed: %s"
msgstr ""
#. FIXME -- need 62-bit relocation type
-#: config/tc-ia64.c:4990
+#: config/tc-ia64.c:5015
msgid "62-bit relocation not yet implemented"
msgstr ""
#. XXX technically, this is wrong: we should not be issuing warning
#. messages until we're sure this instruction pattern is going to
#. be used!
-#: config/tc-ia64.c:5063
+#: config/tc-ia64.c:5088
msgid "lower 16 bits of mask ignored"
msgstr ""
-#: config/tc-ia64.c:5618
+#: config/tc-ia64.c:5643
msgid "Value truncated to 62 bits"
msgstr ""
-#: config/tc-ia64.c:5969
+#: config/tc-ia64.c:5994
msgid ""
"Additional NOP may be necessary to workaround Itanium processor A/B step "
"errata"
msgstr ""
-#: config/tc-ia64.c:6152
+#: config/tc-ia64.c:6177
#, c-format
msgid "Unrecognized option '-x%s'"
msgstr ""
-#: config/tc-ia64.c:6180
+#: config/tc-ia64.c:6205
msgid ""
"IA-64 options:\n"
" -milp32|-milp64|-mlp64|-mp64\tselect data model (default -mlp64)\n"
@@ -4034,28 +4038,28 @@ msgid ""
" -xdebug\t\t debug dependency violation checker\n"
msgstr ""
-#: config/tc-ia64.c:6450 config/tc-mips.c:1015
+#: config/tc-ia64.c:6475 config/tc-mips.c:1023
msgid "Could not set architecture and machine"
msgstr ""
-#: config/tc-ia64.c:6542
+#: config/tc-ia64.c:6567
msgid "Explicit stops are ignored in auto mode"
msgstr ""
-#: config/tc-ia64.c:6592
+#: config/tc-ia64.c:6617
msgid "Found '{' after explicit switch to automatic mode"
msgstr ""
-#: config/tc-ia64.c:8305
+#: config/tc-ia64.c:8330
#, c-format
msgid "Unrecognized dependency specifier %d\n"
msgstr ""
-#: config/tc-ia64.c:9096
+#: config/tc-ia64.c:9121
msgid "Only the first path encountering the conflict is reported"
msgstr ""
-#: config/tc-ia64.c:9099
+#: config/tc-ia64.c:9124
msgid "This is the location of the conflicting usage"
msgstr ""
@@ -4190,7 +4194,7 @@ msgid ""
"is this intentional ?"
msgstr ""
-#: config/tc-m32r.c:1251 config/tc-ppc.c:1459 config/tc-ppc.c:3681 read.c:1358
+#: config/tc-m32r.c:1251 config/tc-ppc.c:1459 config/tc-ppc.c:3701 read.c:1358
msgid "Expected comma after symbol-name: rest of line ignored."
msgstr ""
@@ -4200,11 +4204,11 @@ msgid ".SCOMMon length (%ld.) <0! Ignored."
msgstr ""
#: config/tc-m32r.c:1275 config/tc-ppc.c:1481 config/tc-ppc.c:2392
-#: config/tc-ppc.c:3705
+#: config/tc-ppc.c:3725
msgid "ignoring bad alignment"
msgstr ""
-#: config/tc-m32r.c:1302 config/tc-ppc.c:1492 config/tc-ppc.c:3717 read.c:1382
+#: config/tc-m32r.c:1302 config/tc-ppc.c:1492 config/tc-ppc.c:3737 read.c:1382
#: read.c:2108
#, c-format
msgid "Ignoring attempt to re-define symbol `%s'."
@@ -4215,11 +4219,11 @@ msgstr ""
msgid "Length of .scomm \"%s\" is already %ld. Not changed to %ld."
msgstr ""
-#: config/tc-m32r.c:1788
+#: config/tc-m32r.c:1789
msgid "Unmatched high/shigh reloc"
msgstr ""
-#: config/tc-m68hc11.c:311
+#: config/tc-m68hc11.c:313
#, c-format
msgid ""
"Motorola 68HC11/68HC12 options:\n"
@@ -4235,55 +4239,55 @@ msgid ""
" (used for testing)\n"
msgstr ""
-#: config/tc-m68hc11.c:352
+#: config/tc-m68hc11.c:354
#, c-format
msgid "Default target `%s' is not supported."
msgstr ""
#. Dump the opcode statistics table.
-#: config/tc-m68hc11.c:371
+#: config/tc-m68hc11.c:373
msgid "Name # Modes Min ops Max ops Modes mask # Used\n"
msgstr ""
-#: config/tc-m68hc11.c:421
+#: config/tc-m68hc11.c:423
#, c-format
msgid "Option `%s' is not recognized."
msgstr ""
-#: config/tc-m68hc11.c:642
+#: config/tc-m68hc11.c:644
msgid "#<imm8>"
msgstr ""
-#: config/tc-m68hc11.c:651
+#: config/tc-m68hc11.c:653
msgid "#<imm16>"
msgstr ""
-#: config/tc-m68hc11.c:660 config/tc-m68hc11.c:669
+#: config/tc-m68hc11.c:662 config/tc-m68hc11.c:671
msgid "<imm8>,X"
msgstr ""
-#: config/tc-m68hc11.c:687
+#: config/tc-m68hc11.c:689
msgid "*<abs8>"
msgstr ""
-#: config/tc-m68hc11.c:699
+#: config/tc-m68hc11.c:701
msgid "#<mask>"
msgstr ""
-#: config/tc-m68hc11.c:709
+#: config/tc-m68hc11.c:711
#, c-format
msgid "symbol%d"
msgstr ""
-#: config/tc-m68hc11.c:711
+#: config/tc-m68hc11.c:713
msgid "<abs>"
msgstr ""
-#: config/tc-m68hc11.c:730
+#: config/tc-m68hc11.c:732
msgid "<label>"
msgstr ""
-#: config/tc-m68hc11.c:746
+#: config/tc-m68hc11.c:748
#, c-format
msgid ""
"# Example of `%s' instructions\n"
@@ -4291,243 +4295,243 @@ msgid ""
"_start:\n"
msgstr ""
-#: config/tc-m68hc11.c:794
+#: config/tc-m68hc11.c:796
#, c-format
msgid "Instruction `%s' is not recognized."
msgstr ""
-#: config/tc-m68hc11.c:799
+#: config/tc-m68hc11.c:801
#, c-format
msgid "Instruction formats for `%s':"
msgstr ""
-#: config/tc-m68hc11.c:932
+#: config/tc-m68hc11.c:934
#, c-format
msgid "Immediate operand is not allowed for operand %d."
msgstr ""
-#: config/tc-m68hc11.c:958
+#: config/tc-m68hc11.c:960
msgid "Indirect indexed addressing is not valid for 68HC11."
msgstr ""
-#: config/tc-m68hc11.c:978
+#: config/tc-m68hc11.c:980
msgid "Spurious `,' or bad indirect register addressing mode."
msgstr ""
-#: config/tc-m68hc11.c:994
+#: config/tc-m68hc11.c:996
msgid "Missing second register or offset for indexed-indirect mode."
msgstr ""
-#: config/tc-m68hc11.c:1004
+#: config/tc-m68hc11.c:1006
msgid "Missing second register for indexed-indirect mode."
msgstr ""
-#: config/tc-m68hc11.c:1020
+#: config/tc-m68hc11.c:1022
msgid "Missing `]' to close indexed-indirect mode."
msgstr ""
-#: config/tc-m68hc11.c:1064
+#: config/tc-m68hc11.c:1066
msgid "Illegal operand."
msgstr ""
-#: config/tc-m68hc11.c:1069
+#: config/tc-m68hc11.c:1071
msgid "Missing operand."
msgstr ""
-#: config/tc-m68hc11.c:1121
+#: config/tc-m68hc11.c:1123
msgid "Pre-increment mode is not valid for 68HC11"
msgstr ""
-#: config/tc-m68hc11.c:1134
+#: config/tc-m68hc11.c:1136
msgid "Wrong register in register indirect mode."
msgstr ""
-#: config/tc-m68hc11.c:1142
+#: config/tc-m68hc11.c:1144
msgid "Missing `]' to close register indirect operand."
msgstr ""
-#: config/tc-m68hc11.c:1159
+#: config/tc-m68hc11.c:1161
msgid "Post-decrement mode is not valid for 68HC11."
msgstr ""
-#: config/tc-m68hc11.c:1167
+#: config/tc-m68hc11.c:1169
msgid "Post-increment mode is not valid for 68HC11."
msgstr ""
-#: config/tc-m68hc11.c:1184
+#: config/tc-m68hc11.c:1186
msgid "Invalid indexed indirect mode."
msgstr ""
-#: config/tc-m68hc11.c:1278
+#: config/tc-m68hc11.c:1280
#, c-format
msgid "Trap id `%ld' is out of range."
msgstr ""
-#: config/tc-m68hc11.c:1282
+#: config/tc-m68hc11.c:1284
msgid "Trap id must be within [0x30..0x39] or [0x40..0xff]."
msgstr ""
-#: config/tc-m68hc11.c:1289
+#: config/tc-m68hc11.c:1291
#, c-format
msgid "Operand out of 8-bit range: `%ld'."
msgstr ""
-#: config/tc-m68hc11.c:1296
+#: config/tc-m68hc11.c:1298
msgid "The trap id must be a constant."
msgstr ""
-#: config/tc-m68hc11.c:1321
+#: config/tc-m68hc11.c:1323
#, c-format
msgid "Operand `%x' not recognized in fixup8."
msgstr ""
-#: config/tc-m68hc11.c:1341
+#: config/tc-m68hc11.c:1343
#, c-format
msgid "Operand out of 16-bit range: `%ld'."
msgstr ""
-#: config/tc-m68hc11.c:1362
+#: config/tc-m68hc11.c:1364
#, c-format
msgid "Operand `%x' not recognized in fixup16."
msgstr ""
-#: config/tc-m68hc11.c:1380
+#: config/tc-m68hc11.c:1382
#, c-format
msgid "Unexpected branch conversion with `%x'"
msgstr ""
-#: config/tc-m68hc11.c:1467 config/tc-m68hc11.c:1594
+#: config/tc-m68hc11.c:1469 config/tc-m68hc11.c:1596
#, c-format
msgid "Operand out of range for a relative branch: `%ld'"
msgstr ""
-#: config/tc-m68hc11.c:1562
+#: config/tc-m68hc11.c:1564
msgid "Invalid register for dbcc/tbcc instruction."
msgstr ""
-#: config/tc-m68hc11.c:1653
+#: config/tc-m68hc11.c:1655
#, c-format
msgid "Increment/decrement value is out of range: `%ld'."
msgstr ""
-#: config/tc-m68hc11.c:1664
+#: config/tc-m68hc11.c:1666
msgid "Expecting a register."
msgstr ""
-#: config/tc-m68hc11.c:1679
+#: config/tc-m68hc11.c:1681
msgid "Invalid register for post/pre increment."
msgstr ""
-#: config/tc-m68hc11.c:1709
+#: config/tc-m68hc11.c:1711
msgid "Invalid register."
msgstr ""
-#: config/tc-m68hc11.c:1716
+#: config/tc-m68hc11.c:1718
#, c-format
msgid "Offset out of 16-bit range: %ld."
msgstr ""
-#: config/tc-m68hc11.c:1721
+#: config/tc-m68hc11.c:1723
#, c-format
msgid "Offset out of 5-bit range for movw/movb insn: %ld."
msgstr ""
-#: config/tc-m68hc11.c:1787
+#: config/tc-m68hc11.c:1789
msgid "Expecting register D for indexed indirect mode."
msgstr ""
-#: config/tc-m68hc11.c:1789
+#: config/tc-m68hc11.c:1791
msgid "Indexed indirect mode is not allowed for movb/movw."
msgstr ""
-#: config/tc-m68hc11.c:1806
+#: config/tc-m68hc11.c:1808
msgid "Invalid accumulator register."
msgstr ""
-#: config/tc-m68hc11.c:1831
+#: config/tc-m68hc11.c:1833
msgid "Invalid indexed register."
msgstr ""
-#: config/tc-m68hc11.c:1839
+#: config/tc-m68hc11.c:1841
msgid "Addressing mode not implemented yet."
msgstr ""
-#: config/tc-m68hc11.c:1854
+#: config/tc-m68hc11.c:1856
msgid "Invalid source register for this instruction, use 'tfr'."
msgstr ""
-#: config/tc-m68hc11.c:1856
+#: config/tc-m68hc11.c:1858
msgid "Invalid source register."
msgstr ""
-#: config/tc-m68hc11.c:1861
+#: config/tc-m68hc11.c:1863
msgid "Invalid destination register for this instruction, use 'tfr'."
msgstr ""
-#: config/tc-m68hc11.c:1863
+#: config/tc-m68hc11.c:1865
msgid "Invalid destination register."
msgstr ""
-#: config/tc-m68hc11.c:1948
+#: config/tc-m68hc11.c:1950
msgid "Invalid indexed register, expecting register X."
msgstr ""
-#: config/tc-m68hc11.c:1950
+#: config/tc-m68hc11.c:1952
msgid "Invalid indexed register, expecting register Y."
msgstr ""
-#: config/tc-m68hc11.c:2242
+#: config/tc-m68hc11.c:2244
msgid "No instruction or missing opcode."
msgstr ""
-#: config/tc-m68hc11.c:2307
+#: config/tc-m68hc11.c:2309
#, c-format
msgid "Opcode `%s' is not recognized."
msgstr ""
-#: config/tc-m68hc11.c:2329
+#: config/tc-m68hc11.c:2331
#, c-format
msgid "Garbage at end of instruction: `%s'."
msgstr ""
-#: config/tc-m68hc11.c:2352
+#: config/tc-m68hc11.c:2354
#, c-format
msgid "Invalid operand for `%s'"
msgstr ""
-#: config/tc-m68hc11.c:2409
+#: config/tc-m68hc11.c:2411
#, c-format
msgid "Relocation %d is not supported by object file format."
msgstr ""
-#: config/tc-m68hc11.c:2590
+#: config/tc-m68hc11.c:2591
msgid "bra or bsr with undefined symbol."
msgstr ""
-#: config/tc-m68hc11.c:2701
+#: config/tc-m68hc11.c:2661 config/tc-m68hc11.c:2711
#, c-format
msgid "Subtype %d is not recognized."
msgstr ""
-#: config/tc-m68hc11.c:2738
+#: config/tc-m68hc11.c:2748
msgid "Expression too complex."
msgstr ""
-#: config/tc-m68hc11.c:2767
+#: config/tc-m68hc11.c:2777
msgid "Value out of 16-bit range."
msgstr ""
-#: config/tc-m68hc11.c:2790
+#: config/tc-m68hc11.c:2800
#, c-format
msgid "Value %ld too large for 8-bit PC-relative branch."
msgstr ""
-#: config/tc-m68hc11.c:2797
+#: config/tc-m68hc11.c:2807
#, c-format
msgid "Auto increment/decrement offset '%ld' is out of range."
msgstr ""
-#: config/tc-m68hc11.c:2808
+#: config/tc-m68hc11.c:2818
#, c-format
msgid "Line %d: unknown relocation type: 0x%x."
msgstr ""
@@ -4536,356 +4540,362 @@ msgstr ""
msgid "Unknown PC relative instruction"
msgstr ""
-#: config/tc-m68k.c:810
+#: config/tc-m68k.c:823
#, c-format
msgid "Can not do %d byte pc-relative relocation"
msgstr ""
-#: config/tc-m68k.c:812
+#: config/tc-m68k.c:825
#, c-format
msgid "Can not do %d byte pc-relative pic relocation"
msgstr ""
-#: config/tc-m68k.c:817
+#: config/tc-m68k.c:830
#, c-format
msgid "Can not do %d byte relocation"
msgstr ""
-#: config/tc-m68k.c:819
+#: config/tc-m68k.c:832
#, c-format
msgid "Can not do %d byte pic relocation"
msgstr ""
-#: config/tc-m68k.c:889
+#: config/tc-m68k.c:903
#, c-format
msgid "Unable to produce reloc against symbol '%s'"
msgstr ""
-#: config/tc-m68k.c:933 config/tc-mips.c:11263
+#: config/tc-m68k.c:947 config/tc-mips.c:11296
#, c-format
msgid "Cannot make %s relocation PC relative"
msgstr ""
-#: config/tc-m68k.c:1046 config/tc-tahoe.c:1519 config/tc-vax.c:1766
+#: config/tc-m68k.c:1040 config/tc-tahoe.c:1493 config/tc-vax.c:1756
msgid "No operator"
msgstr ""
-#: config/tc-m68k.c:1076 config/tc-tahoe.c:1536 config/tc-vax.c:1783
+#: config/tc-m68k.c:1070 config/tc-tahoe.c:1510 config/tc-vax.c:1773
msgid "Unknown operator"
msgstr ""
-#: config/tc-m68k.c:1851
+#: config/tc-m68k.c:1845
msgid "invalid instruction for this architecture; needs "
msgstr ""
-#: config/tc-m68k.c:1856
+#: config/tc-m68k.c:1850
msgid "fpu (68040, 68060 or 68881/68882)"
msgstr ""
-#: config/tc-m68k.c:1859
+#: config/tc-m68k.c:1853
msgid "mmu (68030 or 68851)"
msgstr ""
-#: config/tc-m68k.c:1862
+#: config/tc-m68k.c:1856
msgid "68020 or higher"
msgstr ""
-#: config/tc-m68k.c:1865
+#: config/tc-m68k.c:1859
msgid "68000 or higher"
msgstr ""
-#: config/tc-m68k.c:1868
+#: config/tc-m68k.c:1862
msgid "68010 or higher"
msgstr ""
-#: config/tc-m68k.c:1897
+#: config/tc-m68k.c:1891
msgid "operands mismatch"
msgstr ""
-#: config/tc-m68k.c:1954 config/tc-m68k.c:1960 config/tc-m68k.c:1966
+#: config/tc-m68k.c:1948 config/tc-m68k.c:1954 config/tc-m68k.c:1960
msgid "operand out of range"
msgstr ""
-#: config/tc-m68k.c:2023
+#: config/tc-m68k.c:2017
#, c-format
msgid "Bignum too big for %c format; truncated"
msgstr ""
-#: config/tc-m68k.c:2091
+#: config/tc-m68k.c:2085
msgid "displacement too large for this architecture; needs 68020 or higher"
msgstr ""
-#: config/tc-m68k.c:2201
+#: config/tc-m68k.c:2195
msgid ""
"scale factor invalid on this architecture; needs cpu32 or 68020 or higher"
msgstr ""
-#: config/tc-m68k.c:2206
+#: config/tc-m68k.c:2200
msgid "invalid index size for coldfire"
msgstr ""
-#: config/tc-m68k.c:2259
+#: config/tc-m68k.c:2253
msgid "Forcing byte displacement"
msgstr ""
-#: config/tc-m68k.c:2261
+#: config/tc-m68k.c:2255
msgid "byte displacement out of range"
msgstr ""
-#: config/tc-m68k.c:2308 config/tc-m68k.c:2346
+#: config/tc-m68k.c:2302 config/tc-m68k.c:2340
msgid "invalid operand mode for this architecture; needs 68020 or higher"
msgstr ""
-#: config/tc-m68k.c:2332 config/tc-m68k.c:2366
+#: config/tc-m68k.c:2326 config/tc-m68k.c:2360
msgid ":b not permitted; defaulting to :w"
msgstr ""
-#: config/tc-m68k.c:2443
+#: config/tc-m68k.c:2437
msgid "unsupported byte value; use a different suffix"
msgstr ""
-#: config/tc-m68k.c:2457
+#: config/tc-m68k.c:2451
msgid "unknown/incorrect operand"
msgstr ""
-#: config/tc-m68k.c:2490 config/tc-m68k.c:2498 config/tc-m68k.c:2505
-#: config/tc-m68k.c:2512
+#: config/tc-m68k.c:2484 config/tc-m68k.c:2492 config/tc-m68k.c:2499
+#: config/tc-m68k.c:2506
msgid "out of range"
msgstr ""
-#: config/tc-m68k.c:2562
+#: config/tc-m68k.c:2552
msgid "Can't use long branches on 68000/68010/5200"
msgstr ""
-#: config/tc-m68k.c:2672
+#: config/tc-m68k.c:2662
msgid "Expression out of range, using 0"
msgstr ""
-#: config/tc-m68k.c:2784 config/tc-m68k.c:2800
+#: config/tc-m68k.c:2774 config/tc-m68k.c:2790
msgid "Floating point register in register list"
msgstr ""
-#: config/tc-m68k.c:2790
+#: config/tc-m68k.c:2780
msgid "Wrong register in floating-point reglist"
msgstr ""
-#: config/tc-m68k.c:2806
+#: config/tc-m68k.c:2796
msgid "incorrect register in reglist"
msgstr ""
-#: config/tc-m68k.c:2812
+#: config/tc-m68k.c:2802
msgid "wrong register in floating-point reglist"
msgstr ""
-#: config/tc-m68k.c:2888
+#: config/tc-m68k.c:2878
msgid "failed sanity check"
msgstr ""
#. ERROR
-#: config/tc-m68k.c:3253
+#: config/tc-m68k.c:3243
msgid "Extra )"
msgstr ""
#. ERROR
-#: config/tc-m68k.c:3264
+#: config/tc-m68k.c:3254
msgid "Missing )"
msgstr ""
-#: config/tc-m68k.c:3281
+#: config/tc-m68k.c:3271
msgid "Missing operand"
msgstr ""
-#: config/tc-m68k.c:3613
+#: config/tc-m68k.c:3603
#, c-format
msgid "%s -- statement `%s' ignored"
msgstr ""
-#: config/tc-m68k.c:3657
+#: config/tc-m68k.c:3647
#, c-format
msgid "Don't know how to figure width of %c in md_assemble()"
msgstr ""
-#: config/tc-m68k.c:3825 config/tc-m68k.c:3863
+#: config/tc-m68k.c:3830 config/tc-m68k.c:3868
#, c-format
msgid "Internal Error: Can't find %s in hash table"
msgstr ""
-#: config/tc-m68k.c:3828 config/tc-m68k.c:3866
+#: config/tc-m68k.c:3833 config/tc-m68k.c:3871
#, c-format
msgid "Internal Error: Can't hash %s: %s"
msgstr ""
-#: config/tc-m68k.c:3995
+#: config/tc-m68k.c:4000
#, c-format
msgid "unrecognized default cpu `%s' ???"
msgstr ""
-#: config/tc-m68k.c:4007
+#: config/tc-m68k.c:4012
msgid "68040 and 68851 specified; mmu instructions may assemble incorrectly"
msgstr ""
-#: config/tc-m68k.c:4027
+#: config/tc-m68k.c:4032
msgid "options for 68881 and no-68881 both given"
msgstr ""
-#: config/tc-m68k.c:4029
+#: config/tc-m68k.c:4034
msgid "options for 68851 and no-68851 both given"
msgstr ""
-#: config/tc-m68k.c:4100
+#: config/tc-m68k.c:4105
#, c-format
msgid "text label `%s' aligned to odd boundary"
msgstr ""
-#: config/tc-m68k.c:4317
+#: config/tc-m68k.c:4319
msgid "invalid byte branch offset"
msgstr ""
-#: config/tc-m68k.c:4375
+#: config/tc-m68k.c:4377
msgid "short branch with zero offset: use :w"
msgstr ""
-#: config/tc-m68k.c:4910 config/tc-m68k.c:4921
+#: config/tc-m68k.c:4851 config/tc-m68k.c:4862
msgid "expression out of range: defaulting to 1"
msgstr ""
-#: config/tc-m68k.c:4953
+#: config/tc-m68k.c:4894
msgid "expression out of range: defaulting to 0"
msgstr ""
-#: config/tc-m68k.c:4986 config/tc-m68k.c:4998
+#: config/tc-m68k.c:4927 config/tc-m68k.c:4939
#, c-format
msgid "Can't deal with expression; defaulting to %ld"
msgstr ""
-#: config/tc-m68k.c:5012
+#: config/tc-m68k.c:4953
msgid "expression doesn't fit in BYTE"
msgstr ""
-#: config/tc-m68k.c:5016
+#: config/tc-m68k.c:4957
msgid "expression doesn't fit in WORD"
msgstr ""
-#: config/tc-m68k.c:5109
+#: config/tc-m68k.c:5050
#, c-format
msgid "%s: unrecognized processor name"
msgstr ""
-#: config/tc-m68k.c:5174
+#: config/tc-m68k.c:5115
msgid "bad coprocessor id"
msgstr ""
-#: config/tc-m68k.c:5180
+#: config/tc-m68k.c:5121
msgid "unrecognized fopt option"
msgstr ""
-#: config/tc-m68k.c:5314
+#: config/tc-m68k.c:5255
#, c-format
msgid "option `%s' may not be negated"
msgstr ""
-#: config/tc-m68k.c:5325
+#: config/tc-m68k.c:5266
#, c-format
msgid "option `%s' not recognized"
msgstr ""
-#: config/tc-m68k.c:5358
+#: config/tc-m68k.c:5299
msgid "bad format of OPT NEST=depth"
msgstr ""
-#: config/tc-m68k.c:5421
+#: config/tc-m68k.c:5362
msgid "missing label"
msgstr ""
-#: config/tc-m68k.c:5445 config/tc-m68k.c:5474
+#: config/tc-m68k.c:5386 config/tc-m68k.c:5415
msgid "bad register list"
msgstr ""
-#: config/tc-m68k.c:5447
+#: config/tc-m68k.c:5388
#, c-format
msgid "bad register list: %s"
msgstr ""
-#: config/tc-m68k.c:5545
+#: config/tc-m68k.c:5486
msgid "restore without save"
msgstr ""
-#: config/tc-m68k.c:5722 config/tc-m68k.c:6071
+#: config/tc-m68k.c:5663 config/tc-m68k.c:6050
msgid "syntax error in structured control directive"
msgstr ""
-#: config/tc-m68k.c:5773
+#: config/tc-m68k.c:5714
msgid "missing condition code in structured control directive"
msgstr ""
-#: config/tc-m68k.c:6105
+#: config/tc-m68k.c:5786
+#, c-format
+msgid ""
+"Condition <%c%c> in structured control directive can not be encoded correctly"
+msgstr ""
+
+#: config/tc-m68k.c:6093
msgid "missing then"
msgstr ""
-#: config/tc-m68k.c:6187
+#: config/tc-m68k.c:6175
msgid "else without matching if"
msgstr ""
-#: config/tc-m68k.c:6221
+#: config/tc-m68k.c:6209
msgid "endi without matching if"
msgstr ""
-#: config/tc-m68k.c:6262
+#: config/tc-m68k.c:6250
msgid "break outside of structured loop"
msgstr ""
-#: config/tc-m68k.c:6301
+#: config/tc-m68k.c:6289
msgid "next outside of structured loop"
msgstr ""
-#: config/tc-m68k.c:6353
+#: config/tc-m68k.c:6341
msgid "missing ="
msgstr ""
-#: config/tc-m68k.c:6391
+#: config/tc-m68k.c:6379
msgid "missing to or downto"
msgstr ""
-#: config/tc-m68k.c:6427 config/tc-m68k.c:6461 config/tc-m68k.c:6671
+#: config/tc-m68k.c:6415 config/tc-m68k.c:6449 config/tc-m68k.c:6668
msgid "missing do"
msgstr ""
-#: config/tc-m68k.c:6564
+#: config/tc-m68k.c:6552
msgid "endf without for"
msgstr ""
-#: config/tc-m68k.c:6620
+#: config/tc-m68k.c:6608
msgid "until without repeat"
msgstr ""
-#: config/tc-m68k.c:6707
+#: config/tc-m68k.c:6704
msgid "endw without while"
msgstr ""
-#: config/tc-m68k.c:6831
+#: config/tc-m68k.c:6828
#, c-format
msgid "unrecognized option `%s'"
msgstr ""
-#: config/tc-m68k.c:6876
+#: config/tc-m68k.c:6873
#, c-format
msgid "unrecognized architecture specification `%s'"
msgstr ""
-#: config/tc-m68k.c:6946
+#: config/tc-m68k.c:6943
msgid ""
"680X0 options:\n"
"-l\t\t\tuse 1 word for refs to undefined symbols [default 2]\n"
-"-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n"
-" | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n"
-" | -mcpu32 | -m5200\n"
+"-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n"
+"-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n"
+"-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n"
"\t\t\tspecify variant of 680X0 architecture [default 68020]\n"
"-m68881 | -m68882 | -mno-68881 | -mno-68882\n"
"\t\t\ttarget has/lacks floating-point coprocessor\n"
"\t\t\t[default yes for 68020, 68030, and cpu32]\n"
msgstr ""
-#: config/tc-m68k.c:6956
+#: config/tc-m68k.c:6953
msgid ""
"-m68851 | -mno-68851\n"
"\t\t\ttarget has/lacks memory-management unit coprocessor\n"
@@ -4898,7 +4908,7 @@ msgid ""
"--bitwise-or\t\tdo not treat `|' as a comment character\n"
msgstr ""
-#: config/tc-m68k.c:6966
+#: config/tc-m68k.c:6963
msgid ""
"--base-size-default-16\tbase reg without size is 16 bits\n"
"--base-size-default-32\tbase reg without size is 32 bits (default)\n"
@@ -4906,12 +4916,12 @@ msgid ""
"--disp-size-default-32\tdisplacement with unknown size is 32 bits (default)\n"
msgstr ""
-#: config/tc-m68k.c:7001
+#: config/tc-m68k.c:6998
#, c-format
msgid "Error %s in %s\n"
msgstr ""
-#: config/tc-m68k.c:7005
+#: config/tc-m68k.c:7002
#, c-format
msgid "Opcode(%d.%s): "
msgstr ""
@@ -4972,7 +4982,7 @@ msgstr ""
msgid "Relaxation should never occur"
msgstr ""
-#: config/tc-m88k.c:1265 config/tc-sparc.c:3541 read.c:1962
+#: config/tc-m88k.c:1265 config/tc-sparc.c:3547 read.c:1962
#, c-format
msgid "BSS length (%d.) <0! Ignored."
msgstr ""
@@ -5162,356 +5172,356 @@ msgstr ""
msgid "odd displacement at %x"
msgstr ""
-#: config/tc-mcore.c:2104
+#: config/tc-mcore.c:2099
msgid "unknown"
msgstr ""
-#: config/tc-mcore.c:2135
+#: config/tc-mcore.c:2130
#, c-format
msgid "odd distance branch (0x%x bytes)"
msgstr ""
-#: config/tc-mcore.c:2139
+#: config/tc-mcore.c:2134
#, c-format
msgid "pcrel for branch to %s too far (0x%x)"
msgstr ""
-#: config/tc-mcore.c:2158
+#: config/tc-mcore.c:2153
#, c-format
msgid "pcrel for lrw/jmpi/jsri to %s too far (0x%x)"
msgstr ""
-#: config/tc-mcore.c:2169
+#: config/tc-mcore.c:2164
#, c-format
msgid "pcrel for loopt too far (0x%x)"
msgstr ""
-#: config/tc-mcore.c:2402
+#: config/tc-mcore.c:2396
#, c-format
msgid "Can not do %d byte %srelocation"
msgstr ""
-#: config/tc-mcore.c:2404
+#: config/tc-mcore.c:2398
msgid "pc-relative"
msgstr ""
-#: config/tc-mcore.c:2421 config/tc-pj.c:569 config/tc-sh.c:3345
+#: config/tc-mcore.c:2415 config/tc-pj.c:569 config/tc-sh.c:3347
#, c-format
msgid "Cannot represent relocation type %s"
msgstr ""
-#: config/tc-mips.c:928
+#: config/tc-mips.c:936
msgid "-G not supported in this configuration."
msgstr ""
-#: config/tc-mips.c:997
+#: config/tc-mips.c:1005
msgid "trap exception not supported at ISA 1"
msgstr ""
-#: config/tc-mips.c:1054
+#: config/tc-mips.c:1062
#, c-format
msgid "internal: can't hash `%s': %s"
msgstr ""
-#: config/tc-mips.c:1062
+#: config/tc-mips.c:1070
#, c-format
msgid "internal error: bad mips16 opcode: %s %s\n"
msgstr ""
-#: config/tc-mips.c:1230
+#: config/tc-mips.c:1238
#, c-format
msgid "returned from mips_ip(%s) insn_opcode = 0x%x\n"
msgstr ""
-#: config/tc-mips.c:1783 config/tc-mips.c:11395
+#: config/tc-mips.c:1796 config/tc-mips.c:11428
msgid "extended instruction in delay slot"
msgstr ""
-#: config/tc-mips.c:1805 config/tc-mips.c:1812
+#: config/tc-mips.c:1818 config/tc-mips.c:1825
#, c-format
msgid "jump to misaligned address (0x%lx)"
msgstr ""
-#: config/tc-mips.c:2461 config/tc-mips.c:2815
+#: config/tc-mips.c:2477 config/tc-mips.c:2831
msgid "Macro instruction expanded into multiple instructions"
msgstr ""
-#: config/tc-mips.c:2868
+#: config/tc-mips.c:2884
msgid "unsupported large constant"
msgstr ""
-#: config/tc-mips.c:2870
+#: config/tc-mips.c:2886
#, c-format
msgid "Instruction %s requires absolute expression"
msgstr ""
-#: config/tc-mips.c:3016
+#: config/tc-mips.c:3032
msgid "Number larger than 32 bits"
msgstr ""
-#: config/tc-mips.c:3037
+#: config/tc-mips.c:3053
msgid "Number larger than 64 bits"
msgstr ""
-#: config/tc-mips.c:3305 config/tc-mips.c:3377 config/tc-mips.c:5072
-#: config/tc-mips.c:5123 config/tc-mips.c:5659 config/tc-mips.c:5722
+#: config/tc-mips.c:3321 config/tc-mips.c:3393 config/tc-mips.c:5092
+#: config/tc-mips.c:5143 config/tc-mips.c:5679 config/tc-mips.c:5742
msgid "PIC code offset overflow (max 16 signed bits)"
msgstr ""
-#: config/tc-mips.c:3616
+#: config/tc-mips.c:3633
#, c-format
msgid "Branch %s is always false (nop)"
msgstr ""
-#: config/tc-mips.c:3621
+#: config/tc-mips.c:3640
#, c-format
msgid "Branch likely %s is always false"
msgstr ""
-#: config/tc-mips.c:3628 config/tc-mips.c:3702 config/tc-mips.c:3805
-#: config/tc-mips.c:3860 config/tc-mips.c:6759 config/tc-mips.c:6768
-#: config/tc-mips.c:6776 config/tc-mips.c:6885
+#: config/tc-mips.c:3648 config/tc-mips.c:3722 config/tc-mips.c:3825
+#: config/tc-mips.c:3880 config/tc-mips.c:6779 config/tc-mips.c:6788
+#: config/tc-mips.c:6796 config/tc-mips.c:6905
msgid "Unsupported large constant"
msgstr ""
#. result is always true
-#: config/tc-mips.c:3664
+#: config/tc-mips.c:3684
#, c-format
msgid "Branch %s is always true"
msgstr ""
-#: config/tc-mips.c:3936 config/tc-mips.c:4043
+#: config/tc-mips.c:3956 config/tc-mips.c:4063
msgid "Divide by zero."
msgstr ""
-#: config/tc-mips.c:4643
+#: config/tc-mips.c:4663
msgid "MIPS PIC call to register other than $25"
msgstr ""
-#: config/tc-mips.c:4648 config/tc-mips.c:4760
+#: config/tc-mips.c:4668 config/tc-mips.c:4780
msgid "No .cprestore pseudo-op used in PIC code"
msgstr ""
-#: config/tc-mips.c:4833 config/tc-mips.c:4922 config/tc-mips.c:5410
-#: config/tc-mips.c:5451 config/tc-mips.c:5469 config/tc-mips.c:6098
+#: config/tc-mips.c:4853 config/tc-mips.c:4942 config/tc-mips.c:5430
+#: config/tc-mips.c:5471 config/tc-mips.c:5489 config/tc-mips.c:6118
msgid "opcode not supported on this processor"
msgstr ""
-#: config/tc-mips.c:5929 config/tc-mips.c:6653
+#: config/tc-mips.c:5949 config/tc-mips.c:6673
msgid "Macro used $at after \".set noat\""
msgstr ""
-#: config/tc-mips.c:6069 config/tc-mips.c:6087
+#: config/tc-mips.c:6089 config/tc-mips.c:6107
msgid "rotate count too large"
msgstr ""
-#: config/tc-mips.c:6138
+#: config/tc-mips.c:6158
#, c-format
msgid "Instruction %s: result is always false"
msgstr ""
-#: config/tc-mips.c:6307
+#: config/tc-mips.c:6327
#, c-format
msgid "Instruction %s: result is always true"
msgstr ""
-#: config/tc-mips.c:6446 config/tc-mips.c:6473 config/tc-mips.c:6545
-#: config/tc-mips.c:6570
+#: config/tc-mips.c:6466 config/tc-mips.c:6493 config/tc-mips.c:6565
+#: config/tc-mips.c:6590
msgid "operand overflow"
msgstr ""
#. FIXME: Check if this is one of the itbl macros, since they
#. are added dynamically.
-#: config/tc-mips.c:6649
+#: config/tc-mips.c:6669
#, c-format
msgid "Macro %s not implemented yet"
msgstr ""
-#: config/tc-mips.c:6919
+#: config/tc-mips.c:6939
#, c-format
msgid "internal: bad mips opcode (mask error): %s %s"
msgstr ""
-#: config/tc-mips.c:6975
+#: config/tc-mips.c:6995
#, c-format
msgid "internal: bad mips opcode (unknown operand type `%c'): %s %s"
msgstr ""
-#: config/tc-mips.c:6982
+#: config/tc-mips.c:7002
#, c-format
msgid "internal: bad mips opcode (bits 0x%lx undefined): %s %s"
msgstr ""
-#: config/tc-mips.c:7090
+#: config/tc-mips.c:7112
#, c-format
msgid "opcode not supported on this processor: %s (%s)"
msgstr ""
-#: config/tc-mips.c:7161
+#: config/tc-mips.c:7187
#, c-format
msgid "Improper shift amount (%ld)"
msgstr ""
-#: config/tc-mips.c:7187 config/tc-mips.c:8341 config/tc-mips.c:8456
+#: config/tc-mips.c:7213 config/tc-mips.c:8370 config/tc-mips.c:8485
#, c-format
msgid "Invalid value for `%s' (%lu)"
msgstr ""
-#: config/tc-mips.c:7205
+#: config/tc-mips.c:7231
#, c-format
msgid "Illegal break code (%ld)"
msgstr ""
-#: config/tc-mips.c:7219
+#: config/tc-mips.c:7245
#, c-format
msgid "Illegal lower break code (%ld)"
msgstr ""
-#: config/tc-mips.c:7232
+#: config/tc-mips.c:7258
#, c-format
msgid "Illegal 20-bit code (%ld)"
msgstr ""
-#: config/tc-mips.c:7244
+#: config/tc-mips.c:7270
#, c-format
msgid "Coproccesor code > 25 bits (%ld)"
msgstr ""
-#: config/tc-mips.c:7257
+#: config/tc-mips.c:7283
#, c-format
msgid "Illegal 19-bit code (%ld)"
msgstr ""
-#: config/tc-mips.c:7269
+#: config/tc-mips.c:7295
#, c-format
msgid "Invalidate performance regster (%ld)"
msgstr ""
-#: config/tc-mips.c:7306
+#: config/tc-mips.c:7332
#, c-format
msgid "Invalid register number (%d)"
msgstr ""
-#: config/tc-mips.c:7470
+#: config/tc-mips.c:7496
#, c-format
msgid "Invalid float register number (%d)"
msgstr ""
-#: config/tc-mips.c:7480
+#: config/tc-mips.c:7506
#, c-format
msgid "Float register should be even, was %d"
msgstr ""
-#: config/tc-mips.c:7531
+#: config/tc-mips.c:7557
msgid "absolute expression required"
msgstr ""
-#: config/tc-mips.c:7592
+#: config/tc-mips.c:7618
#, c-format
msgid "Bad floating point constant: %s"
msgstr ""
-#: config/tc-mips.c:7714
+#: config/tc-mips.c:7740
msgid "Can't use floating point insn in this section"
msgstr ""
-#: config/tc-mips.c:7768
+#: config/tc-mips.c:7794
msgid "16 bit expression not in range 0..65535"
msgstr ""
-#: config/tc-mips.c:7805
+#: config/tc-mips.c:7831
msgid "16 bit expression not in range -32768..32767"
msgstr ""
-#: config/tc-mips.c:7876
+#: config/tc-mips.c:7902
msgid "lui expression not in range 0..65535"
msgstr ""
-#: config/tc-mips.c:7900
+#: config/tc-mips.c:7926
#, c-format
msgid "invalid condition code register $fcc%d"
msgstr ""
-#: config/tc-mips.c:7925
+#: config/tc-mips.c:7951
msgid "invalid coprocessor sub-selection value (0-7)"
msgstr ""
-#: config/tc-mips.c:7930
+#: config/tc-mips.c:7956
#, c-format
msgid "bad char = '%c'\n"
msgstr ""
-#: config/tc-mips.c:7943 config/tc-mips.c:8481
+#: config/tc-mips.c:7967 config/tc-mips.c:7972 config/tc-mips.c:8510
msgid "illegal operands"
msgstr ""
-#: config/tc-mips.c:8010
+#: config/tc-mips.c:8039
msgid "unrecognized opcode"
msgstr ""
-#: config/tc-mips.c:8119
+#: config/tc-mips.c:8148
#, c-format
msgid "invalid register number (%d)"
msgstr ""
-#: config/tc-mips.c:8200
+#: config/tc-mips.c:8229
msgid "used $at without \".set noat\""
msgstr ""
-#: config/tc-mips.c:8375
+#: config/tc-mips.c:8404
msgid "can't parse register list"
msgstr ""
-#: config/tc-mips.c:8409 config/tc-mips.c:8439
+#: config/tc-mips.c:8438 config/tc-mips.c:8468
msgid "invalid register list"
msgstr ""
-#: config/tc-mips.c:8607
+#: config/tc-mips.c:8636
msgid "extended operand requested but not required"
msgstr ""
-#: config/tc-mips.c:8609
+#: config/tc-mips.c:8638
msgid "invalid unextended operand value"
msgstr ""
-#: config/tc-mips.c:8637
+#: config/tc-mips.c:8666
msgid "operand value out of range for instruction"
msgstr ""
-#: config/tc-mips.c:9022
+#: config/tc-mips.c:9056
#, c-format
msgid "invalid architecture -mcpu=%s"
msgstr ""
-#: config/tc-mips.c:9071
+#: config/tc-mips.c:9105
msgid "-G may not be used with embedded PIC code"
msgstr ""
-#: config/tc-mips.c:9084
+#: config/tc-mips.c:9118
msgid "-call_shared is supported only for ELF format"
msgstr ""
-#: config/tc-mips.c:9090 config/tc-mips.c:10179 config/tc-mips.c:10353
+#: config/tc-mips.c:9124 config/tc-mips.c:10221 config/tc-mips.c:10395
msgid "-G may not be used with SVR4 PIC code"
msgstr ""
-#: config/tc-mips.c:9099
+#: config/tc-mips.c:9133
msgid "-non_shared is supported only for ELF format"
msgstr ""
-#: config/tc-mips.c:9116
+#: config/tc-mips.c:9150
msgid "-G is not supported for this configuration"
msgstr ""
-#: config/tc-mips.c:9121
+#: config/tc-mips.c:9155
msgid "-G may not be used with SVR4 or embedded PIC code"
msgstr ""
-#: config/tc-mips.c:9146
+#: config/tc-mips.c:9182
msgid "No compiled in support for 64 bit object file format"
msgstr ""
-#: config/tc-mips.c:9239
+#: config/tc-mips.c:9275
msgid ""
"MIPS options:\n"
"-membedded-pic\t\tgenerate embedded position independent code\n"
@@ -5522,7 +5532,7 @@ msgid ""
"\t\t\timplicitly with the gp register [default 8]\n"
msgstr ""
-#: config/tc-mips.c:9247
+#: config/tc-mips.c:9283
msgid ""
"-mips1\t\t\tgenerate MIPS ISA I instructions\n"
"-mips2\t\t\tgenerate MIPS ISA II instructions\n"
@@ -5534,29 +5544,30 @@ msgid ""
"-mcpu=CPU\t\tgenerate code for CPU, where CPU is one of:\n"
msgstr ""
-#: config/tc-mips.c:9278
+#: config/tc-mips.c:9315
msgid ""
"-mCPU\t\t\tequivalent to -mcpu=CPU.\n"
"-no-mCPU\t\tdon't generate code specific to CPU.\n"
"\t\t\tFor -mCPU and -no-mCPU, CPU must be one of:\n"
msgstr ""
-#: config/tc-mips.c:9291
+#: config/tc-mips.c:9328
msgid ""
"-mips16\t\t\tgenerate mips16 instructions\n"
"-no-mips16\t\tdo not generate mips16 instructions\n"
msgstr ""
-#: config/tc-mips.c:9294
+#: config/tc-mips.c:9331
msgid ""
"-O0\t\t\tremove unneeded NOPs, do not swap branches\n"
"-O\t\t\tremove unneeded NOPs and swap branches\n"
+"-n\t\t\twarn about NOPs generated from macros\n"
"--[no-]construct-floats [dis]allow floating point values to be constructed\n"
"--trap, --no-break\ttrap exception on div by 0 and mult overflow\n"
"--break, --no-trap\tbreak exception on div by 0 and mult overflow\n"
msgstr ""
-#: config/tc-mips.c:9301
+#: config/tc-mips.c:9339
msgid ""
"-KPIC, -call_shared\tgenerate SVR4 position independent code\n"
"-non_shared\t\tdo not generate position independent code\n"
@@ -5565,170 +5576,170 @@ msgid ""
"-64\t\t\tcreate 64 bit object file\n"
msgstr ""
-#: config/tc-mips.c:9358
+#: config/tc-mips.c:9396
#, c-format
msgid "Unsupported reloc size %d"
msgstr ""
-#: config/tc-mips.c:9461
+#: config/tc-mips.c:9499
msgid "Unmatched %%hi reloc"
msgstr ""
-#: config/tc-mips.c:9584
+#: config/tc-mips.c:9626
msgid "Invalid PC relative reloc"
msgstr ""
-#: config/tc-mips.c:9694 config/tc-sparc.c:3102 config/tc-sparc.c:3109
-#: config/tc-sparc.c:3116 config/tc-sparc.c:3123 config/tc-sparc.c:3130
-#: config/tc-sparc.c:3139 config/tc-sparc.c:3150 config/tc-sparc.c:3176
-#: config/tc-sparc.c:3204 write.c:1025 write.c:1089
+#: config/tc-mips.c:9736 config/tc-sparc.c:3105 config/tc-sparc.c:3112
+#: config/tc-sparc.c:3119 config/tc-sparc.c:3126 config/tc-sparc.c:3133
+#: config/tc-sparc.c:3142 config/tc-sparc.c:3153 config/tc-sparc.c:3179
+#: config/tc-sparc.c:3207 write.c:1023 write.c:1087
msgid "relocation overflow"
msgstr ""
-#: config/tc-mips.c:9710
+#: config/tc-mips.c:9752
#, c-format
msgid "Branch to odd address (%lx)"
msgstr ""
-#: config/tc-mips.c:9874
+#: config/tc-mips.c:9916
#, c-format
msgid "%08lx UNDEFINED\n"
msgstr ""
-#: config/tc-mips.c:9940
+#: config/tc-mips.c:9982
msgid "Alignment negative: 0 assumed."
msgstr ""
-#: config/tc-mips.c:10028
+#: config/tc-mips.c:10070
msgid "No read only data section in this object file format"
msgstr ""
-#: config/tc-mips.c:10051
+#: config/tc-mips.c:10093
msgid "Global pointers not supported; recompile -G 0"
msgstr ""
-#: config/tc-mips.c:10137
+#: config/tc-mips.c:10179
#, c-format
msgid "%s: no such section"
msgstr ""
-#: config/tc-mips.c:10174
+#: config/tc-mips.c:10216
#, c-format
msgid ".option pic%d not supported"
msgstr ""
-#: config/tc-mips.c:10185
+#: config/tc-mips.c:10227
#, c-format
msgid "Unrecognized option \"%s\""
msgstr ""
-#: config/tc-mips.c:10248
+#: config/tc-mips.c:10290
msgid "`noreorder' must be set before `nomacro'"
msgstr ""
-#: config/tc-mips.c:10290
+#: config/tc-mips.c:10332
msgid "unknown ISA level"
msgstr ""
-#: config/tc-mips.c:10312
+#: config/tc-mips.c:10354
msgid ".set pop with no .set push"
msgstr ""
-#: config/tc-mips.c:10336
+#: config/tc-mips.c:10378
#, c-format
msgid "Tried to set unrecognized symbol: %s\n"
msgstr ""
-#: config/tc-mips.c:10386
+#: config/tc-mips.c:10428
msgid ".cpload not in noreorder section"
msgstr ""
-#: config/tc-mips.c:10468
+#: config/tc-mips.c:10510
msgid "Unsupported use of .gpword"
msgstr ""
-#: config/tc-mips.c:10605
+#: config/tc-mips.c:10647
msgid "expected `$'"
msgstr ""
-#: config/tc-mips.c:10613
+#: config/tc-mips.c:10655
msgid "Bad register number"
msgstr ""
-#: config/tc-mips.c:10629
+#: config/tc-mips.c:10671
msgid "Unrecognized register name"
msgstr ""
-#: config/tc-mips.c:10828
+#: config/tc-mips.c:10852
msgid "unsupported PC relative reference to different section"
msgstr ""
-#: config/tc-mips.c:10937
+#: config/tc-mips.c:10965
msgid "unsupported relocation"
msgstr ""
-#: config/tc-mips.c:11041
+#: config/tc-mips.c:11069
msgid "AT used after \".set noat\" or macro used after \".set nomacro\""
msgstr ""
-#: config/tc-mips.c:11104
+#: config/tc-mips.c:11137
msgid "Double check fx_r_type in tc-mips.c:tc_gen_reloc"
msgstr ""
-#: config/tc-mips.c:11617
+#: config/tc-mips.c:11650
msgid "missing `.end' at end of assembly"
msgstr ""
-#: config/tc-mips.c:11632
+#: config/tc-mips.c:11665
msgid "Expected simple number."
msgstr ""
-#: config/tc-mips.c:11658
+#: config/tc-mips.c:11691
#, c-format
msgid " *input_line_pointer == '%c' 0x%02x\n"
msgstr ""
-#: config/tc-mips.c:11660
+#: config/tc-mips.c:11693
msgid "Invalid number"
msgstr ""
-#: config/tc-mips.c:11714
+#: config/tc-mips.c:11747
msgid ".end not in text section"
msgstr ""
-#: config/tc-mips.c:11718
+#: config/tc-mips.c:11751
msgid ".end directive without a preceding .ent directive."
msgstr ""
-#: config/tc-mips.c:11727
+#: config/tc-mips.c:11760
msgid ".end symbol does not match .ent symbol."
msgstr ""
-#: config/tc-mips.c:11730
+#: config/tc-mips.c:11763
msgid ".end directive missing or unknown symbol"
msgstr ""
-#: config/tc-mips.c:11805
+#: config/tc-mips.c:11838
msgid ".ent or .aent not in text section."
msgstr ""
-#: config/tc-mips.c:11808
+#: config/tc-mips.c:11841
msgid "missing `.end'"
msgstr ""
-#: config/tc-mips.c:11841 ecoff.c:3206
+#: config/tc-mips.c:11874 ecoff.c:3206
msgid ".frame outside of .ent"
msgstr ""
-#: config/tc-mips.c:11852 ecoff.c:3217
+#: config/tc-mips.c:11885 ecoff.c:3217
msgid "Bad .frame directive"
msgstr ""
-#: config/tc-mips.c:11882
+#: config/tc-mips.c:11915
msgid ".mask/.fmask outside of .ent"
msgstr ""
-#: config/tc-mips.c:11889
+#: config/tc-mips.c:11922
msgid "Bad .mask/.fmask directive"
msgstr ""
@@ -5739,19 +5750,19 @@ msgid ""
msgstr ""
#: config/tc-mn10200.c:808 config/tc-mn10300.c:955 config/tc-ppc.c:1736
-#: config/tc-s390.c:1262 config/tc-v850.c:1728
+#: config/tc-s390.c:1262 config/tc-v850.c:1725
#, c-format
msgid "Unrecognized opcode: `%s'"
msgstr ""
#: config/tc-mn10200.c:1051 config/tc-mn10300.c:1478 config/tc-ppc.c:2097
-#: config/tc-s390.c:1188 config/tc-v850.c:2152
+#: config/tc-s390.c:1188 config/tc-v850.c:2149
#, c-format
msgid "junk at end of line: `%s'"
msgstr ""
-#: config/tc-mn10200.c:1365 config/tc-mn10300.c:2015 config/tc-ppc.c:1224
-#: config/tc-v850.c:1656
+#: config/tc-mn10200.c:1365 config/tc-mn10300.c:2074 config/tc-ppc.c:1224
+#: config/tc-v850.c:1654
#, c-format
msgid "operand out of range (%s not between %ld and %ld)"
msgstr ""
@@ -5922,18 +5933,18 @@ msgstr ""
msgid "Bit field out of range"
msgstr ""
-#: config/tc-ns32k.c:2182
+#: config/tc-ns32k.c:2170
#, c-format
msgid "invalid architecture option -m%s"
msgstr ""
-#: config/tc-ns32k.c:2198
+#: config/tc-ns32k.c:2186
msgid ""
"NS32K options:\n"
"-m32032 | -m32532\tselect variant of NS32K architecture\n"
msgstr ""
-#: config/tc-ns32k.c:2376
+#: config/tc-ns32k.c:2364
#, c-format
msgid "Cannot find relocation type for symbol %s, code %d"
msgstr ""
@@ -5958,12 +5969,12 @@ msgid ""
"-big\t\t\tgenerate big endian code\n"
msgstr ""
-#: config/tc-pj.c:458 config/tc-sh.c:2909 config/tc-sh.c:2916
-#: config/tc-sh.c:2923 config/tc-sh.c:2930
+#: config/tc-pj.c:458 config/tc-sh.c:2911 config/tc-sh.c:2918
+#: config/tc-sh.c:2925 config/tc-sh.c:2932
msgid "pcrel too far"
msgstr ""
-#: config/tc-pj.c:526 config/tc-sh.c:3021
+#: config/tc-pj.c:526 config/tc-sh.c:3023
msgid "offset out of range"
msgstr ""
@@ -6104,7 +6115,7 @@ msgstr ""
msgid "missing rename string"
msgstr ""
-#: config/tc-ppc.c:2780 config/tc-ppc.c:3305 read.c:3000
+#: config/tc-ppc.c:2780 config/tc-ppc.c:3325 read.c:3000
msgid "missing value"
msgstr ""
@@ -6120,93 +6131,93 @@ msgstr ""
msgid "missing type"
msgstr ""
-#: config/tc-ppc.c:2900
+#: config/tc-ppc.c:2920
msgid "missing symbol name"
msgstr ""
-#: config/tc-ppc.c:3076
+#: config/tc-ppc.c:3096
msgid "nested .bs blocks"
msgstr ""
-#: config/tc-ppc.c:3109
+#: config/tc-ppc.c:3129
msgid ".es without preceding .bs"
msgstr ""
-#: config/tc-ppc.c:3297
+#: config/tc-ppc.c:3317
msgid "non-constant byte count"
msgstr ""
-#: config/tc-ppc.c:3342
+#: config/tc-ppc.c:3362
msgid ".tc not in .toc section"
msgstr ""
-#: config/tc-ppc.c:3361
+#: config/tc-ppc.c:3381
msgid ".tc with no label"
msgstr ""
-#: config/tc-ppc.c:3436
+#: config/tc-ppc.c:3456
msgid "No previous section to return to. Directive ignored."
msgstr ""
#. Section Contents
#. unknown
-#: config/tc-ppc.c:3855
+#: config/tc-ppc.c:3875
msgid "Unsupported section attribute -- 'a'"
msgstr ""
-#: config/tc-ppc.c:4045
+#: config/tc-ppc.c:4065
msgid "bad symbol suffix"
msgstr ""
-#: config/tc-ppc.c:4138
+#: config/tc-ppc.c:4158
msgid "Unrecognized symbol suffix"
msgstr ""
-#: config/tc-ppc.c:4220
+#: config/tc-ppc.c:4240
msgid "two .function pseudo-ops with no intervening .ef"
msgstr ""
-#: config/tc-ppc.c:4233
+#: config/tc-ppc.c:4253
msgid ".ef with no preceding .function"
msgstr ""
-#: config/tc-ppc.c:4361
+#: config/tc-ppc.c:4381
#, c-format
msgid "warning: symbol %s has no csect"
msgstr ""
-#: config/tc-ppc.c:4662
+#: config/tc-ppc.c:4681
msgid "symbol in .toc does not match any .tc"
msgstr ""
-#: config/tc-ppc.c:4957 config/tc-s390.c:1726 config/tc-v850.c:2431
+#: config/tc-ppc.c:4975 config/tc-s390.c:1726 config/tc-v850.c:2423
msgid "unresolved expression that must be resolved"
msgstr ""
-#: config/tc-ppc.c:4960 config/tc-s390.c:1729
+#: config/tc-ppc.c:4978 config/tc-s390.c:1729
msgid "unsupported relocation type"
msgstr ""
-#: config/tc-ppc.c:5022
+#: config/tc-ppc.c:5040
#, c-format
msgid "cannot emit PC relative %s relocation against %s"
msgstr ""
-#: config/tc-ppc.c:5027
+#: config/tc-ppc.c:5045
#, c-format
msgid "cannot emit PC relative %s relocation"
msgstr ""
-#: config/tc-ppc.c:5089
+#: config/tc-ppc.c:5107
msgid "must branch to an address a multiple of 4"
msgstr ""
-#: config/tc-ppc.c:5093
+#: config/tc-ppc.c:5111
#, c-format
msgid "@local or @plt branch destination is too far away, %ld bytes"
msgstr ""
-#: config/tc-ppc.c:5117
+#: config/tc-ppc.c:5135
#, c-format
msgid "Gas failure, reloc value %d\n"
msgstr ""
@@ -6386,15 +6397,15 @@ msgstr ""
msgid "excess operands: '%s'"
msgstr ""
-#: config/tc-sh.c:2109
+#: config/tc-sh.c:2111
msgid ".uses pseudo-op seen when not relaxing"
msgstr ""
-#: config/tc-sh.c:2115
+#: config/tc-sh.c:2117
msgid "bad .uses format"
msgstr ""
-#: config/tc-sh.c:2176
+#: config/tc-sh.c:2178
msgid ""
"SH options:\n"
"-little\t\t\tgenerate little endian code\n"
@@ -6403,61 +6414,61 @@ msgid ""
"-dsp\t\t\tenable sh-dsp insns, and disable sh3e / sh4 insns.\n"
msgstr ""
-#: config/tc-sh.c:2187 config/tc-w65.c:856
+#: config/tc-sh.c:2189 config/tc-w65.c:856
msgid "call to tc_Nout_fix_to_chars \n"
msgstr ""
-#: config/tc-sh.c:2271
+#: config/tc-sh.c:2273
msgid ".uses does not refer to a local symbol in the same section"
msgstr ""
-#: config/tc-sh.c:2290
+#: config/tc-sh.c:2292
msgid "can't find fixup pointed to by .uses"
msgstr ""
-#: config/tc-sh.c:2313
+#: config/tc-sh.c:2315
msgid ".uses target does not refer to a local symbol in the same section"
msgstr ""
-#: config/tc-sh.c:2411
+#: config/tc-sh.c:2413
msgid "displacement overflows 12-bit field"
msgstr ""
-#: config/tc-sh.c:2414
+#: config/tc-sh.c:2416
#, c-format
msgid "displacement to defined symbol %s overflows 12-bit field"
msgstr ""
-#: config/tc-sh.c:2418
+#: config/tc-sh.c:2420
#, c-format
msgid "displacement to undefined symbol %s overflows 12-bit field"
msgstr ""
-#: config/tc-sh.c:2496
+#: config/tc-sh.c:2498
msgid "displacement overflows 8-bit field"
msgstr ""
-#: config/tc-sh.c:2499
+#: config/tc-sh.c:2501
#, c-format
msgid "displacement to defined symbol %s overflows 8-bit field"
msgstr ""
-#: config/tc-sh.c:2503
+#: config/tc-sh.c:2505
#, c-format
msgid "displacement to undefined symbol %s overflows 8-bit field "
msgstr ""
-#: config/tc-sh.c:2516
+#: config/tc-sh.c:2518
#, c-format
msgid "overflow in branch to %s; converted into longer instruction sequence"
msgstr ""
-#: config/tc-sh.c:2591 config/tc-sh.c:2639 config/tc-sparc.c:4085
-#: config/tc-sparc.c:4110
+#: config/tc-sh.c:2593 config/tc-sh.c:2641 config/tc-sparc.c:4088
+#: config/tc-sparc.c:4113
msgid "misaligned data"
msgstr ""
-#: config/tc-sh.c:3013
+#: config/tc-sh.c:3015
msgid "misaligned offset"
msgstr ""
@@ -6737,50 +6748,50 @@ msgstr ""
msgid " (Requires %s; requested architecture is %s.)"
msgstr ""
-#: config/tc-sparc.c:3250
+#: config/tc-sparc.c:3253
#, c-format
msgid "bad or unhandled relocation type: 0x%02x"
msgstr ""
-#: config/tc-sparc.c:3381
+#: config/tc-sparc.c:3387
#, c-format
msgid "internal error: can't export reloc type %d (`%s')"
msgstr ""
-#: config/tc-sparc.c:3553
+#: config/tc-sparc.c:3559
msgid "bad .reserve segment -- expected BSS segment"
msgstr ""
-#: config/tc-sparc.c:3570
+#: config/tc-sparc.c:3576
msgid "missing alignment"
msgstr ""
-#: config/tc-sparc.c:3581 config/tc-sparc.c:3731
+#: config/tc-sparc.c:3587 config/tc-sparc.c:3737
#, c-format
msgid "alignment too large; assuming %d"
msgstr ""
-#: config/tc-sparc.c:3587 config/tc-sparc.c:3737
+#: config/tc-sparc.c:3593 config/tc-sparc.c:3743
msgid "negative alignment"
msgstr ""
-#: config/tc-sparc.c:3597 config/tc-sparc.c:3760
+#: config/tc-sparc.c:3603 config/tc-sparc.c:3766
msgid "alignment not a power of 2"
msgstr ""
-#: config/tc-sparc.c:3717
+#: config/tc-sparc.c:3723
msgid "Expected comma after common length"
msgstr ""
-#: config/tc-sparc.c:3952 config/tc-sparc.c:3962
+#: config/tc-sparc.c:3958 config/tc-sparc.c:3968
msgid "register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"
msgstr ""
-#: config/tc-sparc.c:3980
+#: config/tc-sparc.c:3986
msgid "redefinition of global register"
msgstr ""
-#: config/tc-sparc.c:3991
+#: config/tc-sparc.c:3997
#, c-format
msgid "Register symbol %s already defined."
msgstr ""
@@ -6789,25 +6800,25 @@ msgstr ""
msgid "The -a option doesn't exist. (Despite what the man page says!"
msgstr ""
-#: config/tc-tahoe.c:406 config/tc-vax.c:3132
+#: config/tc-tahoe.c:406 config/tc-vax.c:3122
#, c-format
msgid "Displacement length %s ignored!"
msgstr ""
-#: config/tc-tahoe.c:410 config/tc-vax.c:3124
+#: config/tc-tahoe.c:410 config/tc-vax.c:3114
msgid "SYMBOL TABLE not implemented"
msgstr ""
-#: config/tc-tahoe.c:414 config/tc-vax.c:3128
+#: config/tc-tahoe.c:414 config/tc-vax.c:3118
msgid "TOKEN TRACE not implemented"
msgstr ""
-#: config/tc-tahoe.c:418 config/tc-vax.c:3136
+#: config/tc-tahoe.c:418 config/tc-vax.c:3126
#, c-format
msgid "I don't need or use temp. file \"%s\"."
msgstr ""
-#: config/tc-tahoe.c:422 config/tc-vax.c:3140
+#: config/tc-tahoe.c:422 config/tc-vax.c:3130
msgid "I don't use an interpass file! -V ignored"
msgstr ""
@@ -6823,186 +6834,186 @@ msgid ""
"-V\t\t\tignored\n"
msgstr ""
-#: config/tc-tahoe.c:1090
+#: config/tc-tahoe.c:1064
msgid "Casting a branch displacement is bad form, and is ignored."
msgstr ""
-#: config/tc-tahoe.c:1146
+#: config/tc-tahoe.c:1120
msgid "Couldn't parse the [index] in this operand."
msgstr ""
-#: config/tc-tahoe.c:1152
+#: config/tc-tahoe.c:1126
msgid "Couldn't find the opening '[' for the index of this operand."
msgstr ""
-#: config/tc-tahoe.c:1192
+#: config/tc-tahoe.c:1166
msgid "Couldn't find the opening '(' for the deref of this operand."
msgstr ""
-#: config/tc-tahoe.c:1202
+#: config/tc-tahoe.c:1176
msgid "Operand can't be both pre-inc and post-dec."
msgstr ""
-#: config/tc-tahoe.c:1232
+#: config/tc-tahoe.c:1206
msgid "I parsed 2 registers in this operand."
msgstr ""
-#: config/tc-tahoe.c:1282
+#: config/tc-tahoe.c:1256
msgid "Can't relocate expression error."
msgstr ""
#. This is an error. Tahoe doesn't allow any expressions
#. bigger that a 32 bit long word. Any bigger has to be referenced
#. by address.
-#: config/tc-tahoe.c:1289
+#: config/tc-tahoe.c:1263
msgid "Expression is too large for a 32 bits."
msgstr ""
-#: config/tc-tahoe.c:1294
+#: config/tc-tahoe.c:1268
msgid "Junk at end of expression."
msgstr ""
-#: config/tc-tahoe.c:1333
+#: config/tc-tahoe.c:1307
msgid "Syntax error in direct register mode."
msgstr ""
-#: config/tc-tahoe.c:1335
+#: config/tc-tahoe.c:1309
msgid "You can't index a register in direct register mode."
msgstr ""
-#: config/tc-tahoe.c:1338
+#: config/tc-tahoe.c:1312
msgid "SP can't be the source operand with direct register addressing."
msgstr ""
-#: config/tc-tahoe.c:1340
+#: config/tc-tahoe.c:1314
msgid "Can't take the address of a register."
msgstr ""
-#: config/tc-tahoe.c:1342
+#: config/tc-tahoe.c:1316
msgid "Direct Register can't be used in a branch."
msgstr ""
-#: config/tc-tahoe.c:1344
+#: config/tc-tahoe.c:1318
msgid "For quad access, the register must be even and < 14."
msgstr ""
-#: config/tc-tahoe.c:1346
+#: config/tc-tahoe.c:1320
msgid "You can't cast a direct register."
msgstr ""
-#: config/tc-tahoe.c:1352
+#: config/tc-tahoe.c:1326
msgid "Using reg 14 for quadwords can tromp the FP register."
msgstr ""
-#: config/tc-tahoe.c:1364
+#: config/tc-tahoe.c:1338
msgid "Syntax error in auto-dec mode."
msgstr ""
-#: config/tc-tahoe.c:1366
+#: config/tc-tahoe.c:1340
msgid "You can't have an index auto dec mode."
msgstr ""
-#: config/tc-tahoe.c:1368
+#: config/tc-tahoe.c:1342
msgid "Auto dec mode cant be used for reading."
msgstr ""
-#: config/tc-tahoe.c:1370
+#: config/tc-tahoe.c:1344
msgid "Auto dec only works of the SP register."
msgstr ""
-#: config/tc-tahoe.c:1372
+#: config/tc-tahoe.c:1346
msgid "Auto dec can't be used in a branch."
msgstr ""
-#: config/tc-tahoe.c:1374
+#: config/tc-tahoe.c:1348
msgid "Auto dec won't work with quadwords."
msgstr ""
-#: config/tc-tahoe.c:1381
+#: config/tc-tahoe.c:1355
msgid "Syntax error in one of the auto-inc modes."
msgstr ""
-#: config/tc-tahoe.c:1387
+#: config/tc-tahoe.c:1361
msgid "Auto inc deferred only works of the SP register."
msgstr ""
-#: config/tc-tahoe.c:1389
+#: config/tc-tahoe.c:1363
msgid "You can't have an index auto inc deferred mode."
msgstr ""
-#: config/tc-tahoe.c:1391 config/tc-tahoe.c:1402
+#: config/tc-tahoe.c:1365 config/tc-tahoe.c:1376
msgid "Auto inc can't be used in a branch."
msgstr ""
-#: config/tc-tahoe.c:1398
+#: config/tc-tahoe.c:1372
msgid "You can't write to an auto inc register."
msgstr ""
-#: config/tc-tahoe.c:1400
+#: config/tc-tahoe.c:1374
msgid "Auto inc only works of the SP register."
msgstr ""
-#: config/tc-tahoe.c:1404
+#: config/tc-tahoe.c:1378
msgid "Auto inc won't work with quadwords."
msgstr ""
-#: config/tc-tahoe.c:1406
+#: config/tc-tahoe.c:1380
msgid "You can't have an index in auto inc mode."
msgstr ""
-#: config/tc-tahoe.c:1414
+#: config/tc-tahoe.c:1388
msgid "You can't index the sp register."
msgstr ""
-#: config/tc-tahoe.c:1420
+#: config/tc-tahoe.c:1394
msgid "Syntax error in register displaced mode."
msgstr ""
-#: config/tc-tahoe.c:1439
+#: config/tc-tahoe.c:1413
msgid "An offest is needed for this operand."
msgstr ""
-#: config/tc-tahoe.c:1451
+#: config/tc-tahoe.c:1425
msgid "You can't index a register in immediate mode."
msgstr ""
-#: config/tc-tahoe.c:1453
+#: config/tc-tahoe.c:1427
msgid "Immediate access can't be used as an address."
msgstr ""
-#: config/tc-tahoe.c:1564
+#: config/tc-tahoe.c:1538
#, c-format
msgid "Compiler bug: ODD number of bytes in arg structure %s."
msgstr ""
-#: config/tc-tahoe.c:1591 config/tc-vax.c:1839
+#: config/tc-tahoe.c:1565 config/tc-vax.c:1829
msgid "Not enough operands"
msgstr ""
-#: config/tc-tahoe.c:1601 config/tc-vax.c:1846
+#: config/tc-tahoe.c:1575 config/tc-vax.c:1836
msgid "Too many operands"
msgstr ""
-#: config/tc-tahoe.c:1652 config/tc-vax.c:364
+#: config/tc-tahoe.c:1626 config/tc-vax.c:372
#, c-format
msgid "Ignoring statement due to \"%s\""
msgstr ""
-#: config/tc-tahoe.c:1747
+#: config/tc-tahoe.c:1721
#, c-format
msgid "Compliler bug: Got a case (%d) I wasn't expecting."
msgstr ""
-#: config/tc-tahoe.c:1841
+#: config/tc-tahoe.c:1815
msgid "Real branch displacements must be expressions."
msgstr ""
-#: config/tc-tahoe.c:1844
+#: config/tc-tahoe.c:1818
#, c-format
msgid "Complier error: I got an unknown synthetic branch :%c"
msgstr ""
-#: config/tc-tahoe.c:1985
+#: config/tc-tahoe.c:1959
#, c-format
msgid "Barf, bad mode %x\n"
msgstr ""
@@ -7519,335 +7530,335 @@ msgstr ""
msgid "md_convert_frag() not implemented yet"
msgstr ""
-#: config/tc-v850.c:270
+#: config/tc-v850.c:271
#, c-format
msgid ".COMMon length (%d.) < 0! Ignored."
msgstr ""
-#: config/tc-v850.c:1013
+#: config/tc-v850.c:1014
#, c-format
msgid "unknown operand shift: %x\n"
msgstr ""
-#: config/tc-v850.c:1014
+#: config/tc-v850.c:1015
msgid "internal failure in parse_register_list"
msgstr ""
-#: config/tc-v850.c:1031
+#: config/tc-v850.c:1032
msgid "constant expression or register list expected"
msgstr ""
-#: config/tc-v850.c:1036 config/tc-v850.c:1049 config/tc-v850.c:1068
+#: config/tc-v850.c:1037 config/tc-v850.c:1050 config/tc-v850.c:1069
msgid "high bits set in register list expression"
msgstr ""
-#: config/tc-v850.c:1108 config/tc-v850.c:1172
+#: config/tc-v850.c:1109 config/tc-v850.c:1173
msgid "illegal register included in list"
msgstr ""
-#: config/tc-v850.c:1115
+#: config/tc-v850.c:1116
msgid "system registers cannot be included in list"
msgstr ""
-#: config/tc-v850.c:1120
+#: config/tc-v850.c:1121
msgid "PSW cannot be included in list"
msgstr ""
-#: config/tc-v850.c:1127
+#: config/tc-v850.c:1128
msgid "High value system registers cannot be included in list"
msgstr ""
-#: config/tc-v850.c:1151
+#: config/tc-v850.c:1152
msgid "second register should follow dash in register list"
msgstr ""
-#: config/tc-v850.c:1198
+#: config/tc-v850.c:1199
msgid " V850 options:\n"
msgstr ""
-#: config/tc-v850.c:1199
+#: config/tc-v850.c:1200
msgid " -mwarn-signed-overflow Warn if signed immediate values overflow\n"
msgstr ""
-#: config/tc-v850.c:1200
+#: config/tc-v850.c:1201
msgid ""
" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n"
msgstr ""
-#: config/tc-v850.c:1201
+#: config/tc-v850.c:1202
msgid " -mv850 The code is targeted at the v850\n"
msgstr ""
-#: config/tc-v850.c:1202
+#: config/tc-v850.c:1203
msgid " -mv850e The code is targeted at the v850e\n"
msgstr ""
-#: config/tc-v850.c:1203
+#: config/tc-v850.c:1204
msgid " -mv850ea The code is targeted at the v850ea\n"
msgstr ""
-#: config/tc-v850.c:1204
+#: config/tc-v850.c:1205
msgid ""
" -mv850any The code is generic, despite any processor "
"specific instructions\n"
msgstr ""
-#: config/tc-v850.c:1216 config/tc-v850.c:1254
+#: config/tc-v850.c:1217 config/tc-v850.c:1255
#, c-format
msgid "unknown command line option: -%c%s\n"
msgstr ""
-#: config/tc-v850.c:1407
+#: config/tc-v850.c:1405
#, c-format
msgid "Unable to determine default target processor from string: %s"
msgstr ""
-#: config/tc-v850.c:1455
+#: config/tc-v850.c:1453
msgid "ctoff() relocation used on an instruction which does not support it"
msgstr ""
-#: config/tc-v850.c:1477
+#: config/tc-v850.c:1475
msgid "sdaoff() relocation used on an instruction which does not support it"
msgstr ""
-#: config/tc-v850.c:1499
+#: config/tc-v850.c:1497
msgid "zdaoff() relocation used on an instruction which does not support it"
msgstr ""
-#: config/tc-v850.c:1532
+#: config/tc-v850.c:1530
msgid "tdaoff() relocation used on an instruction which does not support it"
msgstr ""
-#: config/tc-v850.c:1749
+#: config/tc-v850.c:1746
msgid "Target processor does not support this instruction."
msgstr ""
-#: config/tc-v850.c:1839 config/tc-v850.c:1869 config/tc-v850.c:2057
+#: config/tc-v850.c:1836 config/tc-v850.c:1866 config/tc-v850.c:2054
msgid "immediate operand is too large"
msgstr ""
-#: config/tc-v850.c:1851
+#: config/tc-v850.c:1848
msgid "AAARG -> unhandled constant reloc"
msgstr ""
-#: config/tc-v850.c:1895
+#: config/tc-v850.c:1892
msgid "invalid register name"
msgstr ""
-#: config/tc-v850.c:1900
+#: config/tc-v850.c:1897
msgid "register r0 cannot be used here"
msgstr ""
-#: config/tc-v850.c:1912
+#: config/tc-v850.c:1909
msgid "invalid system register name"
msgstr ""
-#: config/tc-v850.c:1925
+#: config/tc-v850.c:1922
msgid "expected EP register"
msgstr ""
-#: config/tc-v850.c:1942
+#: config/tc-v850.c:1939
msgid "invalid condition code name"
msgstr ""
-#: config/tc-v850.c:1963 config/tc-v850.c:1967
+#: config/tc-v850.c:1960 config/tc-v850.c:1964
msgid "constant too big to fit into instruction"
msgstr ""
-#: config/tc-v850.c:2020
+#: config/tc-v850.c:2017
msgid "syntax error: value is missing before the register name"
msgstr ""
-#: config/tc-v850.c:2022
+#: config/tc-v850.c:2019
msgid "syntax error: register not expected"
msgstr ""
-#: config/tc-v850.c:2036
+#: config/tc-v850.c:2033
msgid "syntax error: system register not expected"
msgstr ""
-#: config/tc-v850.c:2041
+#: config/tc-v850.c:2038
msgid "syntax error: condition code not expected"
msgstr ""
-#: config/tc-v850.c:2082
+#: config/tc-v850.c:2079
msgid "invalid operand"
msgstr ""
-#: config/tc-vax.c:259
+#: config/tc-vax.c:267
#, c-format
msgid "VIP_BEGIN error:%s"
msgstr ""
-#: config/tc-vax.c:383
+#: config/tc-vax.c:391
#, c-format
msgid "Ignoring statement because \"%s\""
msgstr ""
-#: config/tc-vax.c:430
+#: config/tc-vax.c:438
msgid "Can't relocate expression"
msgstr ""
-#: config/tc-vax.c:533
+#: config/tc-vax.c:541
msgid "Bignum not permitted in short literal. Immediate mode assumed."
msgstr ""
-#: config/tc-vax.c:542
+#: config/tc-vax.c:550
msgid "Can't do flonum short literal: immediate mode used."
msgstr ""
-#: config/tc-vax.c:587
+#: config/tc-vax.c:595
#, c-format
msgid "A bignum/flonum may not be a displacement: 0x%lx used"
msgstr ""
-#: config/tc-vax.c:908
+#: config/tc-vax.c:916
#, c-format
msgid "Short literal overflow(%ld.), immediate mode assumed."
msgstr ""
-#: config/tc-vax.c:917
+#: config/tc-vax.c:925
#, c-format
msgid "Forced short literal to immediate mode. now_seg=%s to_seg=%s"
msgstr ""
-#: config/tc-vax.c:976
+#: config/tc-vax.c:984
msgid "Length specification ignored. Address mode 9F used"
msgstr ""
-#: config/tc-vax.c:1025
+#: config/tc-vax.c:1033
msgid "Invalid operand: immediate value used as base address."
msgstr ""
-#: config/tc-vax.c:1027
+#: config/tc-vax.c:1035
msgid "Invalid operand: immediate value used as address."
msgstr ""
-#: config/tc-vax.c:1818
+#: config/tc-vax.c:1808
msgid "odd number of bytes in operand description"
msgstr ""
-#: config/tc-vax.c:1834
+#: config/tc-vax.c:1824
msgid "Bad operand"
msgstr ""
-#: config/tc-vax.c:2390
+#: config/tc-vax.c:2380
msgid "no '[' to match ']'"
msgstr ""
-#: config/tc-vax.c:2408
+#: config/tc-vax.c:2398
msgid "bad register in []"
msgstr ""
-#: config/tc-vax.c:2410
+#: config/tc-vax.c:2400
msgid "[PC] index banned"
msgstr ""
-#: config/tc-vax.c:2445
+#: config/tc-vax.c:2435
msgid "no '(' to match ')'"
msgstr ""
-#: config/tc-vax.c:2580
+#: config/tc-vax.c:2570
msgid "invalid branch operand"
msgstr ""
-#: config/tc-vax.c:2609
+#: config/tc-vax.c:2599
msgid "address prohibits @"
msgstr ""
-#: config/tc-vax.c:2611
+#: config/tc-vax.c:2601
msgid "address prohibits #"
msgstr ""
-#: config/tc-vax.c:2615
+#: config/tc-vax.c:2605
msgid "address prohibits -()"
msgstr ""
-#: config/tc-vax.c:2617
+#: config/tc-vax.c:2607
msgid "address prohibits ()+"
msgstr ""
-#: config/tc-vax.c:2620
+#: config/tc-vax.c:2610
msgid "address prohibits ()"
msgstr ""
-#: config/tc-vax.c:2622
+#: config/tc-vax.c:2612
msgid "address prohibits []"
msgstr ""
-#: config/tc-vax.c:2624
+#: config/tc-vax.c:2614
msgid "address prohibits register"
msgstr ""
-#: config/tc-vax.c:2626
+#: config/tc-vax.c:2616
msgid "address prohibits displacement length specifier"
msgstr ""
-#: config/tc-vax.c:2656
+#: config/tc-vax.c:2646
msgid "invalid operand of S^#"
msgstr ""
-#: config/tc-vax.c:2673
+#: config/tc-vax.c:2663
msgid "S^# needs expression"
msgstr ""
-#: config/tc-vax.c:2680
+#: config/tc-vax.c:2670
msgid "S^# may only read-access"
msgstr ""
-#: config/tc-vax.c:2705
+#: config/tc-vax.c:2695
msgid "invalid operand of -()"
msgstr ""
-#: config/tc-vax.c:2711
+#: config/tc-vax.c:2701
msgid "-(PC) unpredictable"
msgstr ""
-#: config/tc-vax.c:2713
+#: config/tc-vax.c:2703
msgid "[]index same as -()register: unpredictable"
msgstr ""
-#: config/tc-vax.c:2749
+#: config/tc-vax.c:2739
msgid "invalid operand of ()+"
msgstr ""
-#: config/tc-vax.c:2755
+#: config/tc-vax.c:2745
msgid "(PC)+ unpredictable"
msgstr ""
-#: config/tc-vax.c:2757
+#: config/tc-vax.c:2747
msgid "[]index same as ()+register: unpredictable"
msgstr ""
-#: config/tc-vax.c:2782
+#: config/tc-vax.c:2772
msgid "# conflicts length"
msgstr ""
-#: config/tc-vax.c:2784
+#: config/tc-vax.c:2774
msgid "# bars register"
msgstr ""
-#: config/tc-vax.c:2806
+#: config/tc-vax.c:2796
msgid "writing or modifying # is unpredictable"
msgstr ""
-#: config/tc-vax.c:2836
+#: config/tc-vax.c:2826
msgid "length not needed"
msgstr ""
-#: config/tc-vax.c:2843
+#: config/tc-vax.c:2833
msgid "can't []index a register, because it has no address"
msgstr ""
-#: config/tc-vax.c:2845
+#: config/tc-vax.c:2835
msgid "a register has no address"
msgstr ""
-#: config/tc-vax.c:2856
+#: config/tc-vax.c:2846
msgid "PC part of operand unpredictable"
msgstr ""
-#: config/tc-vax.c:3185
+#: config/tc-vax.c:3175
msgid ""
"VAX options:\n"
"-d LENGTH\t\tignored\n"
@@ -7858,7 +7869,7 @@ msgid ""
"-V\t\t\tignored\n"
msgstr ""
-#: config/tc-vax.c:3194
+#: config/tc-vax.c:3184
msgid ""
"VMS options:\n"
"-+\t\t\thash encode names longer than 31 characters\n"
@@ -7877,84 +7888,84 @@ msgstr ""
msgid "syntax error after <exp"
msgstr ""
-#: config/tc-z8k.c:286
+#: config/tc-z8k.c:284
#, c-format
msgid "register rr%d, out of range."
msgstr ""
-#: config/tc-z8k.c:294
+#: config/tc-z8k.c:292
#, c-format
msgid "register rh%d, out of range."
msgstr ""
-#: config/tc-z8k.c:302
+#: config/tc-z8k.c:300
#, c-format
msgid "register rl%d, out of range."
msgstr ""
-#: config/tc-z8k.c:311
+#: config/tc-z8k.c:309
#, c-format
msgid "register rq%d, out of range."
msgstr ""
-#: config/tc-z8k.c:319
+#: config/tc-z8k.c:317
#, c-format
msgid "register r%d, out of range."
msgstr ""
-#: config/tc-z8k.c:364
+#: config/tc-z8k.c:362
#, c-format
msgid "expected %c"
msgstr ""
-#: config/tc-z8k.c:381
+#: config/tc-z8k.c:379
#, c-format
msgid "register is wrong size for a word %s"
msgstr ""
-#: config/tc-z8k.c:397
+#: config/tc-z8k.c:395
#, c-format
msgid "register is wrong size for address %s"
msgstr ""
-#: config/tc-z8k.c:665
+#: config/tc-z8k.c:656
msgid "Missing ) in ra(rb)"
msgstr ""
-#: config/tc-z8k.c:932
+#: config/tc-z8k.c:923
#, c-format
msgid "operand %s0x%x out of range."
msgstr ""
-#: config/tc-z8k.c:1070
+#: config/tc-z8k.c:1051
msgid "immediate must be 1 or 2"
msgstr ""
-#: config/tc-z8k.c:1073
+#: config/tc-z8k.c:1054
msgid "immediate 1 or 2 expected"
msgstr ""
-#: config/tc-z8k.c:1099
+#: config/tc-z8k.c:1080
msgid "can't use R0 here"
msgstr ""
-#: config/tc-z8k.c:1256
+#: config/tc-z8k.c:1234
msgid "Can't find opcode to match operands"
msgstr ""
-#: config/tc-z8k.c:1371
+#: config/tc-z8k.c:1349
#, c-format
msgid "invalid architecture -z%s"
msgstr ""
-#: config/tc-z8k.c:1387
+#: config/tc-z8k.c:1365
msgid ""
"Z8K options:\n"
"-z8001\t\t\tgenerate segmented code\n"
"-z8002\t\t\tgenerate unsegmented code\n"
msgstr ""
-#: config/tc-z8k.c:1531
+#: config/tc-z8k.c:1509
#, c-format
msgid "Can't subtract symbols in different sections %s %s"
msgstr ""
@@ -8191,11 +8202,11 @@ msgstr ""
msgid ".begin/.bend in different segments"
msgstr ""
-#: ecoff.c:4742
+#: ecoff.c:4743
msgid "Missing .end or .bend at end of file"
msgstr ""
-#: ecoff.c:5232
+#: ecoff.c:5233
msgid "GP prologue size exceeds field size, using 0 instead"
msgstr ""
@@ -8281,7 +8292,7 @@ msgstr ""
msgid "right operand is a float; integer 0 assumed"
msgstr ""
-#: expr.c:1797 symbols.c:1098
+#: expr.c:1797 symbols.c:1094
msgid "division by zero"
msgstr ""
@@ -8708,27 +8719,27 @@ msgstr ""
msgid "missplaced )"
msgstr ""
-#: macro.c:978
+#: macro.c:986
msgid "confusion in formal parameters"
msgstr ""
-#: macro.c:983
+#: macro.c:991
msgid "macro formal argument does not exist"
msgstr ""
-#: macro.c:998
+#: macro.c:1006
msgid "can't mix positional and keyword arguments"
msgstr ""
-#: macro.c:1006
+#: macro.c:1014
msgid "too many positional arguments"
msgstr ""
-#: macro.c:1186
+#: macro.c:1194
msgid "unexpected end of file in irp or irpc"
msgstr ""
-#: macro.c:1194
+#: macro.c:1202
msgid "missing model parameter"
msgstr ""
@@ -8996,11 +9007,11 @@ msgstr ""
msgid "attempt to store value in absolute section"
msgstr ""
-#: read.c:3501 read.c:4399
+#: read.c:3501 read.c:4400
msgid "zero assumed for missing expression"
msgstr ""
-#: read.c:3513 read.c:4411 write.c:291
+#: read.c:3513 read.c:4412 write.c:289
msgid "register value used as expression"
msgstr ""
@@ -9056,45 +9067,45 @@ msgstr ""
msgid "unresolvable or nonpositive repeat count; using 1"
msgstr ""
-#: read.c:4542
+#: read.c:4554
msgid "Expected <nn>"
msgstr ""
#. To be compatible with BSD 4.2 as: give the luser a linefeed!!
-#: read.c:4575 read.c:4661
+#: read.c:4587 read.c:4673
msgid "Unterminated string: Newline inserted."
msgstr ""
-#: read.c:4669
+#: read.c:4681
msgid "Bad escaped character in string, '?' assumed"
msgstr ""
-#: read.c:4695
+#: read.c:4707
msgid "expected address expression; zero assumed"
msgstr ""
-#: read.c:4715
+#: read.c:4727
#, c-format
msgid "symbol \"%s\" undefined; zero assumed"
msgstr ""
-#: read.c:4718
+#: read.c:4730
msgid "some symbol undefined; zero assumed"
msgstr ""
-#: read.c:4771
+#: read.c:4783
msgid "This string may not contain '\\0'"
msgstr ""
-#: read.c:4808
+#: read.c:4820
msgid "Missing string"
msgstr ""
-#: read.c:5044
+#: read.c:5056
msgid "missing .func"
msgstr ""
-#: read.c:5061
+#: read.c:5073
msgid ".endfunc missing for previous .func"
msgstr ""
@@ -9131,102 +9142,106 @@ msgstr ""
msgid "Inserting \"%s\" into symbol table failed: %s"
msgstr ""
-#: symbols.c:881
+#: symbols.c:876
#, c-format
msgid "Symbol definition loop encountered at %s"
msgstr ""
-#: symbols.c:1059 symbols.c:1063
+#: symbols.c:1055 symbols.c:1059
#, c-format
msgid "undefined symbol %s in operation"
msgstr ""
-#: symbols.c:1068
+#: symbols.c:1064
msgid "invalid section for operation"
msgstr ""
-#: symbols.c:1073 symbols.c:1077
+#: symbols.c:1069 symbols.c:1073
#, c-format
msgid "undefined symbol %s in operation setting %s"
msgstr ""
-#: symbols.c:1082
+#: symbols.c:1078
#, c-format
msgid "invalid section for operation setting %s"
msgstr ""
-#: symbols.c:1100
+#: symbols.c:1096
#, c-format
msgid "division by zero when setting %s"
msgstr ""
-#: symbols.c:1172 write.c:2010
+#: symbols.c:1168 write.c:2009
#, c-format
msgid "can't resolve value for symbol \"%s\""
msgstr ""
-#: symbols.c:1566
+#: symbols.c:1562
#, c-format
msgid "\"%d\" (instance number %d of a %s label)"
msgstr ""
-#: symbols.c:1603
+#: symbols.c:1599
#, c-format
msgid "Attempt to get value of unresolved symbol %s"
msgstr ""
-#: write.c:177
+#: symbols.c:1835
+msgid "Section symbols are already global"
+msgstr ""
+
+#: write.c:175
#, c-format
msgid "field fx_size too small to hold %d"
msgstr ""
-#: write.c:318
+#: write.c:316
msgid "rva not supported"
msgstr ""
-#: write.c:526
+#: write.c:524
#, c-format
msgid "attempt to .org/.space backwards? (%ld)"
msgstr ""
-#: write.c:1028
+#: write.c:1026
msgid "relocation out of range"
msgstr ""
-#: write.c:1031
+#: write.c:1029
#, c-format
msgid "%s:%u: bad return from bfd_install_relocation: %x"
msgstr ""
-#: write.c:1076
+#: write.c:1074
msgid "internal error: fixup not contained within frag"
msgstr ""
-#: write.c:1092
+#: write.c:1090
#, c-format
msgid "%s:%u: bad return from bfd_install_relocation"
msgstr ""
-#: write.c:1179 write.c:1203
+#: write.c:1177 write.c:1201
#, c-format
msgid "FATAL: Can't write %s"
msgstr ""
-#: write.c:1235
+#: write.c:1233
msgid "Cannot write to output file."
msgstr ""
-#: write.c:1484
+#: write.c:1482
#, c-format
msgid "%d error%s, %d warning%s, generating bad object file.\n"
msgstr ""
-#: write.c:1491
+#: write.c:1489
#, c-format
msgid "%d error%s, %d warning%s, no object file generated.\n"
msgstr ""
-#: write.c:1947
+#: write.c:1946
#, c-format
msgid "local label %s is not defined"
msgstr ""
@@ -9236,31 +9251,31 @@ msgstr ""
msgid "alignment padding (%lu bytes) not a multiple of %ld"
msgstr ""
-#: write.c:2357
+#: write.c:2358
#, c-format
msgid ".word %s-%s+%s didn't fit"
msgstr ""
-#: write.c:2438
+#: write.c:2439
msgid "attempt to .org backwards ignored"
msgstr ""
-#: write.c:2462
+#: write.c:2467
msgid ".space specifies non-absolute value"
msgstr ""
-#: write.c:2466
+#: write.c:2474
msgid ".space or .fill with negative value, ignored"
msgstr ""
-#: write.c:2721
+#: write.c:2730
#, c-format
msgid ""
"Subtraction of two symbols in different sections \"%s\" {%s section} - "
"\"%s\" {%s section} at file address %s."
msgstr ""
-#: write.c:2875
+#: write.c:2884
#, c-format
msgid "Value of %s too large for field of %d bytes at %s"
msgstr ""
generated by cgit v1.1 at 2024-11-04 16:31:43 +0000