Implement Intel Transactional Synchronization Extensions

gas/

2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (HLE_PREFIX): New.
	(check_hle): Likewise.
	(_i386_insn): Add have_hle.
	(cpu_arch): Add .hle and .rtm.
	(md_assemble): Call check_hle if i.have_hle isn't zero.
	(parse_insn): Set i.have_hle to 1 for HLE prefix.
	(output_jump): Support up to 2 byte opcode.

	* doc/c-i386.texi: Document hle/.hle and rtm/.rtm.

gas/testsuite/

2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/hle-intel.d: New.
	* gas/i386/hle.d: Likewise.
	* gas/i386/hle.s: Likewise.
	* gas/i386/hlebad.l: Likewise.
	* gas/i386/hlebad.s: Likewise.
	* gas/i386/rtm-intel.d: Likewise.
	* gas/i386/rtm.d: Likewise.
	* gas/i386/rtm.s: Likewise.
	* gas/i386/x86-64-hle-intel.d: Likewise.
	* gas/i386/x86-64-hle.d: Likewise.
	* gas/i386/x86-64-hle.s: Likewise.
	* gas/i386/x86-64-hlebad.l: Likewise.
	* gas/i386/x86-64-hlebad.s: Likewise.
	* gas/i386/x86-64-rtm-intel.d: Likewise.
	* gas/i386/x86-64-rtm.d: Likewise.
	* gas/i386/x86-64-rtm.s: Likewise.

	* gas/i386/i386.exp: Run hle, hle-intel, hlebad x86-64-hle, rtm,
	rtm-intel, x86-64-hle-intel, x86-64-hlebad, x86-64-rtm and
	x86-64-rtm-intel.

include/opcode/

2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (XACQUIRE_PREFIX_OPCODE): New.
	(XRELEASE_PREFIX_OPCODE): Likewise.

opcodes/

2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (HLE_Fixup1): New.
	(HLE_Fixup2): Likewise.
	(HLE_Fixup3): Likewise.
	(Ebh1): Likewise.
	(Evh1): Likewise.
	(Ebh2): Likewise.
	(Evh2): Likewise.
	(Ebh3): Likewise.
	(Evh3): Likewise.
	(MOD_C6_REG_7): Likewise.
	(MOD_C7_REG_7): Likewise.
	(RM_C6_REG_7): Likewise.
	(RM_C7_REG_7): Likewise.
	(XACQUIRE_PREFIX): Likewise.
	(XRELEASE_PREFIX): Likewise.
	(dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
	cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
	Ebh2/Evh2 on xchg.  Use Ebh3/Evh3 on mov.
	(reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
	not, or, sbb, sub and xor.  Use Ebh3/Evh3 on mov.  Use
	MOD_C6_REG_7 and MOD_C7_REG_7.
	(mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
	(rm_table): Add RM_C6_REG_7 and RM_C7_REG_7.  Add xend and
	xtest.
	(prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
	(CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.

	* i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
	CPU_RTM_FLAGS.
	(cpu_flags): Add CpuHLE and CpuRTM.
	(opcode_modifiers): Add HLEPrefixOk.

	* i386-opc.h (CpuHLE): New.
	(CpuRTM): Likewise.
	(HLEPrefixOk): Likewise.
	(i386_cpu_flags): Add cpuhle and cpurtm.
	(i386_opcode_modifier): Add hleprefixok.

	* i386-opc.tbl: Add HLEPrefixOk=3 to mov.  Add HLEPrefixOk to
	add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
	sbb, sub, xor and xadd.  Add HLEPrefixOk=2 to xchg with memory
	operand.  Add xacquire, xrelease, xabort, xbegin, xend and
	xtest.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

21 files changed, 11810 insertions, 5 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 143667a..dc5da04 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (HLE_PREFIX): New.
+	(check_hle): Likewise.
+	(_i386_insn): Add have_hle.
+	(cpu_arch): Add .hle and .rtm.
+	(md_assemble): Call check_hle if i.have_hle isn't zero.
+	(parse_insn): Set i.have_hle to 1 for HLE prefix.
+	(output_jump): Support up to 2 byte opcode.
+
+	* doc/c-i386.texi: Document hle/.hle and rtm/.rtm.
+
 2012-02-02  Tristan Gingold  <gingold@adacore.com>
 
 	* config/obj-macho.c (obj_mach_o_zerofill): Silent
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 75ed56c..97cb68e 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -60,12 +60,13 @@
    WAIT_PREFIX must be the first prefix since FWAIT is really is an
    instruction, and so must come before any prefixes.
    The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
-   REP_PREFIX, LOCK_PREFIX.  */
+   REP_PREFIX/HLE_PREFIX, LOCK_PREFIX.  */
 #define WAIT_PREFIX	0
 #define SEG_PREFIX	1
 #define ADDR_PREFIX	2
 #define DATA_PREFIX	3
 #define REP_PREFIX	4
+#define HLE_PREFIX	REP_PREFIX
 #define LOCK_PREFIX	5
 #define REX_PREFIX	6       /* must come last.  */
 #define MAX_PREFIXES	7	/* max prefixes per opcode */
@@ -288,6 +289,9 @@ struct _i386_insn
 	disp_encoding_32bit
       } disp_encoding;
 
+    /* Have HLE prefix.  */
+    unsigned int have_hle;
+
     /* Error message.  */
     enum i386_error error;
   };
@@ -731,6 +735,10 @@ static const arch_entry cpu_arch[] =
     CPU_EPT_FLAGS, 0, 0 },
   { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
     CPU_LZCNT_FLAGS, 0, 0 },
+  { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
+    CPU_HLE_FLAGS, 0, 0 },
+  { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
+    CPU_RTM_FLAGS, 0, 0 },
   { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
     CPU_INVPCID_FLAGS, 0, 0 },
   { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
@@ -2999,6 +3007,50 @@ process_immext (void)
   i.tm.extension_opcode = None;
 }
 
+
+static int
+check_hle (void)
+{
+  switch (i.tm.opcode_modifier.hleprefixok)
+    {
+    default:
+      abort ();
+    case 0:
+      if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE)
+	as_bad (_("invalid instruction `%s' after `xacquire'"),
+		i.tm.name);
+      else
+	as_bad (_("invalid instruction `%s' after `xrelease'"),
+		i.tm.name);
+      return 0;
+    case 1:
+      if (i.prefix[LOCK_PREFIX])
+	return 1;
+      if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE)
+	as_bad (_("missing `lock' with `xacquire'"));
+      else
+	as_bad (_("missing `lock' with `xrelease'"));
+      return 0;
+    case 2:
+      return 1;
+    case 3:
+      if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
+	{
+	  as_bad (_("instruction `%s' after `xacquire' not allowed"),
+		  i.tm.name);
+	  return 0;
+	}
+      if (i.mem_operands == 0
+	  || !operand_type_check (i.types[i.operands - 1], anymem))
+	{
+	  as_bad (_("memory destination needed for instruction `%s'"
+		    " after `xrelease'"), i.tm.name);
+	  return 0;
+	}
+      return 1;
+    }
+}
+
 /* This is the guts of the machine-dependent assembler.  LINE points to a
    machine dependent instruction.  This function is supposed to emit
    the frags/bytes it assembles to.  */
@@ -3117,6 +3169,10 @@ md_assemble (char *line)
       return;
     }
 
+  /* Check if HLE prefix is OK.  */
+  if (i.have_hle && !check_hle ())
+    return;
+
   /* Check string instruction segment overrides.  */
   if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
     {
@@ -3320,7 +3376,10 @@ parse_insn (char *line, char *mnemonic)
 	    case PREFIX_EXIST:
 	      return NULL;
 	    case PREFIX_REP:
-	      expecting_string_instruction = current_templates->start->name;
+	      if (current_templates->start->cpu_flags.bitfield.cpuhle)
+		i.have_hle = 1;
+	      else
+		expecting_string_instruction = current_templates->start->name;
 	      break;
 	    default:
 	      break;
@@ -6041,8 +6100,17 @@ output_jump (void)
   if (i.prefixes != 0 && !intel_syntax)
     as_warn (_("skipping prefixes on this instruction"));
 
-  p = frag_more (1 + size);
-  *p++ = i.tm.base_opcode;
+  p = frag_more (i.tm.opcode_length + size);
+  switch (i.tm.opcode_length)
+    {
+    case 2:
+      *p++ = i.tm.base_opcode >> 8;
+    case 1:
+      *p++ = i.tm.base_opcode;
+      break;
+    default:
+      abort ();
+    }
 
   fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
 		      i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 07f3462..7c19219 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -159,6 +159,8 @@ accept various extension mnemonics.  For example,
 @code{movbe},
 @code{ept},
 @code{lzcnt},
+@code{hle},
+@code{rtm},
 @code{invpcid},
 @code{clflush},
 @code{lwp},
@@ -1015,7 +1017,8 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
-@item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc}
+@item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle}
+@item @samp{.rtm}
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop}
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 80bf81b..8a75c1a 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,26 @@
+2012-02-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/hle-intel.d: New.
+	* gas/i386/hle.d: Likewise.
+	* gas/i386/hle.s: Likewise.
+	* gas/i386/hlebad.l: Likewise.
+	* gas/i386/hlebad.s: Likewise.
+	* gas/i386/rtm-intel.d: Likewise.
+	* gas/i386/rtm.d: Likewise.
+	* gas/i386/rtm.s: Likewise.
+	* gas/i386/x86-64-hle-intel.d: Likewise.
+	* gas/i386/x86-64-hle.d: Likewise.
+	* gas/i386/x86-64-hle.s: Likewise.
+	* gas/i386/x86-64-hlebad.l: Likewise.
+	* gas/i386/x86-64-hlebad.s: Likewise.
+	* gas/i386/x86-64-rtm-intel.d: Likewise.
+	* gas/i386/x86-64-rtm.d: Likewise.
+	* gas/i386/x86-64-rtm.s: Likewise.
+
+	* gas/i386/i386.exp: Run hle, hle-intel, hlebad x86-64-hle, rtm,
+	rtm-intel, x86-64-hle-intel, x86-64-hlebad, x86-64-rtm and
+	x86-64-rtm-intel.
+
 2012-01-20  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* gas/i386/disp32.s: Add tests for .d8 suffix.
diff --git a/gas/testsuite/gas/i386/hle-intel.d b/gas/testsuite/gas/i386/hle-intel.d
new file mode 100644
index 0000000..0caf954
--- /dev/null
+++ b/gas/testsuite/gas/i386/hle-intel.d
@@ -0,0 +1,1205 @@
+#objdump: -dwMintel
+#name: i386 HLE insns (Intel disassembly)
+#source: hle.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease mov BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adc WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adc WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adc WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adc WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 11 e8 03 	lock xacquire adc WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 11 e8 03 	lock xrelease adc WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock add WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock add WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock add WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock add WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 01 e8 03 	lock xacquire add WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 01 e8 03 	lock xrelease add WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock and WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock and WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock and WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock and WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 21 e8 03 	lock xacquire and WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 21 e8 03 	lock xrelease and WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 c7 01 e8 03    	xrelease mov WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock or WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock or WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock or WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock or WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 09 e8 03 	lock xacquire or WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 09 e8 03 	lock xrelease or WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbb WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbb WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbb WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbb WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 19 e8 03 	lock xacquire sbb WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 19 e8 03 	lock xrelease sbb WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock sub WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock sub WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock sub WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock sub WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 29 e8 03 	lock xacquire sub WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 29 e8 03 	lock xrelease sub WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xor WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xor WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xor WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xor WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 31 e8 03 	lock xacquire xor WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 31 e8 03 	lock xrelease xor WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adc DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adc DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adc DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adc DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 11 80 96 98 00 	lock xacquire adc DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 11 80 96 98 00 	lock xrelease adc DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock add DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock add DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock add DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock add DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 01 80 96 98 00 	lock xacquire add DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 01 80 96 98 00 	lock xrelease add DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock and DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock and DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock and DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock and DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 21 80 96 98 00 	lock xacquire and DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 21 80 96 98 00 	lock xrelease and DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 c7 01 80 96 98 00 	xrelease mov DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock or DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock or DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock or DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock or DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 09 80 96 98 00 	lock xacquire or DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 09 80 96 98 00 	lock xrelease or DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbb DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbb DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbb DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbb DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 19 80 96 98 00 	lock xacquire sbb DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 19 80 96 98 00 	lock xrelease sbb DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock sub DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock sub DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock sub DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock sub DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 29 80 96 98 00 	lock xacquire sub DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 29 80 96 98 00 	lock xrelease sub DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xor DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xor DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xor DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xor DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 31 80 96 98 00 	lock xacquire xor DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 31 80 96 98 00 	lock xrelease xor DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 11 64    	lock xacquire adc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 11 64    	lock xrelease adc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock add WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock add WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock add WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock add WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 01 64    	lock xacquire add WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 01 64    	lock xrelease add WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock and WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock and WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock and WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock and WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 21 64    	lock xacquire and WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 21 64    	lock xrelease and WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 39 64 	lock xacquire btc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 39 64 	lock xrelease btc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btr WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btr WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btr WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btr WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 31 64 	lock xacquire btr WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 31 64 	lock xrelease btr WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock bts WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock bts WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock bts WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock bts WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 29 64 	lock xacquire bts WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 29 64 	lock xrelease bts WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 c7 01 64 00    	xrelease mov WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock or WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock or WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock or WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock or WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 09 64    	lock xacquire or WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 09 64    	lock xrelease or WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbb WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbb WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbb WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbb WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 19 64    	lock xacquire sbb WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 19 64    	lock xrelease sbb WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock sub WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock sub WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock sub WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock sub WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 29 64    	lock xacquire sub WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 29 64    	lock xrelease sub WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xor WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xor WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xor WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xor WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 31 64    	lock xacquire xor WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 31 64    	lock xrelease xor WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 11 64       	lock xacquire adc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 11 64       	lock xrelease adc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock add DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock add DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock add DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock add DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 01 64       	lock xacquire add DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 01 64       	lock xrelease add DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock and DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock and DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock and DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock and DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 21 64       	lock xacquire and DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 21 64       	lock xrelease and DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 39 64    	lock xacquire btc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 39 64    	lock xrelease btc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btr DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btr DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btr DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btr DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 31 64    	lock xacquire btr DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 31 64    	lock xrelease btr DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock bts DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock bts DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock bts DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock bts DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 29 64    	lock xacquire bts DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 29 64    	lock xrelease bts DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 c7 01 64 00 00 00 	xrelease mov DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock or DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock or DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock or DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock or DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 09 64       	lock xacquire or DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 09 64       	lock xrelease or DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbb DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbb DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbb DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbb DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 19 64       	lock xacquire sbb DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 19 64       	lock xrelease sbb DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock sub DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock sub DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock sub DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock sub DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 29 64       	lock xacquire sub DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 29 64       	lock xrelease sub DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xor DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xor DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xor DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xor DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 31 64       	lock xacquire xor DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 31 64       	lock xrelease xor DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease mov BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 10 01          	lock xacquire adc BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 10 01          	lock xrelease adc BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 00 01          	lock xacquire add BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 00 01          	lock xrelease add BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 20 01          	lock xacquire and BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 20 01          	lock xrelease and BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 88 01             	xrelease mov BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 08 01          	lock xacquire or BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 08 01          	lock xrelease or BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 18 01          	lock xacquire sbb BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 18 01          	lock xrelease sbb BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 28 01          	lock xacquire sub BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 28 01          	lock xrelease sub BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 86 01             	xacquire xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 86 01             	xrelease xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 86 01          	lock xacquire xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 86 01          	lock xrelease xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 30 01          	lock xacquire xor BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 30 01          	lock xrelease xor BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 11 01       	lock xacquire adc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 11 01       	lock xrelease adc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 01 01       	lock xacquire add WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 01 01       	lock xrelease add WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 21 01       	lock xacquire and WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 21 01       	lock xrelease and WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 89 01          	xrelease mov WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 09 01       	lock xacquire or WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 09 01       	lock xrelease or WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 19 01       	lock xacquire sbb WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 19 01       	lock xrelease sbb WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 29 01       	lock xacquire sub WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 29 01       	lock xrelease sub WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 87 01          	xacquire xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 87 01          	xrelease xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 87 01       	lock xacquire xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 87 01       	lock xrelease xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 31 01       	lock xacquire xor WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 31 01       	lock xrelease xor WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 11 01          	lock xacquire adc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 11 01          	lock xrelease adc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 01 01          	lock xacquire add DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 01 01          	lock xrelease add DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 21 01          	lock xacquire and DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 21 01          	lock xrelease and DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 89 01             	xrelease mov DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 09 01          	lock xacquire or DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 09 01          	lock xrelease or DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 19 01          	lock xacquire sbb DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 19 01          	lock xrelease sbb DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 29 01          	lock xacquire sub DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 29 01          	lock xrelease sub DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 87 01             	xacquire xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 87 01             	xrelease xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 87 01          	lock xacquire xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 87 01          	lock xrelease xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 31 01          	lock xacquire xor DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 31 01          	lock xrelease xor DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f bb 01    	lock xacquire btc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f bb 01    	lock xrelease btc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b3 01    	lock xacquire btr WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b3 01    	lock xrelease btr WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ab 01    	lock xacquire bts WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ab 01    	lock xrelease bts WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b1 01    	lock xacquire cmpxchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b1 01    	lock xrelease cmpxchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f c1 01    	lock xacquire xadd WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f c1 01    	lock xrelease xadd WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f bb 01       	lock xacquire btc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f bb 01       	lock xrelease btc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f b3 01       	lock xacquire btr DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f b3 01       	lock xrelease btr DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f ab 01       	lock xacquire bts DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f ab 01       	lock xrelease bts DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f b1 01       	lock xacquire cmpxchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f b1 01       	lock xrelease cmpxchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f c1 01       	lock xacquire xadd DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f c1 01       	lock xrelease xadd DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock dec BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock dec BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock dec BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock dec BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 fe 09          	lock xacquire dec BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 fe 09          	lock xrelease dec BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock inc BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock inc BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock inc BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock inc BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 fe 01          	lock xacquire inc BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 fe 01          	lock xrelease inc BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock neg BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock neg BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock neg BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock neg BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 f6 19          	lock xacquire neg BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 f6 19          	lock xrelease neg BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock not BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock not BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock not BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock not BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 f6 11          	lock xacquire not BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 f6 11          	lock xrelease not BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock dec WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock dec WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock dec WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock dec WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 09       	lock xacquire dec WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 09       	lock xrelease dec WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock inc WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock inc WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock inc WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock inc WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 01       	lock xacquire inc WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 01       	lock xrelease inc WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock neg WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock neg WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock neg WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock neg WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 19       	lock xacquire neg WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 19       	lock xrelease neg WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock not WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock not WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock not WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock not WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 11       	lock xacquire not WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 11       	lock xrelease not WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock dec DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock dec DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock dec DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock dec DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 ff 09          	lock xacquire dec DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 ff 09          	lock xrelease dec DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock inc DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock inc DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock inc DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock inc DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 ff 01          	lock xacquire inc DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 ff 01          	lock xrelease inc DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock neg DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock neg DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock neg DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock neg DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 f7 19          	lock xacquire neg DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 f7 19          	lock xrelease neg DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock not DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock not DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock not DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock not DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 f7 11          	lock xacquire not DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 f7 11          	lock xrelease not DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 0f c7 09       	lock xacquire cmpxchg8b QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 0f c7 09       	lock xrelease cmpxchg8b QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f0 f2 0f b0 09       	lock xacquire cmpxchg BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f0 f3 0f b0 09       	lock xrelease cmpxchg BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f0 f2 0f c0 09       	lock xacquire xadd BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f0 f3 0f c0 09       	lock xrelease xadd BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease mov BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adc WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adc WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adc WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adc WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 11 e8 03 	lock xacquire adc WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 11 e8 03 	lock xrelease adc WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock add WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock add WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock add WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock add WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 01 e8 03 	lock xacquire add WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 01 e8 03 	lock xrelease add WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock and WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock and WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock and WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock and WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 21 e8 03 	lock xacquire and WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 21 e8 03 	lock xrelease and WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 c7 01 e8 03    	xrelease mov WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock or WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock or WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock or WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock or WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 09 e8 03 	lock xacquire or WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 09 e8 03 	lock xrelease or WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbb WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbb WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbb WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbb WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 19 e8 03 	lock xacquire sbb WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 19 e8 03 	lock xrelease sbb WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock sub WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock sub WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock sub WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock sub WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 29 e8 03 	lock xacquire sub WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 29 e8 03 	lock xrelease sub WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xor WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xor WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xor WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xor WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 31 e8 03 	lock xacquire xor WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 31 e8 03 	lock xrelease xor WORD PTR \[ecx\],0x3e8
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adc DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adc DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adc DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adc DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 11 80 96 98 00 	lock xacquire adc DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 11 80 96 98 00 	lock xrelease adc DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock add DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock add DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock add DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock add DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 01 80 96 98 00 	lock xacquire add DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 01 80 96 98 00 	lock xrelease add DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock and DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock and DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock and DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock and DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 21 80 96 98 00 	lock xacquire and DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 21 80 96 98 00 	lock xrelease and DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 c7 01 80 96 98 00 	xrelease mov DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock or DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock or DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock or DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock or DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 09 80 96 98 00 	lock xacquire or DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 09 80 96 98 00 	lock xrelease or DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbb DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbb DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbb DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbb DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 19 80 96 98 00 	lock xacquire sbb DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 19 80 96 98 00 	lock xrelease sbb DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock sub DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock sub DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock sub DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock sub DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 29 80 96 98 00 	lock xacquire sub DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 29 80 96 98 00 	lock xrelease sub DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xor DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xor DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xor DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xor DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 31 80 96 98 00 	lock xacquire xor DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 31 80 96 98 00 	lock xrelease xor DWORD PTR \[ecx\],0x989680
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 11 64    	lock xacquire adc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 11 64    	lock xrelease adc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock add WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock add WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock add WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock add WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 01 64    	lock xacquire add WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 01 64    	lock xrelease add WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock and WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock and WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock and WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock and WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 21 64    	lock xacquire and WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 21 64    	lock xrelease and WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 39 64 	lock xacquire btc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 39 64 	lock xrelease btc WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btr WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btr WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btr WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btr WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 31 64 	lock xacquire btr WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 31 64 	lock xrelease btr WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock bts WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock bts WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock bts WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock bts WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 29 64 	lock xacquire bts WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 29 64 	lock xrelease bts WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 c7 01 64 00    	xrelease mov WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock or WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock or WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock or WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock or WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 09 64    	lock xacquire or WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 09 64    	lock xrelease or WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbb WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbb WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbb WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbb WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 19 64    	lock xacquire sbb WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 19 64    	lock xrelease sbb WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock sub WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock sub WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock sub WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock sub WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 29 64    	lock xacquire sub WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 29 64    	lock xrelease sub WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xor WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xor WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xor WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xor WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 31 64    	lock xacquire xor WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 31 64    	lock xrelease xor WORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 11 64       	lock xacquire adc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 11 64       	lock xrelease adc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock add DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock add DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock add DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock add DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 01 64       	lock xacquire add DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 01 64       	lock xrelease add DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock and DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock and DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock and DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock and DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 21 64       	lock xacquire and DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 21 64       	lock xrelease and DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 39 64    	lock xacquire btc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 39 64    	lock xrelease btc DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btr DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btr DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btr DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btr DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 31 64    	lock xacquire btr DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 31 64    	lock xrelease btr DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock bts DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock bts DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock bts DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock bts DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 29 64    	lock xacquire bts DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 29 64    	lock xrelease bts DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 c7 01 64 00 00 00 	xrelease mov DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock or DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock or DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock or DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock or DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 09 64       	lock xacquire or DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 09 64       	lock xrelease or DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbb DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbb DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbb DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbb DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 19 64       	lock xacquire sbb DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 19 64       	lock xrelease sbb DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock sub DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock sub DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock sub DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock sub DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 29 64       	lock xacquire sub DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 29 64       	lock xrelease sub DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xor DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xor DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xor DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xor DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 31 64       	lock xacquire xor DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 31 64       	lock xrelease xor DWORD PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adc BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease add BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease and BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease mov BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease or BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbb BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease sub BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xor BYTE PTR \[ecx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 10 01          	lock xacquire adc BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 10 01          	lock xrelease adc BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 00 01          	lock xacquire add BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 00 01          	lock xrelease add BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 20 01          	lock xacquire and BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 20 01          	lock xrelease and BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 88 01             	xrelease mov BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 08 01          	lock xacquire or BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 08 01          	lock xrelease or BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 18 01          	lock xacquire sbb BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 18 01          	lock xrelease sbb BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 28 01          	lock xacquire sub BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 28 01          	lock xrelease sub BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 86 01             	xacquire xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 86 01             	xrelease xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 86 01          	lock xacquire xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 86 01          	lock xrelease xchg BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f2 30 01          	lock xacquire xor BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	f0 f3 30 01          	lock xrelease xor BYTE PTR \[ecx\],al
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 11 01       	lock xacquire adc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 11 01       	lock xrelease adc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 01 01       	lock xacquire add WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 01 01       	lock xrelease add WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 21 01       	lock xacquire and WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 21 01       	lock xrelease and WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 89 01          	xrelease mov WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 09 01       	lock xacquire or WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 09 01       	lock xrelease or WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 19 01       	lock xacquire sbb WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 19 01       	lock xrelease sbb WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 29 01       	lock xacquire sub WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 29 01       	lock xrelease sub WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 87 01          	xacquire xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 87 01          	xrelease xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 87 01       	lock xacquire xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 87 01       	lock xrelease xchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 31 01       	lock xacquire xor WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 31 01       	lock xrelease xor WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 11 01          	lock xacquire adc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 11 01          	lock xrelease adc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 01 01          	lock xacquire add DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 01 01          	lock xrelease add DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 21 01          	lock xacquire and DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 21 01          	lock xrelease and DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 89 01             	xrelease mov DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 09 01          	lock xacquire or DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 09 01          	lock xrelease or DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 19 01          	lock xacquire sbb DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 19 01          	lock xrelease sbb DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 29 01          	lock xacquire sub DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 29 01          	lock xrelease sub DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 87 01             	xacquire xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 87 01             	xrelease xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 87 01          	lock xacquire xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 87 01          	lock xrelease xchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 31 01          	lock xacquire xor DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 31 01          	lock xrelease xor DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f bb 01    	lock xacquire btc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f bb 01    	lock xrelease btc WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b3 01    	lock xacquire btr WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b3 01    	lock xrelease btr WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ab 01    	lock xacquire bts WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ab 01    	lock xrelease bts WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b1 01    	lock xacquire cmpxchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b1 01    	lock xrelease cmpxchg WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f c1 01    	lock xacquire xadd WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f c1 01    	lock xrelease xadd WORD PTR \[ecx\],ax
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f bb 01       	lock xacquire btc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f bb 01       	lock xrelease btc DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f b3 01       	lock xacquire btr DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f b3 01       	lock xrelease btr DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f ab 01       	lock xacquire bts DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f ab 01       	lock xrelease bts DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f b1 01       	lock xacquire cmpxchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f b1 01       	lock xrelease cmpxchg DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f c1 01       	lock xacquire xadd DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f c1 01       	lock xrelease xadd DWORD PTR \[ecx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock dec BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock dec BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock dec BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock dec BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 fe 09          	lock xacquire dec BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 fe 09          	lock xrelease dec BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock inc BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock inc BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock inc BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock inc BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 fe 01          	lock xacquire inc BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 fe 01          	lock xrelease inc BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock neg BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock neg BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock neg BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock neg BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 f6 19          	lock xacquire neg BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 f6 19          	lock xrelease neg BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock not BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock not BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock not BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock not BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 f6 11          	lock xacquire not BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 f6 11          	lock xrelease not BYTE PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock dec WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock dec WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock dec WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock dec WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 09       	lock xacquire dec WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 09       	lock xrelease dec WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock inc WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock inc WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock inc WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock inc WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 01       	lock xacquire inc WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 01       	lock xrelease inc WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock neg WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock neg WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock neg WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock neg WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 19       	lock xacquire neg WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 19       	lock xrelease neg WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock not WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock not WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock not WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock not WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 11       	lock xacquire not WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 11       	lock xrelease not WORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock dec DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock dec DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock dec DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock dec DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 ff 09          	lock xacquire dec DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 ff 09          	lock xrelease dec DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock inc DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock inc DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock inc DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock inc DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 ff 01          	lock xacquire inc DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 ff 01          	lock xrelease inc DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock neg DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock neg DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock neg DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock neg DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 f7 19          	lock xacquire neg DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 f7 19          	lock xrelease neg DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock not DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock not DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock not DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock not DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 f7 11          	lock xacquire not DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 f7 11          	lock xrelease not DWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f2 0f c7 09       	lock xacquire cmpxchg8b QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f0 f3 0f c7 09       	lock xrelease cmpxchg8b QWORD PTR \[ecx\]
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f0 f2 0f b0 09       	lock xacquire cmpxchg BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f0 f3 0f b0 09       	lock xrelease cmpxchg BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f0 f2 0f c0 09       	lock xacquire xadd BYTE PTR \[ecx\],cl
+[ 	]*[a-f0-9]+:	f0 f3 0f c0 09       	lock xrelease xadd BYTE PTR \[ecx\],cl
+#pass
diff --git a/gas/testsuite/gas/i386/hle.d b/gas/testsuite/gas/i386/hle.d
new file mode 100644
index 0000000..bf7bdcf
--- /dev/null
+++ b/gas/testsuite/gas/i386/hle.d
@@ -0,0 +1,1204 @@
+#objdump: -dw
+#name: i386 HLE insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease movb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adcw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adcw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adcw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adcw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 11 e8 03 	lock xacquire adcw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 11 e8 03 	lock xrelease adcw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock addw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock addw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock addw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock addw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 01 e8 03 	lock xacquire addw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 01 e8 03 	lock xrelease addw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock andw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock andw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock andw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock andw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 21 e8 03 	lock xacquire andw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 21 e8 03 	lock xrelease andw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 c7 01 e8 03    	xrelease movw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock orw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock orw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock orw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock orw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 09 e8 03 	lock xacquire orw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 09 e8 03 	lock xrelease orw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbbw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbbw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbbw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbbw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 19 e8 03 	lock xacquire sbbw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 19 e8 03 	lock xrelease sbbw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock subw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock subw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock subw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock subw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 29 e8 03 	lock xacquire subw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 29 e8 03 	lock xrelease subw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xorw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xorw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xorw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xorw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 31 e8 03 	lock xacquire xorw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 31 e8 03 	lock xrelease xorw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adcl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adcl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adcl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adcl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 11 80 96 98 00 	lock xacquire adcl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 11 80 96 98 00 	lock xrelease adcl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock addl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock addl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock addl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock addl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 01 80 96 98 00 	lock xacquire addl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 01 80 96 98 00 	lock xrelease addl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock andl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock andl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock andl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock andl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 21 80 96 98 00 	lock xacquire andl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 21 80 96 98 00 	lock xrelease andl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 c7 01 80 96 98 00 	xrelease movl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock orl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock orl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock orl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock orl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 09 80 96 98 00 	lock xacquire orl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 09 80 96 98 00 	lock xrelease orl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbbl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbbl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbbl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbbl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 19 80 96 98 00 	lock xacquire sbbl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 19 80 96 98 00 	lock xrelease sbbl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock subl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock subl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock subl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock subl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 29 80 96 98 00 	lock xacquire subl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 29 80 96 98 00 	lock xrelease subl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xorl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xorl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xorl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xorl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 31 80 96 98 00 	lock xacquire xorl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 31 80 96 98 00 	lock xrelease xorl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 11 64    	lock xacquire adcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 11 64    	lock xrelease adcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock addw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock addw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock addw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock addw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 01 64    	lock xacquire addw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 01 64    	lock xrelease addw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock andw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock andw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock andw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock andw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 21 64    	lock xacquire andw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 21 64    	lock xrelease andw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 39 64 	lock xacquire btcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 39 64 	lock xrelease btcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btrw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btrw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btrw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btrw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 31 64 	lock xacquire btrw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 31 64 	lock xrelease btrw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock btsw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock btsw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock btsw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock btsw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 29 64 	lock xacquire btsw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 29 64 	lock xrelease btsw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 c7 01 64 00    	xrelease movw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock orw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock orw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock orw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock orw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 09 64    	lock xacquire orw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 09 64    	lock xrelease orw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbbw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbbw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbbw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbbw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 19 64    	lock xacquire sbbw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 19 64    	lock xrelease sbbw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock subw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock subw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock subw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock subw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 29 64    	lock xacquire subw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 29 64    	lock xrelease subw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xorw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xorw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xorw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xorw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 31 64    	lock xacquire xorw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 31 64    	lock xrelease xorw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 11 64       	lock xacquire adcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 11 64       	lock xrelease adcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock addl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock addl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock addl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock addl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 01 64       	lock xacquire addl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 01 64       	lock xrelease addl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock andl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock andl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock andl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock andl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 21 64       	lock xacquire andl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 21 64       	lock xrelease andl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 39 64    	lock xacquire btcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 39 64    	lock xrelease btcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btrl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btrl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btrl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btrl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 31 64    	lock xacquire btrl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 31 64    	lock xrelease btrl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock btsl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock btsl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock btsl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock btsl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 29 64    	lock xacquire btsl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 29 64    	lock xrelease btsl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 c7 01 64 00 00 00 	xrelease movl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock orl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock orl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock orl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock orl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 09 64       	lock xacquire orl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 09 64       	lock xrelease orl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbbl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbbl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbbl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbbl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 19 64       	lock xacquire sbbl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 19 64       	lock xrelease sbbl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock subl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock subl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock subl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock subl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 29 64       	lock xacquire subl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 29 64       	lock xrelease subl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xorl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xorl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xorl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xorl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 31 64       	lock xacquire xorl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 31 64       	lock xrelease xorl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease movb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 10 01          	lock xacquire adc %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 10 01          	lock xrelease adc %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 00 01          	lock xacquire add %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 00 01          	lock xrelease add %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 20 01          	lock xacquire and %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 20 01          	lock xrelease and %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 88 01             	xrelease mov %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 08 01          	lock xacquire or %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 08 01          	lock xrelease or %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 18 01          	lock xacquire sbb %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 18 01          	lock xrelease sbb %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 28 01          	lock xacquire sub %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 28 01          	lock xrelease sub %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 86 01             	xacquire xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 86 01             	xrelease xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 86 01          	lock xacquire xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 86 01          	lock xrelease xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 30 01          	lock xacquire xor %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 30 01          	lock xrelease xor %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 11 01       	lock xacquire adc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 11 01       	lock xrelease adc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 01 01       	lock xacquire add %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 01 01       	lock xrelease add %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 21 01       	lock xacquire and %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 21 01       	lock xrelease and %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 89 01          	xrelease mov %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 09 01       	lock xacquire or %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 09 01       	lock xrelease or %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 19 01       	lock xacquire sbb %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 19 01       	lock xrelease sbb %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 29 01       	lock xacquire sub %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 29 01       	lock xrelease sub %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 87 01          	xacquire xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 87 01          	xrelease xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 87 01       	lock xacquire xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 87 01       	lock xrelease xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 31 01       	lock xacquire xor %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 31 01       	lock xrelease xor %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 11 01          	lock xacquire adc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 11 01          	lock xrelease adc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 01 01          	lock xacquire add %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 01 01          	lock xrelease add %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 21 01          	lock xacquire and %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 21 01          	lock xrelease and %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 89 01             	xrelease mov %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 09 01          	lock xacquire or %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 09 01          	lock xrelease or %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 19 01          	lock xacquire sbb %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 19 01          	lock xrelease sbb %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 29 01          	lock xacquire sub %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 29 01          	lock xrelease sub %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 87 01             	xacquire xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 87 01             	xrelease xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 87 01          	lock xacquire xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 87 01          	lock xrelease xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 31 01          	lock xacquire xor %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 31 01          	lock xrelease xor %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f bb 01    	lock xacquire btc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f bb 01    	lock xrelease btc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b3 01    	lock xacquire btr %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b3 01    	lock xrelease btr %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ab 01    	lock xacquire bts %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ab 01    	lock xrelease bts %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b1 01    	lock xacquire cmpxchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b1 01    	lock xrelease cmpxchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f c1 01    	lock xacquire xadd %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f c1 01    	lock xrelease xadd %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f bb 01       	lock xacquire btc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f bb 01       	lock xrelease btc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f b3 01       	lock xacquire btr %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f b3 01       	lock xrelease btr %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ab 01       	lock xacquire bts %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ab 01       	lock xrelease bts %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f b1 01       	lock xacquire cmpxchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f b1 01       	lock xrelease cmpxchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f c1 01       	lock xacquire xadd %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f c1 01       	lock xrelease xadd %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock decb \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock decb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock decb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock decb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 fe 09          	lock xacquire decb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 fe 09          	lock xrelease decb \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock incb \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock incb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock incb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock incb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 fe 01          	lock xacquire incb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 fe 01          	lock xrelease incb \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock negb \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock negb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock negb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock negb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 f6 19          	lock xacquire negb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 f6 19          	lock xrelease negb \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock notb \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock notb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock notb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock notb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 f6 11          	lock xacquire notb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 f6 11          	lock xrelease notb \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock decw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock decw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock decw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock decw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 09       	lock xacquire decw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 09       	lock xrelease decw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock incw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock incw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock incw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock incw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 01       	lock xacquire incw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 01       	lock xrelease incw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock negw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock negw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock negw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock negw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 19       	lock xacquire negw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 19       	lock xrelease negw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock notw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock notw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock notw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock notw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 11       	lock xacquire notw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 11       	lock xrelease notw \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock decl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock decl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock decl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock decl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 ff 09          	lock xacquire decl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 ff 09          	lock xrelease decl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock incl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock incl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock incl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock incl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 ff 01          	lock xacquire incl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 ff 01          	lock xrelease incl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock negl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock negl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock negl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock negl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 f7 19          	lock xacquire negl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 f7 19          	lock xrelease negl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock notl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock notl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock notl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock notl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 f7 11          	lock xacquire notl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 f7 11          	lock xrelease notl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f c7 09       	lock xacquire cmpxchg8b \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f c7 09       	lock xrelease cmpxchg8b \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f b0 09       	lock xacquire cmpxchg %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f b0 09       	lock xrelease cmpxchg %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f c0 09       	lock xacquire xadd %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f c0 09       	lock xrelease xadd %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease movb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adcw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adcw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adcw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adcw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 11 e8 03 	lock xacquire adcw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 11 e8 03 	lock xrelease adcw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock addw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock addw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock addw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock addw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 01 e8 03 	lock xacquire addw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 01 e8 03 	lock xrelease addw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock andw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock andw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock andw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock andw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 21 e8 03 	lock xacquire andw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 21 e8 03 	lock xrelease andw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 c7 01 e8 03    	xrelease movw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock orw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock orw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock orw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock orw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 09 e8 03 	lock xacquire orw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 09 e8 03 	lock xrelease orw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbbw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbbw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbbw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbbw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 19 e8 03 	lock xacquire sbbw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 19 e8 03 	lock xrelease sbbw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock subw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock subw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock subw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock subw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 29 e8 03 	lock xacquire subw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 29 e8 03 	lock xrelease subw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xorw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xorw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xorw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xorw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 31 e8 03 	lock xacquire xorw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 31 e8 03 	lock xrelease xorw \$0x3e8,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adcl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adcl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adcl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adcl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 11 80 96 98 00 	lock xacquire adcl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 11 80 96 98 00 	lock xrelease adcl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock addl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock addl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock addl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock addl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 01 80 96 98 00 	lock xacquire addl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 01 80 96 98 00 	lock xrelease addl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock andl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock andl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock andl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock andl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 21 80 96 98 00 	lock xacquire andl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 21 80 96 98 00 	lock xrelease andl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 c7 01 80 96 98 00 	xrelease movl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock orl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock orl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock orl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock orl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 09 80 96 98 00 	lock xacquire orl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 09 80 96 98 00 	lock xrelease orl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbbl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbbl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbbl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbbl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 19 80 96 98 00 	lock xacquire sbbl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 19 80 96 98 00 	lock xrelease sbbl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock subl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock subl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock subl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock subl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 29 80 96 98 00 	lock xacquire subl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 29 80 96 98 00 	lock xrelease subl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xorl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xorl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xorl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xorl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 31 80 96 98 00 	lock xacquire xorl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 31 80 96 98 00 	lock xrelease xorl \$0x989680,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 11 64    	lock xacquire adcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 11 64    	lock xrelease adcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock addw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock addw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock addw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock addw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 01 64    	lock xacquire addw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 01 64    	lock xrelease addw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock andw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock andw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock andw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock andw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 21 64    	lock xacquire andw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 21 64    	lock xrelease andw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 39 64 	lock xacquire btcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 39 64 	lock xrelease btcw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btrw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btrw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btrw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btrw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 31 64 	lock xacquire btrw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 31 64 	lock xrelease btrw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock btsw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock btsw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock btsw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock btsw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 29 64 	lock xacquire btsw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 29 64 	lock xrelease btsw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 c7 01 64 00    	xrelease movw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock orw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock orw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock orw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock orw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 09 64    	lock xacquire orw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 09 64    	lock xrelease orw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbbw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbbw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbbw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbbw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 19 64    	lock xacquire sbbw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 19 64    	lock xrelease sbbw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock subw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock subw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock subw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock subw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 29 64    	lock xacquire subw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 29 64    	lock xrelease subw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xorw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xorw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xorw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xorw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 31 64    	lock xacquire xorw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 31 64    	lock xrelease xorw \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 11 64       	lock xacquire adcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 11 64       	lock xrelease adcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock addl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock addl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock addl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock addl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 01 64       	lock xacquire addl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 01 64       	lock xrelease addl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock andl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock andl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock andl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock andl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 21 64       	lock xacquire andl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 21 64       	lock xrelease andl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 39 64    	lock xacquire btcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 39 64    	lock xrelease btcl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btrl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btrl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btrl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btrl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 31 64    	lock xacquire btrl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 31 64    	lock xrelease btrl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock btsl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock btsl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock btsl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock btsl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 29 64    	lock xacquire btsl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 29 64    	lock xrelease btsl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 c7 01 64 00 00 00 	xrelease movl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock orl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock orl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock orl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock orl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 09 64       	lock xacquire orl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 09 64       	lock xrelease orl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbbl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbbl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbbl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbbl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 19 64       	lock xacquire sbbl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 19 64       	lock xrelease sbbl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock subl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock subl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock subl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock subl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 29 64       	lock xacquire subl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 29 64       	lock xrelease subl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xorl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xorl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xorl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xorl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 31 64       	lock xacquire xorl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 31 64       	lock xrelease xorl \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adcb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease addb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease andb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease movb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease orb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbbb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease subb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xorb \$0x64,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 10 01          	lock xacquire adc %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 10 01          	lock xrelease adc %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 00 01          	lock xacquire add %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 00 01          	lock xrelease add %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 20 01          	lock xacquire and %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 20 01          	lock xrelease and %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 88 01             	xrelease mov %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 08 01          	lock xacquire or %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 08 01          	lock xrelease or %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 18 01          	lock xacquire sbb %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 18 01          	lock xrelease sbb %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 28 01          	lock xacquire sub %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 28 01          	lock xrelease sub %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 86 01             	xacquire xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 86 01             	xrelease xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 86 01          	lock xacquire xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 86 01          	lock xrelease xchg %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 30 01          	lock xacquire xor %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 30 01          	lock xrelease xor %al,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 11 01       	lock xacquire adc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 11 01       	lock xrelease adc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 01 01       	lock xacquire add %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 01 01       	lock xrelease add %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 21 01       	lock xacquire and %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 21 01       	lock xrelease and %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 89 01          	xrelease mov %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 09 01       	lock xacquire or %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 09 01       	lock xrelease or %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 19 01       	lock xacquire sbb %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 19 01       	lock xrelease sbb %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 29 01       	lock xacquire sub %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 29 01       	lock xrelease sub %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 87 01          	xacquire xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 87 01          	xrelease xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 87 01       	lock xacquire xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 87 01       	lock xrelease xchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 31 01       	lock xacquire xor %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 31 01       	lock xrelease xor %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 11 01          	lock xacquire adc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 11 01          	lock xrelease adc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 01 01          	lock xacquire add %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 01 01          	lock xrelease add %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 21 01          	lock xacquire and %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 21 01          	lock xrelease and %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 89 01             	xrelease mov %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 09 01          	lock xacquire or %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 09 01          	lock xrelease or %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 19 01          	lock xacquire sbb %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 19 01          	lock xrelease sbb %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 29 01          	lock xacquire sub %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 29 01          	lock xrelease sub %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 87 01             	xacquire xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 87 01             	xrelease xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 87 01          	lock xacquire xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 87 01          	lock xrelease xchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 31 01          	lock xacquire xor %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 31 01          	lock xrelease xor %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f bb 01    	lock xacquire btc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f bb 01    	lock xrelease btc %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b3 01    	lock xacquire btr %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b3 01    	lock xrelease btr %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ab 01    	lock xacquire bts %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ab 01    	lock xrelease bts %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b1 01    	lock xacquire cmpxchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b1 01    	lock xrelease cmpxchg %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f c1 01    	lock xacquire xadd %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f c1 01    	lock xrelease xadd %ax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f bb 01       	lock xacquire btc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f bb 01       	lock xrelease btc %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f b3 01       	lock xacquire btr %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f b3 01       	lock xrelease btr %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ab 01       	lock xacquire bts %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ab 01       	lock xrelease bts %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f b1 01       	lock xacquire cmpxchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f b1 01       	lock xrelease cmpxchg %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f c1 01       	lock xacquire xadd %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f c1 01       	lock xrelease xadd %eax,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock decb \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock decb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock decb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock decb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 fe 09          	lock xacquire decb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 fe 09          	lock xrelease decb \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock incb \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock incb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock incb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock incb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 fe 01          	lock xacquire incb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 fe 01          	lock xrelease incb \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock negb \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock negb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock negb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock negb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 f6 19          	lock xacquire negb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 f6 19          	lock xrelease negb \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock notb \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock notb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock notb \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock notb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 f6 11          	lock xacquire notb \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 f6 11          	lock xrelease notb \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock decw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock decw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock decw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock decw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 09       	lock xacquire decw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 09       	lock xrelease decw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock incw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock incw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock incw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock incw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 01       	lock xacquire incw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 01       	lock xrelease incw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock negw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock negw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock negw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock negw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 19       	lock xacquire negw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 19       	lock xrelease negw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock notw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock notw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock notw \(%ecx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock notw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 11       	lock xacquire notw \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 11       	lock xrelease notw \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock decl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock decl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock decl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock decl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 ff 09          	lock xacquire decl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 ff 09          	lock xrelease decl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock incl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock incl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock incl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock incl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 ff 01          	lock xacquire incl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 ff 01          	lock xrelease incl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock negl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock negl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock negl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock negl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 f7 19          	lock xacquire negl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 f7 19          	lock xrelease negl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock notl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock notl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock notl \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock notl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 f7 11          	lock xacquire notl \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 f7 11          	lock xrelease notl \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b \(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f c7 09       	lock xacquire cmpxchg8b \(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f c7 09       	lock xrelease cmpxchg8b \(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f b0 09       	lock xacquire cmpxchg %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f b0 09       	lock xrelease cmpxchg %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f c0 09       	lock xacquire xadd %cl,\(%ecx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f c0 09       	lock xrelease xadd %cl,\(%ecx\)
+#pass
diff --git a/gas/testsuite/gas/i386/hle.s b/gas/testsuite/gas/i386/hle.s
new file mode 100644
index 0000000..1fffa9e
--- /dev/null
+++ b/gas/testsuite/gas/i386/hle.s
@@ -0,0 +1,1271 @@
+# Check 32bit HLE instructions
+
+	.allow_index_reg
+	.text
+_start:
+
+# Tests for op imm8 regb/m8
+	xacquire lock adcb $100,(%ecx)
+	lock xacquire adcb $100,(%ecx)
+	xrelease lock adcb $100,(%ecx)
+	lock xrelease adcb $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; adcb $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; adcb $100,(%ecx)
+	xacquire lock addb $100,(%ecx)
+	lock xacquire addb $100,(%ecx)
+	xrelease lock addb $100,(%ecx)
+	lock xrelease addb $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; addb $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; addb $100,(%ecx)
+	xacquire lock andb $100,(%ecx)
+	lock xacquire andb $100,(%ecx)
+	xrelease lock andb $100,(%ecx)
+	lock xrelease andb $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; andb $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; andb $100,(%ecx)
+	xrelease movb $100,(%ecx)
+	xacquire lock orb $100,(%ecx)
+	lock xacquire orb $100,(%ecx)
+	xrelease lock orb $100,(%ecx)
+	lock xrelease orb $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; orb $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; orb $100,(%ecx)
+	xacquire lock sbbb $100,(%ecx)
+	lock xacquire sbbb $100,(%ecx)
+	xrelease lock sbbb $100,(%ecx)
+	lock xrelease sbbb $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; sbbb $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; sbbb $100,(%ecx)
+	xacquire lock subb $100,(%ecx)
+	lock xacquire subb $100,(%ecx)
+	xrelease lock subb $100,(%ecx)
+	lock xrelease subb $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; subb $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; subb $100,(%ecx)
+	xacquire lock xorb $100,(%ecx)
+	lock xacquire xorb $100,(%ecx)
+	xrelease lock xorb $100,(%ecx)
+	lock xrelease xorb $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; xorb $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; xorb $100,(%ecx)
+
+# Tests for op imm16 regs/m16
+	xacquire lock adcw $1000,(%ecx)
+	lock xacquire adcw $1000,(%ecx)
+	xrelease lock adcw $1000,(%ecx)
+	lock xrelease adcw $1000,(%ecx)
+	.byte 0xf0; .byte 0xf2; adcw $1000,(%ecx)
+	.byte 0xf0; .byte 0xf3; adcw $1000,(%ecx)
+	xacquire lock addw $1000,(%ecx)
+	lock xacquire addw $1000,(%ecx)
+	xrelease lock addw $1000,(%ecx)
+	lock xrelease addw $1000,(%ecx)
+	.byte 0xf0; .byte 0xf2; addw $1000,(%ecx)
+	.byte 0xf0; .byte 0xf3; addw $1000,(%ecx)
+	xacquire lock andw $1000,(%ecx)
+	lock xacquire andw $1000,(%ecx)
+	xrelease lock andw $1000,(%ecx)
+	lock xrelease andw $1000,(%ecx)
+	.byte 0xf0; .byte 0xf2; andw $1000,(%ecx)
+	.byte 0xf0; .byte 0xf3; andw $1000,(%ecx)
+	xrelease movw $1000,(%ecx)
+	xacquire lock orw $1000,(%ecx)
+	lock xacquire orw $1000,(%ecx)
+	xrelease lock orw $1000,(%ecx)
+	lock xrelease orw $1000,(%ecx)
+	.byte 0xf0; .byte 0xf2; orw $1000,(%ecx)
+	.byte 0xf0; .byte 0xf3; orw $1000,(%ecx)
+	xacquire lock sbbw $1000,(%ecx)
+	lock xacquire sbbw $1000,(%ecx)
+	xrelease lock sbbw $1000,(%ecx)
+	lock xrelease sbbw $1000,(%ecx)
+	.byte 0xf0; .byte 0xf2; sbbw $1000,(%ecx)
+	.byte 0xf0; .byte 0xf3; sbbw $1000,(%ecx)
+	xacquire lock subw $1000,(%ecx)
+	lock xacquire subw $1000,(%ecx)
+	xrelease lock subw $1000,(%ecx)
+	lock xrelease subw $1000,(%ecx)
+	.byte 0xf0; .byte 0xf2; subw $1000,(%ecx)
+	.byte 0xf0; .byte 0xf3; subw $1000,(%ecx)
+	xacquire lock xorw $1000,(%ecx)
+	lock xacquire xorw $1000,(%ecx)
+	xrelease lock xorw $1000,(%ecx)
+	lock xrelease xorw $1000,(%ecx)
+	.byte 0xf0; .byte 0xf2; xorw $1000,(%ecx)
+	.byte 0xf0; .byte 0xf3; xorw $1000,(%ecx)
+
+# Tests for op imm32 regl/m32
+	xacquire lock adcl $10000000,(%ecx)
+	lock xacquire adcl $10000000,(%ecx)
+	xrelease lock adcl $10000000,(%ecx)
+	lock xrelease adcl $10000000,(%ecx)
+	.byte 0xf0; .byte 0xf2; adcl $10000000,(%ecx)
+	.byte 0xf0; .byte 0xf3; adcl $10000000,(%ecx)
+	xacquire lock addl $10000000,(%ecx)
+	lock xacquire addl $10000000,(%ecx)
+	xrelease lock addl $10000000,(%ecx)
+	lock xrelease addl $10000000,(%ecx)
+	.byte 0xf0; .byte 0xf2; addl $10000000,(%ecx)
+	.byte 0xf0; .byte 0xf3; addl $10000000,(%ecx)
+	xacquire lock andl $10000000,(%ecx)
+	lock xacquire andl $10000000,(%ecx)
+	xrelease lock andl $10000000,(%ecx)
+	lock xrelease andl $10000000,(%ecx)
+	.byte 0xf0; .byte 0xf2; andl $10000000,(%ecx)
+	.byte 0xf0; .byte 0xf3; andl $10000000,(%ecx)
+	xrelease movl $10000000,(%ecx)
+	xacquire lock orl $10000000,(%ecx)
+	lock xacquire orl $10000000,(%ecx)
+	xrelease lock orl $10000000,(%ecx)
+	lock xrelease orl $10000000,(%ecx)
+	.byte 0xf0; .byte 0xf2; orl $10000000,(%ecx)
+	.byte 0xf0; .byte 0xf3; orl $10000000,(%ecx)
+	xacquire lock sbbl $10000000,(%ecx)
+	lock xacquire sbbl $10000000,(%ecx)
+	xrelease lock sbbl $10000000,(%ecx)
+	lock xrelease sbbl $10000000,(%ecx)
+	.byte 0xf0; .byte 0xf2; sbbl $10000000,(%ecx)
+	.byte 0xf0; .byte 0xf3; sbbl $10000000,(%ecx)
+	xacquire lock subl $10000000,(%ecx)
+	lock xacquire subl $10000000,(%ecx)
+	xrelease lock subl $10000000,(%ecx)
+	lock xrelease subl $10000000,(%ecx)
+	.byte 0xf0; .byte 0xf2; subl $10000000,(%ecx)
+	.byte 0xf0; .byte 0xf3; subl $10000000,(%ecx)
+	xacquire lock xorl $10000000,(%ecx)
+	lock xacquire xorl $10000000,(%ecx)
+	xrelease lock xorl $10000000,(%ecx)
+	lock xrelease xorl $10000000,(%ecx)
+	.byte 0xf0; .byte 0xf2; xorl $10000000,(%ecx)
+	.byte 0xf0; .byte 0xf3; xorl $10000000,(%ecx)
+
+# Tests for op imm8 regs/m16
+	xacquire lock adcw $100,(%ecx)
+	lock xacquire adcw $100,(%ecx)
+	xrelease lock adcw $100,(%ecx)
+	lock xrelease adcw $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; adcw $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; adcw $100,(%ecx)
+	xacquire lock addw $100,(%ecx)
+	lock xacquire addw $100,(%ecx)
+	xrelease lock addw $100,(%ecx)
+	lock xrelease addw $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; addw $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; addw $100,(%ecx)
+	xacquire lock andw $100,(%ecx)
+	lock xacquire andw $100,(%ecx)
+	xrelease lock andw $100,(%ecx)
+	lock xrelease andw $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; andw $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; andw $100,(%ecx)
+	xacquire lock btcw $100,(%ecx)
+	lock xacquire btcw $100,(%ecx)
+	xrelease lock btcw $100,(%ecx)
+	lock xrelease btcw $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; btcw $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; btcw $100,(%ecx)
+	xacquire lock btrw $100,(%ecx)
+	lock xacquire btrw $100,(%ecx)
+	xrelease lock btrw $100,(%ecx)
+	lock xrelease btrw $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; btrw $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; btrw $100,(%ecx)
+	xacquire lock btsw $100,(%ecx)
+	lock xacquire btsw $100,(%ecx)
+	xrelease lock btsw $100,(%ecx)
+	lock xrelease btsw $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; btsw $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; btsw $100,(%ecx)
+	xrelease movw $100,(%ecx)
+	xacquire lock orw $100,(%ecx)
+	lock xacquire orw $100,(%ecx)
+	xrelease lock orw $100,(%ecx)
+	lock xrelease orw $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; orw $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; orw $100,(%ecx)
+	xacquire lock sbbw $100,(%ecx)
+	lock xacquire sbbw $100,(%ecx)
+	xrelease lock sbbw $100,(%ecx)
+	lock xrelease sbbw $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; sbbw $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; sbbw $100,(%ecx)
+	xacquire lock subw $100,(%ecx)
+	lock xacquire subw $100,(%ecx)
+	xrelease lock subw $100,(%ecx)
+	lock xrelease subw $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; subw $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; subw $100,(%ecx)
+	xacquire lock xorw $100,(%ecx)
+	lock xacquire xorw $100,(%ecx)
+	xrelease lock xorw $100,(%ecx)
+	lock xrelease xorw $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; xorw $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; xorw $100,(%ecx)
+
+# Tests for op imm8 regl/m32
+	xacquire lock adcl $100,(%ecx)
+	lock xacquire adcl $100,(%ecx)
+	xrelease lock adcl $100,(%ecx)
+	lock xrelease adcl $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; adcl $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; adcl $100,(%ecx)
+	xacquire lock addl $100,(%ecx)
+	lock xacquire addl $100,(%ecx)
+	xrelease lock addl $100,(%ecx)
+	lock xrelease addl $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; addl $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; addl $100,(%ecx)
+	xacquire lock andl $100,(%ecx)
+	lock xacquire andl $100,(%ecx)
+	xrelease lock andl $100,(%ecx)
+	lock xrelease andl $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; andl $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; andl $100,(%ecx)
+	xacquire lock btcl $100,(%ecx)
+	lock xacquire btcl $100,(%ecx)
+	xrelease lock btcl $100,(%ecx)
+	lock xrelease btcl $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; btcl $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; btcl $100,(%ecx)
+	xacquire lock btrl $100,(%ecx)
+	lock xacquire btrl $100,(%ecx)
+	xrelease lock btrl $100,(%ecx)
+	lock xrelease btrl $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; btrl $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; btrl $100,(%ecx)
+	xacquire lock btsl $100,(%ecx)
+	lock xacquire btsl $100,(%ecx)
+	xrelease lock btsl $100,(%ecx)
+	lock xrelease btsl $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; btsl $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; btsl $100,(%ecx)
+	xrelease movl $100,(%ecx)
+	xacquire lock orl $100,(%ecx)
+	lock xacquire orl $100,(%ecx)
+	xrelease lock orl $100,(%ecx)
+	lock xrelease orl $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; orl $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; orl $100,(%ecx)
+	xacquire lock sbbl $100,(%ecx)
+	lock xacquire sbbl $100,(%ecx)
+	xrelease lock sbbl $100,(%ecx)
+	lock xrelease sbbl $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; sbbl $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; sbbl $100,(%ecx)
+	xacquire lock subl $100,(%ecx)
+	lock xacquire subl $100,(%ecx)
+	xrelease lock subl $100,(%ecx)
+	lock xrelease subl $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; subl $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; subl $100,(%ecx)
+	xacquire lock xorl $100,(%ecx)
+	lock xacquire xorl $100,(%ecx)
+	xrelease lock xorl $100,(%ecx)
+	lock xrelease xorl $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; xorl $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; xorl $100,(%ecx)
+
+# Tests for op imm8 regb/m8
+	xacquire lock adcb $100,(%ecx)
+	lock xacquire adcb $100,(%ecx)
+	xrelease lock adcb $100,(%ecx)
+	lock xrelease adcb $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; adcb $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; adcb $100,(%ecx)
+	xacquire lock addb $100,(%ecx)
+	lock xacquire addb $100,(%ecx)
+	xrelease lock addb $100,(%ecx)
+	lock xrelease addb $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; addb $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; addb $100,(%ecx)
+	xacquire lock andb $100,(%ecx)
+	lock xacquire andb $100,(%ecx)
+	xrelease lock andb $100,(%ecx)
+	lock xrelease andb $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; andb $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; andb $100,(%ecx)
+	xrelease movb $100,(%ecx)
+	xacquire lock orb $100,(%ecx)
+	lock xacquire orb $100,(%ecx)
+	xrelease lock orb $100,(%ecx)
+	lock xrelease orb $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; orb $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; orb $100,(%ecx)
+	xacquire lock sbbb $100,(%ecx)
+	lock xacquire sbbb $100,(%ecx)
+	xrelease lock sbbb $100,(%ecx)
+	lock xrelease sbbb $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; sbbb $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; sbbb $100,(%ecx)
+	xacquire lock subb $100,(%ecx)
+	lock xacquire subb $100,(%ecx)
+	xrelease lock subb $100,(%ecx)
+	lock xrelease subb $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; subb $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; subb $100,(%ecx)
+	xacquire lock xorb $100,(%ecx)
+	lock xacquire xorb $100,(%ecx)
+	xrelease lock xorb $100,(%ecx)
+	lock xrelease xorb $100,(%ecx)
+	.byte 0xf0; .byte 0xf2; xorb $100,(%ecx)
+	.byte 0xf0; .byte 0xf3; xorb $100,(%ecx)
+
+# Tests for op regb regb/m8
+# Tests for op regb/m8 regb
+	xacquire lock adcb %al,(%ecx)
+	lock xacquire adcb %al,(%ecx)
+	xrelease lock adcb %al,(%ecx)
+	lock xrelease adcb %al,(%ecx)
+	.byte 0xf0; .byte 0xf2; adcb %al,(%ecx)
+	.byte 0xf0; .byte 0xf3; adcb %al,(%ecx)
+	xacquire lock addb %al,(%ecx)
+	lock xacquire addb %al,(%ecx)
+	xrelease lock addb %al,(%ecx)
+	lock xrelease addb %al,(%ecx)
+	.byte 0xf0; .byte 0xf2; addb %al,(%ecx)
+	.byte 0xf0; .byte 0xf3; addb %al,(%ecx)
+	xacquire lock andb %al,(%ecx)
+	lock xacquire andb %al,(%ecx)
+	xrelease lock andb %al,(%ecx)
+	lock xrelease andb %al,(%ecx)
+	.byte 0xf0; .byte 0xf2; andb %al,(%ecx)
+	.byte 0xf0; .byte 0xf3; andb %al,(%ecx)
+	xrelease movb %al,(%ecx)
+	xacquire lock orb %al,(%ecx)
+	lock xacquire orb %al,(%ecx)
+	xrelease lock orb %al,(%ecx)
+	lock xrelease orb %al,(%ecx)
+	.byte 0xf0; .byte 0xf2; orb %al,(%ecx)
+	.byte 0xf0; .byte 0xf3; orb %al,(%ecx)
+	xacquire lock sbbb %al,(%ecx)
+	lock xacquire sbbb %al,(%ecx)
+	xrelease lock sbbb %al,(%ecx)
+	lock xrelease sbbb %al,(%ecx)
+	.byte 0xf0; .byte 0xf2; sbbb %al,(%ecx)
+	.byte 0xf0; .byte 0xf3; sbbb %al,(%ecx)
+	xacquire lock subb %al,(%ecx)
+	lock xacquire subb %al,(%ecx)
+	xrelease lock subb %al,(%ecx)
+	lock xrelease subb %al,(%ecx)
+	.byte 0xf0; .byte 0xf2; subb %al,(%ecx)
+	.byte 0xf0; .byte 0xf3; subb %al,(%ecx)
+	xacquire lock xchgb %al,(%ecx)
+	lock xacquire xchgb %al,(%ecx)
+	xacquire xchgb %al,(%ecx)
+	xrelease lock xchgb %al,(%ecx)
+	lock xrelease xchgb %al,(%ecx)
+	xrelease xchgb %al,(%ecx)
+	.byte 0xf0; .byte 0xf2; xchgb %al,(%ecx)
+	.byte 0xf0; .byte 0xf3; xchgb %al,(%ecx)
+	xacquire lock xorb %al,(%ecx)
+	lock xacquire xorb %al,(%ecx)
+	xrelease lock xorb %al,(%ecx)
+	lock xrelease xorb %al,(%ecx)
+	.byte 0xf0; .byte 0xf2; xorb %al,(%ecx)
+	.byte 0xf0; .byte 0xf3; xorb %al,(%ecx)
+
+# Tests for op regs regs/m16
+# Tests for op regs/m16 regs
+	xacquire lock adcw %ax,(%ecx)
+	lock xacquire adcw %ax,(%ecx)
+	xrelease lock adcw %ax,(%ecx)
+	lock xrelease adcw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf2; adcw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf3; adcw %ax,(%ecx)
+	xacquire lock addw %ax,(%ecx)
+	lock xacquire addw %ax,(%ecx)
+	xrelease lock addw %ax,(%ecx)
+	lock xrelease addw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf2; addw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf3; addw %ax,(%ecx)
+	xacquire lock andw %ax,(%ecx)
+	lock xacquire andw %ax,(%ecx)
+	xrelease lock andw %ax,(%ecx)
+	lock xrelease andw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf2; andw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf3; andw %ax,(%ecx)
+	xrelease movw %ax,(%ecx)
+	xacquire lock orw %ax,(%ecx)
+	lock xacquire orw %ax,(%ecx)
+	xrelease lock orw %ax,(%ecx)
+	lock xrelease orw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf2; orw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf3; orw %ax,(%ecx)
+	xacquire lock sbbw %ax,(%ecx)
+	lock xacquire sbbw %ax,(%ecx)
+	xrelease lock sbbw %ax,(%ecx)
+	lock xrelease sbbw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf2; sbbw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf3; sbbw %ax,(%ecx)
+	xacquire lock subw %ax,(%ecx)
+	lock xacquire subw %ax,(%ecx)
+	xrelease lock subw %ax,(%ecx)
+	lock xrelease subw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf2; subw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf3; subw %ax,(%ecx)
+	xacquire lock xchgw %ax,(%ecx)
+	lock xacquire xchgw %ax,(%ecx)
+	xacquire xchgw %ax,(%ecx)
+	xrelease lock xchgw %ax,(%ecx)
+	lock xrelease xchgw %ax,(%ecx)
+	xrelease xchgw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf2; xchgw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf3; xchgw %ax,(%ecx)
+	xacquire lock xorw %ax,(%ecx)
+	lock xacquire xorw %ax,(%ecx)
+	xrelease lock xorw %ax,(%ecx)
+	lock xrelease xorw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf2; xorw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf3; xorw %ax,(%ecx)
+
+# Tests for op regl regl/m32
+# Tests for op regl/m32 regl
+	xacquire lock adcl %eax,(%ecx)
+	lock xacquire adcl %eax,(%ecx)
+	xrelease lock adcl %eax,(%ecx)
+	lock xrelease adcl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf2; adcl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf3; adcl %eax,(%ecx)
+	xacquire lock addl %eax,(%ecx)
+	lock xacquire addl %eax,(%ecx)
+	xrelease lock addl %eax,(%ecx)
+	lock xrelease addl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf2; addl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf3; addl %eax,(%ecx)
+	xacquire lock andl %eax,(%ecx)
+	lock xacquire andl %eax,(%ecx)
+	xrelease lock andl %eax,(%ecx)
+	lock xrelease andl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf2; andl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf3; andl %eax,(%ecx)
+	xrelease movl %eax,(%ecx)
+	xacquire lock orl %eax,(%ecx)
+	lock xacquire orl %eax,(%ecx)
+	xrelease lock orl %eax,(%ecx)
+	lock xrelease orl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf2; orl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf3; orl %eax,(%ecx)
+	xacquire lock sbbl %eax,(%ecx)
+	lock xacquire sbbl %eax,(%ecx)
+	xrelease lock sbbl %eax,(%ecx)
+	lock xrelease sbbl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf2; sbbl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf3; sbbl %eax,(%ecx)
+	xacquire lock subl %eax,(%ecx)
+	lock xacquire subl %eax,(%ecx)
+	xrelease lock subl %eax,(%ecx)
+	lock xrelease subl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf2; subl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf3; subl %eax,(%ecx)
+	xacquire lock xchgl %eax,(%ecx)
+	lock xacquire xchgl %eax,(%ecx)
+	xacquire xchgl %eax,(%ecx)
+	xrelease lock xchgl %eax,(%ecx)
+	lock xrelease xchgl %eax,(%ecx)
+	xrelease xchgl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf2; xchgl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf3; xchgl %eax,(%ecx)
+	xacquire lock xorl %eax,(%ecx)
+	lock xacquire xorl %eax,(%ecx)
+	xrelease lock xorl %eax,(%ecx)
+	lock xrelease xorl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf2; xorl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf3; xorl %eax,(%ecx)
+
+# Tests for op regs, regs/m16
+	xacquire lock btcw %ax,(%ecx)
+	lock xacquire btcw %ax,(%ecx)
+	xrelease lock btcw %ax,(%ecx)
+	lock xrelease btcw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf2; btcw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf3; btcw %ax,(%ecx)
+	xacquire lock btrw %ax,(%ecx)
+	lock xacquire btrw %ax,(%ecx)
+	xrelease lock btrw %ax,(%ecx)
+	lock xrelease btrw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf2; btrw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf3; btrw %ax,(%ecx)
+	xacquire lock btsw %ax,(%ecx)
+	lock xacquire btsw %ax,(%ecx)
+	xrelease lock btsw %ax,(%ecx)
+	lock xrelease btsw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf2; btsw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf3; btsw %ax,(%ecx)
+	xacquire lock cmpxchgw %ax,(%ecx)
+	lock xacquire cmpxchgw %ax,(%ecx)
+	xrelease lock cmpxchgw %ax,(%ecx)
+	lock xrelease cmpxchgw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf2; cmpxchgw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf3; cmpxchgw %ax,(%ecx)
+	xacquire lock xaddw %ax,(%ecx)
+	lock xacquire xaddw %ax,(%ecx)
+	xrelease lock xaddw %ax,(%ecx)
+	lock xrelease xaddw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf2; xaddw %ax,(%ecx)
+	.byte 0xf0; .byte 0xf3; xaddw %ax,(%ecx)
+
+# Tests for op regl regl/m32
+	xacquire lock btcl %eax,(%ecx)
+	lock xacquire btcl %eax,(%ecx)
+	xrelease lock btcl %eax,(%ecx)
+	lock xrelease btcl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf2; btcl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf3; btcl %eax,(%ecx)
+	xacquire lock btrl %eax,(%ecx)
+	lock xacquire btrl %eax,(%ecx)
+	xrelease lock btrl %eax,(%ecx)
+	lock xrelease btrl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf2; btrl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf3; btrl %eax,(%ecx)
+	xacquire lock btsl %eax,(%ecx)
+	lock xacquire btsl %eax,(%ecx)
+	xrelease lock btsl %eax,(%ecx)
+	lock xrelease btsl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf2; btsl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf3; btsl %eax,(%ecx)
+	xacquire lock cmpxchgl %eax,(%ecx)
+	lock xacquire cmpxchgl %eax,(%ecx)
+	xrelease lock cmpxchgl %eax,(%ecx)
+	lock xrelease cmpxchgl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf2; cmpxchgl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf3; cmpxchgl %eax,(%ecx)
+	xacquire lock xaddl %eax,(%ecx)
+	lock xacquire xaddl %eax,(%ecx)
+	xrelease lock xaddl %eax,(%ecx)
+	lock xrelease xaddl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf2; xaddl %eax,(%ecx)
+	.byte 0xf0; .byte 0xf3; xaddl %eax,(%ecx)
+
+# Tests for op regb/m8
+	xacquire lock decb (%ecx)
+	lock xacquire decb (%ecx)
+	xrelease lock decb (%ecx)
+	lock xrelease decb (%ecx)
+	.byte 0xf0; .byte 0xf2; decb (%ecx)
+	.byte 0xf0; .byte 0xf3; decb (%ecx)
+	xacquire lock incb (%ecx)
+	lock xacquire incb (%ecx)
+	xrelease lock incb (%ecx)
+	lock xrelease incb (%ecx)
+	.byte 0xf0; .byte 0xf2; incb (%ecx)
+	.byte 0xf0; .byte 0xf3; incb (%ecx)
+	xacquire lock negb (%ecx)
+	lock xacquire negb (%ecx)
+	xrelease lock negb (%ecx)
+	lock xrelease negb (%ecx)
+	.byte 0xf0; .byte 0xf2; negb (%ecx)
+	.byte 0xf0; .byte 0xf3; negb (%ecx)
+	xacquire lock notb (%ecx)
+	lock xacquire notb (%ecx)
+	xrelease lock notb (%ecx)
+	lock xrelease notb (%ecx)
+	.byte 0xf0; .byte 0xf2; notb (%ecx)
+	.byte 0xf0; .byte 0xf3; notb (%ecx)
+
+# Tests for op regs/m16
+	xacquire lock decw (%ecx)
+	lock xacquire decw (%ecx)
+	xrelease lock decw (%ecx)
+	lock xrelease decw (%ecx)
+	.byte 0xf0; .byte 0xf2; decw (%ecx)
+	.byte 0xf0; .byte 0xf3; decw (%ecx)
+	xacquire lock incw (%ecx)
+	lock xacquire incw (%ecx)
+	xrelease lock incw (%ecx)
+	lock xrelease incw (%ecx)
+	.byte 0xf0; .byte 0xf2; incw (%ecx)
+	.byte 0xf0; .byte 0xf3; incw (%ecx)
+	xacquire lock negw (%ecx)
+	lock xacquire negw (%ecx)
+	xrelease lock negw (%ecx)
+	lock xrelease negw (%ecx)
+	.byte 0xf0; .byte 0xf2; negw (%ecx)
+	.byte 0xf0; .byte 0xf3; negw (%ecx)
+	xacquire lock notw (%ecx)
+	lock xacquire notw (%ecx)
+	xrelease lock notw (%ecx)
+	lock xrelease notw (%ecx)
+	.byte 0xf0; .byte 0xf2; notw (%ecx)
+	.byte 0xf0; .byte 0xf3; notw (%ecx)
+
+# Tests for op regl/m32
+	xacquire lock decl (%ecx)
+	lock xacquire decl (%ecx)
+	xrelease lock decl (%ecx)
+	lock xrelease decl (%ecx)
+	.byte 0xf0; .byte 0xf2; decl (%ecx)
+	.byte 0xf0; .byte 0xf3; decl (%ecx)
+	xacquire lock incl (%ecx)
+	lock xacquire incl (%ecx)
+	xrelease lock incl (%ecx)
+	lock xrelease incl (%ecx)
+	.byte 0xf0; .byte 0xf2; incl (%ecx)
+	.byte 0xf0; .byte 0xf3; incl (%ecx)
+	xacquire lock negl (%ecx)
+	lock xacquire negl (%ecx)
+	xrelease lock negl (%ecx)
+	lock xrelease negl (%ecx)
+	.byte 0xf0; .byte 0xf2; negl (%ecx)
+	.byte 0xf0; .byte 0xf3; negl (%ecx)
+	xacquire lock notl (%ecx)
+	lock xacquire notl (%ecx)
+	xrelease lock notl (%ecx)
+	lock xrelease notl (%ecx)
+	.byte 0xf0; .byte 0xf2; notl (%ecx)
+	.byte 0xf0; .byte 0xf3; notl (%ecx)
+
+# Tests for op m64
+	xacquire lock cmpxchg8bq (%ecx)
+	lock xacquire cmpxchg8bq (%ecx)
+	xrelease lock cmpxchg8bq (%ecx)
+	lock xrelease cmpxchg8bq (%ecx)
+	.byte 0xf0; .byte 0xf2; cmpxchg8bq (%ecx)
+	.byte 0xf0; .byte 0xf3; cmpxchg8bq (%ecx)
+
+# Tests for op regb, regb/m8
+	xacquire lock cmpxchgb %cl,(%ecx)
+	lock xacquire cmpxchgb %cl,(%ecx)
+	xrelease lock cmpxchgb %cl,(%ecx)
+	lock xrelease cmpxchgb %cl,(%ecx)
+	.byte 0xf0; .byte 0xf2; cmpxchgb %cl,(%ecx)
+	.byte 0xf0; .byte 0xf3; cmpxchgb %cl,(%ecx)
+	xacquire lock xaddb %cl,(%ecx)
+	lock xacquire xaddb %cl,(%ecx)
+	xrelease lock xaddb %cl,(%ecx)
+	lock xrelease xaddb %cl,(%ecx)
+	.byte 0xf0; .byte 0xf2; xaddb %cl,(%ecx)
+	.byte 0xf0; .byte 0xf3; xaddb %cl,(%ecx)
+
+	.intel_syntax noprefix
+
+# Tests for op imm8 regb/m8
+	xacquire lock adc BYTE PTR [ecx],100
+	lock xacquire adc BYTE PTR [ecx],100
+	xrelease lock adc BYTE PTR [ecx],100
+	lock xrelease adc BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; adc BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; adc BYTE PTR [ecx],100
+	xacquire lock add BYTE PTR [ecx],100
+	lock xacquire add BYTE PTR [ecx],100
+	xrelease lock add BYTE PTR [ecx],100
+	lock xrelease add BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; add BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; add BYTE PTR [ecx],100
+	xacquire lock and BYTE PTR [ecx],100
+	lock xacquire and BYTE PTR [ecx],100
+	xrelease lock and BYTE PTR [ecx],100
+	lock xrelease and BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; and BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; and BYTE PTR [ecx],100
+	xrelease mov BYTE PTR [ecx],100
+	xacquire lock or BYTE PTR [ecx],100
+	lock xacquire or BYTE PTR [ecx],100
+	xrelease lock or BYTE PTR [ecx],100
+	lock xrelease or BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; or BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; or BYTE PTR [ecx],100
+	xacquire lock sbb BYTE PTR [ecx],100
+	lock xacquire sbb BYTE PTR [ecx],100
+	xrelease lock sbb BYTE PTR [ecx],100
+	lock xrelease sbb BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; sbb BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; sbb BYTE PTR [ecx],100
+	xacquire lock sub BYTE PTR [ecx],100
+	lock xacquire sub BYTE PTR [ecx],100
+	xrelease lock sub BYTE PTR [ecx],100
+	lock xrelease sub BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; sub BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; sub BYTE PTR [ecx],100
+	xacquire lock xor BYTE PTR [ecx],100
+	lock xacquire xor BYTE PTR [ecx],100
+	xrelease lock xor BYTE PTR [ecx],100
+	lock xrelease xor BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; xor BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; xor BYTE PTR [ecx],100
+
+# Tests for op imm16 regs/m16
+	xacquire lock adc WORD PTR [ecx],1000
+	lock xacquire adc WORD PTR [ecx],1000
+	xrelease lock adc WORD PTR [ecx],1000
+	lock xrelease adc WORD PTR [ecx],1000
+	.byte 0xf0; .byte 0xf2; adc WORD PTR [ecx],1000
+	.byte 0xf0; .byte 0xf3; adc WORD PTR [ecx],1000
+	xacquire lock add WORD PTR [ecx],1000
+	lock xacquire add WORD PTR [ecx],1000
+	xrelease lock add WORD PTR [ecx],1000
+	lock xrelease add WORD PTR [ecx],1000
+	.byte 0xf0; .byte 0xf2; add WORD PTR [ecx],1000
+	.byte 0xf0; .byte 0xf3; add WORD PTR [ecx],1000
+	xacquire lock and WORD PTR [ecx],1000
+	lock xacquire and WORD PTR [ecx],1000
+	xrelease lock and WORD PTR [ecx],1000
+	lock xrelease and WORD PTR [ecx],1000
+	.byte 0xf0; .byte 0xf2; and WORD PTR [ecx],1000
+	.byte 0xf0; .byte 0xf3; and WORD PTR [ecx],1000
+	xrelease mov WORD PTR [ecx],1000
+	xacquire lock or WORD PTR [ecx],1000
+	lock xacquire or WORD PTR [ecx],1000
+	xrelease lock or WORD PTR [ecx],1000
+	lock xrelease or WORD PTR [ecx],1000
+	.byte 0xf0; .byte 0xf2; or WORD PTR [ecx],1000
+	.byte 0xf0; .byte 0xf3; or WORD PTR [ecx],1000
+	xacquire lock sbb WORD PTR [ecx],1000
+	lock xacquire sbb WORD PTR [ecx],1000
+	xrelease lock sbb WORD PTR [ecx],1000
+	lock xrelease sbb WORD PTR [ecx],1000
+	.byte 0xf0; .byte 0xf2; sbb WORD PTR [ecx],1000
+	.byte 0xf0; .byte 0xf3; sbb WORD PTR [ecx],1000
+	xacquire lock sub WORD PTR [ecx],1000
+	lock xacquire sub WORD PTR [ecx],1000
+	xrelease lock sub WORD PTR [ecx],1000
+	lock xrelease sub WORD PTR [ecx],1000
+	.byte 0xf0; .byte 0xf2; sub WORD PTR [ecx],1000
+	.byte 0xf0; .byte 0xf3; sub WORD PTR [ecx],1000
+	xacquire lock xor WORD PTR [ecx],1000
+	lock xacquire xor WORD PTR [ecx],1000
+	xrelease lock xor WORD PTR [ecx],1000
+	lock xrelease xor WORD PTR [ecx],1000
+	.byte 0xf0; .byte 0xf2; xor WORD PTR [ecx],1000
+	.byte 0xf0; .byte 0xf3; xor WORD PTR [ecx],1000
+
+# Tests for op imm32 regl/m32
+	xacquire lock adc DWORD PTR [ecx],10000000
+	lock xacquire adc DWORD PTR [ecx],10000000
+	xrelease lock adc DWORD PTR [ecx],10000000
+	lock xrelease adc DWORD PTR [ecx],10000000
+	.byte 0xf0; .byte 0xf2; adc DWORD PTR [ecx],10000000
+	.byte 0xf0; .byte 0xf3; adc DWORD PTR [ecx],10000000
+	xacquire lock add DWORD PTR [ecx],10000000
+	lock xacquire add DWORD PTR [ecx],10000000
+	xrelease lock add DWORD PTR [ecx],10000000
+	lock xrelease add DWORD PTR [ecx],10000000
+	.byte 0xf0; .byte 0xf2; add DWORD PTR [ecx],10000000
+	.byte 0xf0; .byte 0xf3; add DWORD PTR [ecx],10000000
+	xacquire lock and DWORD PTR [ecx],10000000
+	lock xacquire and DWORD PTR [ecx],10000000
+	xrelease lock and DWORD PTR [ecx],10000000
+	lock xrelease and DWORD PTR [ecx],10000000
+	.byte 0xf0; .byte 0xf2; and DWORD PTR [ecx],10000000
+	.byte 0xf0; .byte 0xf3; and DWORD PTR [ecx],10000000
+	xrelease mov DWORD PTR [ecx],10000000
+	xacquire lock or DWORD PTR [ecx],10000000
+	lock xacquire or DWORD PTR [ecx],10000000
+	xrelease lock or DWORD PTR [ecx],10000000
+	lock xrelease or DWORD PTR [ecx],10000000
+	.byte 0xf0; .byte 0xf2; or DWORD PTR [ecx],10000000
+	.byte 0xf0; .byte 0xf3; or DWORD PTR [ecx],10000000
+	xacquire lock sbb DWORD PTR [ecx],10000000
+	lock xacquire sbb DWORD PTR [ecx],10000000
+	xrelease lock sbb DWORD PTR [ecx],10000000
+	lock xrelease sbb DWORD PTR [ecx],10000000
+	.byte 0xf0; .byte 0xf2; sbb DWORD PTR [ecx],10000000
+	.byte 0xf0; .byte 0xf3; sbb DWORD PTR [ecx],10000000
+	xacquire lock sub DWORD PTR [ecx],10000000
+	lock xacquire sub DWORD PTR [ecx],10000000
+	xrelease lock sub DWORD PTR [ecx],10000000
+	lock xrelease sub DWORD PTR [ecx],10000000
+	.byte 0xf0; .byte 0xf2; sub DWORD PTR [ecx],10000000
+	.byte 0xf0; .byte 0xf3; sub DWORD PTR [ecx],10000000
+	xacquire lock xor DWORD PTR [ecx],10000000
+	lock xacquire xor DWORD PTR [ecx],10000000
+	xrelease lock xor DWORD PTR [ecx],10000000
+	lock xrelease xor DWORD PTR [ecx],10000000
+	.byte 0xf0; .byte 0xf2; xor DWORD PTR [ecx],10000000
+	.byte 0xf0; .byte 0xf3; xor DWORD PTR [ecx],10000000
+
+# Tests for op imm8 regs/m16
+	xacquire lock adc WORD PTR [ecx],100
+	lock xacquire adc WORD PTR [ecx],100
+	xrelease lock adc WORD PTR [ecx],100
+	lock xrelease adc WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; adc WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; adc WORD PTR [ecx],100
+	xacquire lock add WORD PTR [ecx],100
+	lock xacquire add WORD PTR [ecx],100
+	xrelease lock add WORD PTR [ecx],100
+	lock xrelease add WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; add WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; add WORD PTR [ecx],100
+	xacquire lock and WORD PTR [ecx],100
+	lock xacquire and WORD PTR [ecx],100
+	xrelease lock and WORD PTR [ecx],100
+	lock xrelease and WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; and WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; and WORD PTR [ecx],100
+	xacquire lock btc WORD PTR [ecx],100
+	lock xacquire btc WORD PTR [ecx],100
+	xrelease lock btc WORD PTR [ecx],100
+	lock xrelease btc WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; btc WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; btc WORD PTR [ecx],100
+	xacquire lock btr WORD PTR [ecx],100
+	lock xacquire btr WORD PTR [ecx],100
+	xrelease lock btr WORD PTR [ecx],100
+	lock xrelease btr WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; btr WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; btr WORD PTR [ecx],100
+	xacquire lock bts WORD PTR [ecx],100
+	lock xacquire bts WORD PTR [ecx],100
+	xrelease lock bts WORD PTR [ecx],100
+	lock xrelease bts WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; bts WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; bts WORD PTR [ecx],100
+	xrelease mov WORD PTR [ecx],100
+	xacquire lock or WORD PTR [ecx],100
+	lock xacquire or WORD PTR [ecx],100
+	xrelease lock or WORD PTR [ecx],100
+	lock xrelease or WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; or WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; or WORD PTR [ecx],100
+	xacquire lock sbb WORD PTR [ecx],100
+	lock xacquire sbb WORD PTR [ecx],100
+	xrelease lock sbb WORD PTR [ecx],100
+	lock xrelease sbb WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; sbb WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; sbb WORD PTR [ecx],100
+	xacquire lock sub WORD PTR [ecx],100
+	lock xacquire sub WORD PTR [ecx],100
+	xrelease lock sub WORD PTR [ecx],100
+	lock xrelease sub WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; sub WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; sub WORD PTR [ecx],100
+	xacquire lock xor WORD PTR [ecx],100
+	lock xacquire xor WORD PTR [ecx],100
+	xrelease lock xor WORD PTR [ecx],100
+	lock xrelease xor WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; xor WORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; xor WORD PTR [ecx],100
+
+# Tests for op imm8 regl/m32
+	xacquire lock adc DWORD PTR [ecx],100
+	lock xacquire adc DWORD PTR [ecx],100
+	xrelease lock adc DWORD PTR [ecx],100
+	lock xrelease adc DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; adc DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; adc DWORD PTR [ecx],100
+	xacquire lock add DWORD PTR [ecx],100
+	lock xacquire add DWORD PTR [ecx],100
+	xrelease lock add DWORD PTR [ecx],100
+	lock xrelease add DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; add DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; add DWORD PTR [ecx],100
+	xacquire lock and DWORD PTR [ecx],100
+	lock xacquire and DWORD PTR [ecx],100
+	xrelease lock and DWORD PTR [ecx],100
+	lock xrelease and DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; and DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; and DWORD PTR [ecx],100
+	xacquire lock btc DWORD PTR [ecx],100
+	lock xacquire btc DWORD PTR [ecx],100
+	xrelease lock btc DWORD PTR [ecx],100
+	lock xrelease btc DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; btc DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; btc DWORD PTR [ecx],100
+	xacquire lock btr DWORD PTR [ecx],100
+	lock xacquire btr DWORD PTR [ecx],100
+	xrelease lock btr DWORD PTR [ecx],100
+	lock xrelease btr DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; btr DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; btr DWORD PTR [ecx],100
+	xacquire lock bts DWORD PTR [ecx],100
+	lock xacquire bts DWORD PTR [ecx],100
+	xrelease lock bts DWORD PTR [ecx],100
+	lock xrelease bts DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; bts DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; bts DWORD PTR [ecx],100
+	xrelease mov DWORD PTR [ecx],100
+	xacquire lock or DWORD PTR [ecx],100
+	lock xacquire or DWORD PTR [ecx],100
+	xrelease lock or DWORD PTR [ecx],100
+	lock xrelease or DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; or DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; or DWORD PTR [ecx],100
+	xacquire lock sbb DWORD PTR [ecx],100
+	lock xacquire sbb DWORD PTR [ecx],100
+	xrelease lock sbb DWORD PTR [ecx],100
+	lock xrelease sbb DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; sbb DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; sbb DWORD PTR [ecx],100
+	xacquire lock sub DWORD PTR [ecx],100
+	lock xacquire sub DWORD PTR [ecx],100
+	xrelease lock sub DWORD PTR [ecx],100
+	lock xrelease sub DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; sub DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; sub DWORD PTR [ecx],100
+	xacquire lock xor DWORD PTR [ecx],100
+	lock xacquire xor DWORD PTR [ecx],100
+	xrelease lock xor DWORD PTR [ecx],100
+	lock xrelease xor DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; xor DWORD PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; xor DWORD PTR [ecx],100
+
+# Tests for op imm8 regb/m8
+	xacquire lock adc BYTE PTR [ecx],100
+	lock xacquire adc BYTE PTR [ecx],100
+	xrelease lock adc BYTE PTR [ecx],100
+	lock xrelease adc BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; adc BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; adc BYTE PTR [ecx],100
+	xacquire lock add BYTE PTR [ecx],100
+	lock xacquire add BYTE PTR [ecx],100
+	xrelease lock add BYTE PTR [ecx],100
+	lock xrelease add BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; add BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; add BYTE PTR [ecx],100
+	xacquire lock and BYTE PTR [ecx],100
+	lock xacquire and BYTE PTR [ecx],100
+	xrelease lock and BYTE PTR [ecx],100
+	lock xrelease and BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; and BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; and BYTE PTR [ecx],100
+	xrelease mov BYTE PTR [ecx],100
+	xacquire lock or BYTE PTR [ecx],100
+	lock xacquire or BYTE PTR [ecx],100
+	xrelease lock or BYTE PTR [ecx],100
+	lock xrelease or BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; or BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; or BYTE PTR [ecx],100
+	xacquire lock sbb BYTE PTR [ecx],100
+	lock xacquire sbb BYTE PTR [ecx],100
+	xrelease lock sbb BYTE PTR [ecx],100
+	lock xrelease sbb BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; sbb BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; sbb BYTE PTR [ecx],100
+	xacquire lock sub BYTE PTR [ecx],100
+	lock xacquire sub BYTE PTR [ecx],100
+	xrelease lock sub BYTE PTR [ecx],100
+	lock xrelease sub BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; sub BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; sub BYTE PTR [ecx],100
+	xacquire lock xor BYTE PTR [ecx],100
+	lock xacquire xor BYTE PTR [ecx],100
+	xrelease lock xor BYTE PTR [ecx],100
+	lock xrelease xor BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf2; xor BYTE PTR [ecx],100
+	.byte 0xf0; .byte 0xf3; xor BYTE PTR [ecx],100
+
+# Tests for op regb regb/m8
+# Tests for op regb/m8 regb
+	xacquire lock adc BYTE PTR [ecx],al
+	lock xacquire adc BYTE PTR [ecx],al
+	xrelease lock adc BYTE PTR [ecx],al
+	lock xrelease adc BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf2; adc BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf3; adc BYTE PTR [ecx],al
+	xacquire lock add BYTE PTR [ecx],al
+	lock xacquire add BYTE PTR [ecx],al
+	xrelease lock add BYTE PTR [ecx],al
+	lock xrelease add BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf2; add BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf3; add BYTE PTR [ecx],al
+	xacquire lock and BYTE PTR [ecx],al
+	lock xacquire and BYTE PTR [ecx],al
+	xrelease lock and BYTE PTR [ecx],al
+	lock xrelease and BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf2; and BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf3; and BYTE PTR [ecx],al
+	xrelease mov BYTE PTR [ecx],al
+	xacquire lock or BYTE PTR [ecx],al
+	lock xacquire or BYTE PTR [ecx],al
+	xrelease lock or BYTE PTR [ecx],al
+	lock xrelease or BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf2; or BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf3; or BYTE PTR [ecx],al
+	xacquire lock sbb BYTE PTR [ecx],al
+	lock xacquire sbb BYTE PTR [ecx],al
+	xrelease lock sbb BYTE PTR [ecx],al
+	lock xrelease sbb BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf2; sbb BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf3; sbb BYTE PTR [ecx],al
+	xacquire lock sub BYTE PTR [ecx],al
+	lock xacquire sub BYTE PTR [ecx],al
+	xrelease lock sub BYTE PTR [ecx],al
+	lock xrelease sub BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf2; sub BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf3; sub BYTE PTR [ecx],al
+	xacquire lock xchg BYTE PTR [ecx],al
+	lock xacquire xchg BYTE PTR [ecx],al
+	xacquire xchg BYTE PTR [ecx],al
+	xrelease lock xchg BYTE PTR [ecx],al
+	lock xrelease xchg BYTE PTR [ecx],al
+	xrelease xchg BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf2; xchg BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf3; xchg BYTE PTR [ecx],al
+	xacquire lock xor BYTE PTR [ecx],al
+	lock xacquire xor BYTE PTR [ecx],al
+	xrelease lock xor BYTE PTR [ecx],al
+	lock xrelease xor BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf2; xor BYTE PTR [ecx],al
+	.byte 0xf0; .byte 0xf3; xor BYTE PTR [ecx],al
+
+# Tests for op regs regs/m16
+# Tests for op regs/m16 regs
+	xacquire lock adc WORD PTR [ecx],ax
+	lock xacquire adc WORD PTR [ecx],ax
+	xrelease lock adc WORD PTR [ecx],ax
+	lock xrelease adc WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf2; adc WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf3; adc WORD PTR [ecx],ax
+	xacquire lock add WORD PTR [ecx],ax
+	lock xacquire add WORD PTR [ecx],ax
+	xrelease lock add WORD PTR [ecx],ax
+	lock xrelease add WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf2; add WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf3; add WORD PTR [ecx],ax
+	xacquire lock and WORD PTR [ecx],ax
+	lock xacquire and WORD PTR [ecx],ax
+	xrelease lock and WORD PTR [ecx],ax
+	lock xrelease and WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf2; and WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf3; and WORD PTR [ecx],ax
+	xrelease mov WORD PTR [ecx],ax
+	xacquire lock or WORD PTR [ecx],ax
+	lock xacquire or WORD PTR [ecx],ax
+	xrelease lock or WORD PTR [ecx],ax
+	lock xrelease or WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf2; or WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf3; or WORD PTR [ecx],ax
+	xacquire lock sbb WORD PTR [ecx],ax
+	lock xacquire sbb WORD PTR [ecx],ax
+	xrelease lock sbb WORD PTR [ecx],ax
+	lock xrelease sbb WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf2; sbb WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf3; sbb WORD PTR [ecx],ax
+	xacquire lock sub WORD PTR [ecx],ax
+	lock xacquire sub WORD PTR [ecx],ax
+	xrelease lock sub WORD PTR [ecx],ax
+	lock xrelease sub WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf2; sub WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf3; sub WORD PTR [ecx],ax
+	xacquire lock xchg WORD PTR [ecx],ax
+	lock xacquire xchg WORD PTR [ecx],ax
+	xacquire xchg WORD PTR [ecx],ax
+	xrelease lock xchg WORD PTR [ecx],ax
+	lock xrelease xchg WORD PTR [ecx],ax
+	xrelease xchg WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf2; xchg WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf3; xchg WORD PTR [ecx],ax
+	xacquire lock xor WORD PTR [ecx],ax
+	lock xacquire xor WORD PTR [ecx],ax
+	xrelease lock xor WORD PTR [ecx],ax
+	lock xrelease xor WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf2; xor WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf3; xor WORD PTR [ecx],ax
+
+# Tests for op regl regl/m32
+# Tests for op regl/m32 regl
+	xacquire lock adc DWORD PTR [ecx],eax
+	lock xacquire adc DWORD PTR [ecx],eax
+	xrelease lock adc DWORD PTR [ecx],eax
+	lock xrelease adc DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf2; adc DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf3; adc DWORD PTR [ecx],eax
+	xacquire lock add DWORD PTR [ecx],eax
+	lock xacquire add DWORD PTR [ecx],eax
+	xrelease lock add DWORD PTR [ecx],eax
+	lock xrelease add DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf2; add DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf3; add DWORD PTR [ecx],eax
+	xacquire lock and DWORD PTR [ecx],eax
+	lock xacquire and DWORD PTR [ecx],eax
+	xrelease lock and DWORD PTR [ecx],eax
+	lock xrelease and DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf2; and DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf3; and DWORD PTR [ecx],eax
+	xrelease mov DWORD PTR [ecx],eax
+	xacquire lock or DWORD PTR [ecx],eax
+	lock xacquire or DWORD PTR [ecx],eax
+	xrelease lock or DWORD PTR [ecx],eax
+	lock xrelease or DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf2; or DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf3; or DWORD PTR [ecx],eax
+	xacquire lock sbb DWORD PTR [ecx],eax
+	lock xacquire sbb DWORD PTR [ecx],eax
+	xrelease lock sbb DWORD PTR [ecx],eax
+	lock xrelease sbb DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf2; sbb DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf3; sbb DWORD PTR [ecx],eax
+	xacquire lock sub DWORD PTR [ecx],eax
+	lock xacquire sub DWORD PTR [ecx],eax
+	xrelease lock sub DWORD PTR [ecx],eax
+	lock xrelease sub DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf2; sub DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf3; sub DWORD PTR [ecx],eax
+	xacquire lock xchg DWORD PTR [ecx],eax
+	lock xacquire xchg DWORD PTR [ecx],eax
+	xacquire xchg DWORD PTR [ecx],eax
+	xrelease lock xchg DWORD PTR [ecx],eax
+	lock xrelease xchg DWORD PTR [ecx],eax
+	xrelease xchg DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf2; xchg DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf3; xchg DWORD PTR [ecx],eax
+	xacquire lock xor DWORD PTR [ecx],eax
+	lock xacquire xor DWORD PTR [ecx],eax
+	xrelease lock xor DWORD PTR [ecx],eax
+	lock xrelease xor DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf2; xor DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf3; xor DWORD PTR [ecx],eax
+
+# Tests for op regs, regs/m16
+	xacquire lock btc WORD PTR [ecx],ax
+	lock xacquire btc WORD PTR [ecx],ax
+	xrelease lock btc WORD PTR [ecx],ax
+	lock xrelease btc WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf2; btc WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf3; btc WORD PTR [ecx],ax
+	xacquire lock btr WORD PTR [ecx],ax
+	lock xacquire btr WORD PTR [ecx],ax
+	xrelease lock btr WORD PTR [ecx],ax
+	lock xrelease btr WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf2; btr WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf3; btr WORD PTR [ecx],ax
+	xacquire lock bts WORD PTR [ecx],ax
+	lock xacquire bts WORD PTR [ecx],ax
+	xrelease lock bts WORD PTR [ecx],ax
+	lock xrelease bts WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf2; bts WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf3; bts WORD PTR [ecx],ax
+	xacquire lock cmpxchg WORD PTR [ecx],ax
+	lock xacquire cmpxchg WORD PTR [ecx],ax
+	xrelease lock cmpxchg WORD PTR [ecx],ax
+	lock xrelease cmpxchg WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf2; cmpxchg WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf3; cmpxchg WORD PTR [ecx],ax
+	xacquire lock xadd WORD PTR [ecx],ax
+	lock xacquire xadd WORD PTR [ecx],ax
+	xrelease lock xadd WORD PTR [ecx],ax
+	lock xrelease xadd WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf2; xadd WORD PTR [ecx],ax
+	.byte 0xf0; .byte 0xf3; xadd WORD PTR [ecx],ax
+
+# Tests for op regl regl/m32
+	xacquire lock btc DWORD PTR [ecx],eax
+	lock xacquire btc DWORD PTR [ecx],eax
+	xrelease lock btc DWORD PTR [ecx],eax
+	lock xrelease btc DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf2; btc DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf3; btc DWORD PTR [ecx],eax
+	xacquire lock btr DWORD PTR [ecx],eax
+	lock xacquire btr DWORD PTR [ecx],eax
+	xrelease lock btr DWORD PTR [ecx],eax
+	lock xrelease btr DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf2; btr DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf3; btr DWORD PTR [ecx],eax
+	xacquire lock bts DWORD PTR [ecx],eax
+	lock xacquire bts DWORD PTR [ecx],eax
+	xrelease lock bts DWORD PTR [ecx],eax
+	lock xrelease bts DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf2; bts DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf3; bts DWORD PTR [ecx],eax
+	xacquire lock cmpxchg DWORD PTR [ecx],eax
+	lock xacquire cmpxchg DWORD PTR [ecx],eax
+	xrelease lock cmpxchg DWORD PTR [ecx],eax
+	lock xrelease cmpxchg DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf2; cmpxchg DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf3; cmpxchg DWORD PTR [ecx],eax
+	xacquire lock xadd DWORD PTR [ecx],eax
+	lock xacquire xadd DWORD PTR [ecx],eax
+	xrelease lock xadd DWORD PTR [ecx],eax
+	lock xrelease xadd DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf2; xadd DWORD PTR [ecx],eax
+	.byte 0xf0; .byte 0xf3; xadd DWORD PTR [ecx],eax
+
+# Tests for op regb/m8
+	xacquire lock dec BYTE PTR [ecx]
+	lock xacquire dec BYTE PTR [ecx]
+	xrelease lock dec BYTE PTR [ecx]
+	lock xrelease dec BYTE PTR [ecx]
+	.byte 0xf0; .byte 0xf2; dec BYTE PTR [ecx]
+	.byte 0xf0; .byte 0xf3; dec BYTE PTR [ecx]
+	xacquire lock inc BYTE PTR [ecx]
+	lock xacquire inc BYTE PTR [ecx]
+	xrelease lock inc BYTE PTR [ecx]
+	lock xrelease inc BYTE PTR [ecx]
+	.byte 0xf0; .byte 0xf2; inc BYTE PTR [ecx]
+	.byte 0xf0; .byte 0xf3; inc BYTE PTR [ecx]
+	xacquire lock neg BYTE PTR [ecx]
+	lock xacquire neg BYTE PTR [ecx]
+	xrelease lock neg BYTE PTR [ecx]
+	lock xrelease neg BYTE PTR [ecx]
+	.byte 0xf0; .byte 0xf2; neg BYTE PTR [ecx]
+	.byte 0xf0; .byte 0xf3; neg BYTE PTR [ecx]
+	xacquire lock not BYTE PTR [ecx]
+	lock xacquire not BYTE PTR [ecx]
+	xrelease lock not BYTE PTR [ecx]
+	lock xrelease not BYTE PTR [ecx]
+	.byte 0xf0; .byte 0xf2; not BYTE PTR [ecx]
+	.byte 0xf0; .byte 0xf3; not BYTE PTR [ecx]
+
+# Tests for op regs/m16
+	xacquire lock dec WORD PTR [ecx]
+	lock xacquire dec WORD PTR [ecx]
+	xrelease lock dec WORD PTR [ecx]
+	lock xrelease dec WORD PTR [ecx]
+	.byte 0xf0; .byte 0xf2; dec WORD PTR [ecx]
+	.byte 0xf0; .byte 0xf3; dec WORD PTR [ecx]
+	xacquire lock inc WORD PTR [ecx]
+	lock xacquire inc WORD PTR [ecx]
+	xrelease lock inc WORD PTR [ecx]
+	lock xrelease inc WORD PTR [ecx]
+	.byte 0xf0; .byte 0xf2; inc WORD PTR [ecx]
+	.byte 0xf0; .byte 0xf3; inc WORD PTR [ecx]
+	xacquire lock neg WORD PTR [ecx]
+	lock xacquire neg WORD PTR [ecx]
+	xrelease lock neg WORD PTR [ecx]
+	lock xrelease neg WORD PTR [ecx]
+	.byte 0xf0; .byte 0xf2; neg WORD PTR [ecx]
+	.byte 0xf0; .byte 0xf3; neg WORD PTR [ecx]
+	xacquire lock not WORD PTR [ecx]
+	lock xacquire not WORD PTR [ecx]
+	xrelease lock not WORD PTR [ecx]
+	lock xrelease not WORD PTR [ecx]
+	.byte 0xf0; .byte 0xf2; not WORD PTR [ecx]
+	.byte 0xf0; .byte 0xf3; not WORD PTR [ecx]
+
+# Tests for op regl/m32
+	xacquire lock dec DWORD PTR [ecx]
+	lock xacquire dec DWORD PTR [ecx]
+	xrelease lock dec DWORD PTR [ecx]
+	lock xrelease dec DWORD PTR [ecx]
+	.byte 0xf0; .byte 0xf2; dec DWORD PTR [ecx]
+	.byte 0xf0; .byte 0xf3; dec DWORD PTR [ecx]
+	xacquire lock inc DWORD PTR [ecx]
+	lock xacquire inc DWORD PTR [ecx]
+	xrelease lock inc DWORD PTR [ecx]
+	lock xrelease inc DWORD PTR [ecx]
+	.byte 0xf0; .byte 0xf2; inc DWORD PTR [ecx]
+	.byte 0xf0; .byte 0xf3; inc DWORD PTR [ecx]
+	xacquire lock neg DWORD PTR [ecx]
+	lock xacquire neg DWORD PTR [ecx]
+	xrelease lock neg DWORD PTR [ecx]
+	lock xrelease neg DWORD PTR [ecx]
+	.byte 0xf0; .byte 0xf2; neg DWORD PTR [ecx]
+	.byte 0xf0; .byte 0xf3; neg DWORD PTR [ecx]
+	xacquire lock not DWORD PTR [ecx]
+	lock xacquire not DWORD PTR [ecx]
+	xrelease lock not DWORD PTR [ecx]
+	lock xrelease not DWORD PTR [ecx]
+	.byte 0xf0; .byte 0xf2; not DWORD PTR [ecx]
+	.byte 0xf0; .byte 0xf3; not DWORD PTR [ecx]
+
+# Tests for op m64
+	xacquire lock cmpxchg8b QWORD PTR [ecx]
+	lock xacquire cmpxchg8b QWORD PTR [ecx]
+	xrelease lock cmpxchg8b QWORD PTR [ecx]
+	lock xrelease cmpxchg8b QWORD PTR [ecx]
+	.byte 0xf0; .byte 0xf2; cmpxchg8b QWORD PTR [ecx]
+	.byte 0xf0; .byte 0xf3; cmpxchg8b QWORD PTR [ecx]
+
+# Tests for op regb, regb/m8
+	xacquire lock cmpxchg BYTE PTR [ecx],cl
+	lock xacquire cmpxchg BYTE PTR [ecx],cl
+	xrelease lock cmpxchg BYTE PTR [ecx],cl
+	lock xrelease cmpxchg BYTE PTR [ecx],cl
+	.byte 0xf0; .byte 0xf2; cmpxchg BYTE PTR [ecx],cl
+	.byte 0xf0; .byte 0xf3; cmpxchg BYTE PTR [ecx],cl
+	xacquire lock xadd BYTE PTR [ecx],cl
+	lock xacquire xadd BYTE PTR [ecx],cl
+	xrelease lock xadd BYTE PTR [ecx],cl
+	lock xrelease xadd BYTE PTR [ecx],cl
+	.byte 0xf0; .byte 0xf2; xadd BYTE PTR [ecx],cl
+	.byte 0xf0; .byte 0xf3; xadd BYTE PTR [ecx],cl
diff --git a/gas/testsuite/gas/i386/hlebad.l b/gas/testsuite/gas/i386/hlebad.l
new file mode 100644
index 0000000..7dc7992
--- /dev/null
+++ b/gas/testsuite/gas/i386/hlebad.l
@@ -0,0 +1,818 @@
+.*: Assembler messages:
+.*:8: Error: .*
+.*:9: Error: .*
+.*:10: Error: .*
+.*:11: Error: .*
+.*:12: Error: .*
+.*:13: Error: .*
+.*:16: Error: .*
+.*:17: Error: .*
+.*:18: Error: .*
+.*:19: Error: .*
+.*:20: Error: .*
+.*:21: Error: .*
+.*:24: Error: .*
+.*:25: Error: .*
+.*:26: Error: .*
+.*:27: Error: .*
+.*:28: Error: .*
+.*:29: Error: .*
+.*:32: Error: .*
+.*:33: Error: .*
+.*:34: Error: .*
+.*:35: Error: .*
+.*:36: Error: .*
+.*:37: Error: .*
+.*:38: Error: .*
+.*:39: Error: .*
+.*:42: Error: .*
+.*:43: Error: .*
+.*:44: Error: .*
+.*:45: Error: .*
+.*:46: Error: .*
+.*:47: Error: .*
+.*:48: Error: .*
+.*:49: Error: .*
+.*:52: Error: .*
+.*:53: Error: .*
+.*:54: Error: .*
+.*:55: Error: .*
+.*:56: Error: .*
+.*:57: Error: .*
+.*:58: Error: .*
+.*:59: Error: .*
+.*:62: Error: .*
+.*:63: Error: .*
+.*:64: Error: .*
+.*:65: Error: .*
+.*:66: Error: .*
+.*:67: Error: .*
+.*:68: Error: .*
+.*:69: Error: .*
+.*:72: Error: .*
+.*:73: Error: .*
+.*:74: Error: .*
+.*:75: Error: .*
+.*:76: Error: .*
+.*:77: Error: .*
+.*:78: Error: .*
+.*:79: Error: .*
+.*:82: Error: .*
+.*:83: Error: .*
+.*:84: Error: .*
+.*:85: Error: .*
+.*:86: Error: .*
+.*:87: Error: .*
+.*:88: Error: .*
+.*:89: Error: .*
+.*:93: Error: .*
+.*:94: Error: .*
+.*:95: Error: .*
+.*:96: Error: .*
+.*:97: Error: .*
+.*:98: Error: .*
+.*:99: Error: .*
+.*:100: Error: .*
+.*:101: Error: .*
+.*:102: Error: .*
+.*:103: Error: .*
+.*:104: Error: .*
+.*:105: Error: .*
+.*:106: Error: .*
+.*:107: Error: .*
+.*:108: Error: .*
+.*:109: Error: .*
+.*:110: Error: .*
+.*:111: Error: .*
+.*:112: Error: .*
+.*:116: Error: .*
+.*:117: Error: .*
+.*:118: Error: .*
+.*:119: Error: .*
+.*:120: Error: .*
+.*:121: Error: .*
+.*:122: Error: .*
+.*:123: Error: .*
+.*:124: Error: .*
+.*:125: Error: .*
+.*:126: Error: .*
+.*:127: Error: .*
+.*:128: Error: .*
+.*:129: Error: .*
+.*:130: Error: .*
+.*:131: Error: .*
+.*:132: Error: .*
+.*:133: Error: .*
+.*:134: Error: .*
+.*:135: Error: .*
+.*:139: Error: .*
+.*:140: Error: .*
+.*:141: Error: .*
+.*:142: Error: .*
+.*:143: Error: .*
+.*:144: Error: .*
+.*:145: Error: .*
+.*:146: Error: .*
+.*:147: Error: .*
+.*:148: Error: .*
+.*:149: Error: .*
+.*:150: Error: .*
+.*:151: Error: .*
+.*:152: Error: .*
+.*:153: Error: .*
+.*:154: Error: .*
+.*:155: Error: .*
+.*:156: Error: .*
+.*:157: Error: .*
+.*:158: Error: .*
+.*:161: Error: .*
+.*:162: Error: .*
+.*:163: Error: .*
+.*:164: Error: .*
+.*:165: Error: .*
+.*:166: Error: .*
+.*:167: Error: .*
+.*:168: Error: .*
+.*:171: Error: .*
+.*:172: Error: .*
+.*:173: Error: .*
+.*:174: Error: .*
+.*:175: Error: .*
+.*:176: Error: .*
+.*:177: Error: .*
+.*:178: Error: .*
+.*:181: Error: .*
+.*:182: Error: .*
+.*:183: Error: .*
+.*:184: Error: .*
+.*:185: Error: .*
+.*:186: Error: .*
+.*:187: Error: .*
+.*:188: Error: .*
+.*:191: Error: .*
+.*:192: Error: .*
+.*:193: Error: .*
+.*:194: Error: .*
+.*:195: Error: .*
+.*:196: Error: .*
+.*:197: Error: .*
+.*:198: Error: .*
+.*:201: Error: .*
+.*:202: Error: .*
+.*:203: Error: .*
+.*:204: Error: .*
+.*:205: Error: .*
+.*:206: Error: .*
+.*:207: Error: .*
+.*:208: Error: .*
+.*:211: Error: .*
+.*:212: Error: .*
+.*:215: Error: .*
+.*:216: Error: .*
+.*:217: Error: .*
+.*:218: Error: .*
+.*:219: Error: .*
+.*:220: Error: .*
+.*:221: Error: .*
+.*:222: Error: .*
+.*:227: Error: .*
+.*:228: Error: .*
+.*:229: Error: .*
+.*:230: Error: .*
+.*:231: Error: .*
+.*:232: Error: .*
+.*:235: Error: .*
+.*:236: Error: .*
+.*:237: Error: .*
+.*:238: Error: .*
+.*:239: Error: .*
+.*:240: Error: .*
+.*:243: Error: .*
+.*:244: Error: .*
+.*:245: Error: .*
+.*:246: Error: .*
+.*:247: Error: .*
+.*:248: Error: .*
+.*:251: Error: .*
+.*:252: Error: .*
+.*:253: Error: .*
+.*:254: Error: .*
+.*:255: Error: .*
+.*:256: Error: .*
+.*:257: Error: .*
+.*:258: Error: .*
+.*:261: Error: .*
+.*:262: Error: .*
+.*:263: Error: .*
+.*:264: Error: .*
+.*:265: Error: .*
+.*:266: Error: .*
+.*:267: Error: .*
+.*:268: Error: .*
+.*:271: Error: .*
+.*:272: Error: .*
+.*:273: Error: .*
+.*:274: Error: .*
+.*:275: Error: .*
+.*:276: Error: .*
+.*:277: Error: .*
+.*:278: Error: .*
+.*:281: Error: .*
+.*:282: Error: .*
+.*:283: Error: .*
+.*:284: Error: .*
+.*:285: Error: .*
+.*:286: Error: .*
+.*:287: Error: .*
+.*:288: Error: .*
+.*:291: Error: .*
+.*:292: Error: .*
+.*:293: Error: .*
+.*:294: Error: .*
+.*:295: Error: .*
+.*:296: Error: .*
+.*:297: Error: .*
+.*:298: Error: .*
+.*:301: Error: .*
+.*:302: Error: .*
+.*:303: Error: .*
+.*:304: Error: .*
+.*:305: Error: .*
+.*:306: Error: .*
+.*:307: Error: .*
+.*:308: Error: .*
+.*:312: Error: .*
+.*:313: Error: .*
+.*:314: Error: .*
+.*:315: Error: .*
+.*:316: Error: .*
+.*:317: Error: .*
+.*:318: Error: .*
+.*:319: Error: .*
+.*:320: Error: .*
+.*:321: Error: .*
+.*:322: Error: .*
+.*:323: Error: .*
+.*:324: Error: .*
+.*:325: Error: .*
+.*:326: Error: .*
+.*:327: Error: .*
+.*:328: Error: .*
+.*:329: Error: .*
+.*:330: Error: .*
+.*:331: Error: .*
+.*:335: Error: .*
+.*:336: Error: .*
+.*:337: Error: .*
+.*:338: Error: .*
+.*:339: Error: .*
+.*:340: Error: .*
+.*:341: Error: .*
+.*:342: Error: .*
+.*:343: Error: .*
+.*:344: Error: .*
+.*:345: Error: .*
+.*:346: Error: .*
+.*:347: Error: .*
+.*:348: Error: .*
+.*:349: Error: .*
+.*:350: Error: .*
+.*:351: Error: .*
+.*:352: Error: .*
+.*:353: Error: .*
+.*:354: Error: .*
+.*:358: Error: .*
+.*:359: Error: .*
+.*:360: Error: .*
+.*:361: Error: .*
+.*:362: Error: .*
+.*:363: Error: .*
+.*:364: Error: .*
+.*:365: Error: .*
+.*:366: Error: .*
+.*:367: Error: .*
+.*:368: Error: .*
+.*:369: Error: .*
+.*:370: Error: .*
+.*:371: Error: .*
+.*:372: Error: .*
+.*:373: Error: .*
+.*:374: Error: .*
+.*:375: Error: .*
+.*:376: Error: .*
+.*:377: Error: .*
+.*:380: Error: .*
+.*:381: Error: .*
+.*:382: Error: .*
+.*:383: Error: .*
+.*:384: Error: .*
+.*:385: Error: .*
+.*:386: Error: .*
+.*:387: Error: .*
+.*:390: Error: .*
+.*:391: Error: .*
+.*:392: Error: .*
+.*:393: Error: .*
+.*:394: Error: .*
+.*:395: Error: .*
+.*:396: Error: .*
+.*:397: Error: .*
+.*:400: Error: .*
+.*:401: Error: .*
+.*:402: Error: .*
+.*:403: Error: .*
+.*:404: Error: .*
+.*:405: Error: .*
+.*:406: Error: .*
+.*:407: Error: .*
+.*:410: Error: .*
+.*:411: Error: .*
+.*:412: Error: .*
+.*:413: Error: .*
+.*:414: Error: .*
+.*:415: Error: .*
+.*:416: Error: .*
+.*:417: Error: .*
+.*:420: Error: .*
+.*:421: Error: .*
+.*:422: Error: .*
+.*:423: Error: .*
+.*:424: Error: .*
+.*:425: Error: .*
+.*:426: Error: .*
+.*:427: Error: .*
+.*:430: Error: .*
+.*:431: Error: .*
+.*:434: Error: .*
+.*:435: Error: .*
+.*:436: Error: .*
+.*:437: Error: .*
+.*:438: Error: .*
+.*:439: Error: .*
+.*:440: Error: .*
+.*:441: Error: .*
+GAS LISTING .*
+
+
+[ 	]*1[ 	]+\# Check 32bit unsupported HLE instructions
+[ 	]*2[ 	]+
+[ 	]*3[ 	]+\.allow_index_reg
+[ 	]*4[ 	]+\.text
+[ 	]*5[ 	]+_start:
+[ 	]*6[ 	]+
+[ 	]*7[ 	]+\# Tests for op imm8 al
+[ 	]*8[ 	]+xacquire adc \$100,%al
+[ 	]*9[ 	]+xacquire lock adc \$100,%al
+[ 	]*10[ 	]+lock xacquire adc \$100,%al
+[ 	]*11[ 	]+xrelease adc \$100,%al
+[ 	]*12[ 	]+xrelease lock adc \$100,%al
+[ 	]*13[ 	]+lock xrelease adc \$100,%al
+[ 	]*14[ 	]+
+[ 	]*15[ 	]+\# Tests for op imm16 ax
+[ 	]*16[ 	]+xacquire adc \$1000,%ax
+[ 	]*17[ 	]+xacquire lock adc \$1000,%ax
+[ 	]*18[ 	]+lock xacquire adc \$1000,%ax
+[ 	]*19[ 	]+xrelease adc \$1000,%ax
+[ 	]*20[ 	]+xrelease lock adc \$1000,%ax
+[ 	]*21[ 	]+lock xrelease adc \$1000,%ax
+[ 	]*22[ 	]+
+[ 	]*23[ 	]+\# Tests for op imm32 eax
+[ 	]*24[ 	]+xacquire adc \$10000000,%eax
+[ 	]*25[ 	]+xacquire lock adc \$10000000,%eax
+[ 	]*26[ 	]+lock xacquire adc \$10000000,%eax
+[ 	]*27[ 	]+xrelease adc \$10000000,%eax
+[ 	]*28[ 	]+xrelease lock adc \$10000000,%eax
+[ 	]*29[ 	]+lock xrelease adc \$10000000,%eax
+[ 	]*30[ 	]+
+[ 	]*31[ 	]+\# Tests for op imm8 regb/m8
+[ 	]*32[ 	]+xacquire adcb \$100,%cl
+[ 	]*33[ 	]+xacquire lock adcb \$100,%cl
+[ 	]*34[ 	]+lock xacquire adcb \$100,%cl
+[ 	]*35[ 	]+xrelease adcb \$100,%cl
+[ 	]*36[ 	]+xrelease lock adcb \$100,%cl
+[ 	]*37[ 	]+lock xrelease adcb \$100,%cl
+[ 	]*38[ 	]+xacquire adcb \$100,\(%ecx\)
+[ 	]*39[ 	]+xrelease adcb \$100,\(%ecx\)
+[ 	]*40[ 	]+
+[ 	]*41[ 	]+\# Tests for op imm16 regs/m16
+[ 	]*42[ 	]+xacquire adcw \$1000,%cx
+[ 	]*43[ 	]+xacquire lock adcw \$1000,%cx
+[ 	]*44[ 	]+lock xacquire adcw \$1000,%cx
+[ 	]*45[ 	]+xrelease adcw \$1000,%cx
+[ 	]*46[ 	]+xrelease lock adcw \$1000,%cx
+[ 	]*47[ 	]+lock xrelease adcw \$1000,%cx
+[ 	]*48[ 	]+xacquire adcw \$1000,\(%ecx\)
+[ 	]*49[ 	]+xrelease adcw \$1000,\(%ecx\)
+[ 	]*50[ 	]+
+[ 	]*51[ 	]+\# Tests for op imm32 regl/m32
+[ 	]*52[ 	]+xacquire adcl \$10000000,%ecx
+[ 	]*53[ 	]+xacquire lock adcl \$10000000,%ecx
+[ 	]*54[ 	]+lock xacquire adcl \$10000000,%ecx
+[ 	]*55[ 	]+xrelease adcl \$10000000,%ecx
+[ 	]*56[ 	]+xrelease lock adcl \$10000000,%ecx
+[ 	]*57[ 	]+lock xrelease adcl \$10000000,%ecx
+GAS LISTING .*
+
+
+[ 	]*58[ 	]+xacquire adcl \$10000000,\(%ecx\)
+[ 	]*59[ 	]+xrelease adcl \$10000000,\(%ecx\)
+[ 	]*60[ 	]+
+[ 	]*61[ 	]+\# Tests for op imm8 regs/m16
+[ 	]*62[ 	]+xacquire adcw \$100,%cx
+[ 	]*63[ 	]+xacquire lock adcw \$100,%cx
+[ 	]*64[ 	]+lock xacquire adcw \$100,%cx
+[ 	]*65[ 	]+xrelease adcw \$100,%cx
+[ 	]*66[ 	]+xrelease lock adcw \$100,%cx
+[ 	]*67[ 	]+lock xrelease adcw \$100,%cx
+[ 	]*68[ 	]+xacquire adcw \$100,\(%ecx\)
+[ 	]*69[ 	]+xrelease adcw \$100,\(%ecx\)
+[ 	]*70[ 	]+
+[ 	]*71[ 	]+\# Tests for op imm8 regl/m32
+[ 	]*72[ 	]+xacquire adcl \$100,%ecx
+[ 	]*73[ 	]+xacquire lock adcl \$100,%ecx
+[ 	]*74[ 	]+lock xacquire adcl \$100,%ecx
+[ 	]*75[ 	]+xrelease adcl \$100,%ecx
+[ 	]*76[ 	]+xrelease lock adcl \$100,%ecx
+[ 	]*77[ 	]+lock xrelease adcl \$100,%ecx
+[ 	]*78[ 	]+xacquire adcl \$100,\(%ecx\)
+[ 	]*79[ 	]+xrelease adcl \$100,\(%ecx\)
+[ 	]*80[ 	]+
+[ 	]*81[ 	]+\# Tests for op imm8 regb/m8
+[ 	]*82[ 	]+xacquire adcb \$100,%cl
+[ 	]*83[ 	]+xacquire lock adcb \$100,%cl
+[ 	]*84[ 	]+lock xacquire adcb \$100,%cl
+[ 	]*85[ 	]+xrelease adcb \$100,%cl
+[ 	]*86[ 	]+xrelease lock adcb \$100,%cl
+[ 	]*87[ 	]+lock xrelease adcb \$100,%cl
+[ 	]*88[ 	]+xacquire adcb \$100,\(%ecx\)
+[ 	]*89[ 	]+xrelease adcb \$100,\(%ecx\)
+[ 	]*90[ 	]+
+[ 	]*91[ 	]+\# Tests for op regb regb/m8
+[ 	]*92[ 	]+\# Tests for op regb/m8 regb
+[ 	]*93[ 	]+xacquire adcb %al,%cl
+[ 	]*94[ 	]+xacquire lock adcb %al,%cl
+[ 	]*95[ 	]+lock xacquire adcb %al,%cl
+[ 	]*96[ 	]+xrelease adcb %al,%cl
+[ 	]*97[ 	]+xrelease lock adcb %al,%cl
+[ 	]*98[ 	]+lock xrelease adcb %al,%cl
+[ 	]*99[ 	]+xacquire adcb %al,\(%ecx\)
+[ 	]*100[ 	]+xrelease adcb %al,\(%ecx\)
+[ 	]*101[ 	]+xacquire adcb %cl,%al
+[ 	]*102[ 	]+xacquire lock adcb %cl,%al
+[ 	]*103[ 	]+lock xacquire adcb %cl,%al
+[ 	]*104[ 	]+xrelease adcb %cl,%al
+[ 	]*105[ 	]+xrelease lock adcb %cl,%al
+[ 	]*106[ 	]+lock xrelease adcb %cl,%al
+[ 	]*107[ 	]+xacquire adcb \(%ecx\),%al
+[ 	]*108[ 	]+xacquire lock adcb \(%ecx\),%al
+[ 	]*109[ 	]+lock xacquire adcb \(%ecx\),%al
+[ 	]*110[ 	]+xrelease adcb \(%ecx\),%al
+[ 	]*111[ 	]+xrelease lock adcb \(%ecx\),%al
+[ 	]*112[ 	]+lock xrelease adcb \(%ecx\),%al
+[ 	]*113[ 	]+
+[ 	]*114[ 	]+\# Tests for op regs regs/m16
+GAS LISTING .*
+
+
+[ 	]*115[ 	]+\# Tests for op regs/m16 regs
+[ 	]*116[ 	]+xacquire adcw %ax,%cx
+[ 	]*117[ 	]+xacquire lock adcw %ax,%cx
+[ 	]*118[ 	]+lock xacquire adcw %ax,%cx
+[ 	]*119[ 	]+xrelease adcw %ax,%cx
+[ 	]*120[ 	]+xrelease lock adcw %ax,%cx
+[ 	]*121[ 	]+lock xrelease adcw %ax,%cx
+[ 	]*122[ 	]+xacquire adcw %ax,\(%ecx\)
+[ 	]*123[ 	]+xrelease adcw %ax,\(%ecx\)
+[ 	]*124[ 	]+xacquire adcw %cx,%ax
+[ 	]*125[ 	]+xacquire lock adcw %cx,%ax
+[ 	]*126[ 	]+lock xacquire adcw %cx,%ax
+[ 	]*127[ 	]+xrelease adcw %cx,%ax
+[ 	]*128[ 	]+xrelease lock adcw %cx,%ax
+[ 	]*129[ 	]+lock xrelease adcw %cx,%ax
+[ 	]*130[ 	]+xacquire adcw \(%ecx\),%ax
+[ 	]*131[ 	]+xacquire lock adcw \(%ecx\),%ax
+[ 	]*132[ 	]+lock xacquire adcw \(%ecx\),%ax
+[ 	]*133[ 	]+xrelease adcw \(%ecx\),%ax
+[ 	]*134[ 	]+xrelease lock adcw \(%ecx\),%ax
+[ 	]*135[ 	]+lock xrelease adcw \(%ecx\),%ax
+[ 	]*136[ 	]+
+[ 	]*137[ 	]+\# Tests for op regl regl/m32
+[ 	]*138[ 	]+\# Tests for op regl/m32 regl
+[ 	]*139[ 	]+xacquire adcl %eax,%ecx
+[ 	]*140[ 	]+xacquire lock adcl %eax,%ecx
+[ 	]*141[ 	]+lock xacquire adcl %eax,%ecx
+[ 	]*142[ 	]+xrelease adcl %eax,%ecx
+[ 	]*143[ 	]+xrelease lock adcl %eax,%ecx
+[ 	]*144[ 	]+lock xrelease adcl %eax,%ecx
+[ 	]*145[ 	]+xacquire adcl %eax,\(%ecx\)
+[ 	]*146[ 	]+xrelease adcl %eax,\(%ecx\)
+[ 	]*147[ 	]+xacquire adcl %ecx,%eax
+[ 	]*148[ 	]+xacquire lock adcl %ecx,%eax
+[ 	]*149[ 	]+lock xacquire adcl %ecx,%eax
+[ 	]*150[ 	]+xrelease adcl %ecx,%eax
+[ 	]*151[ 	]+xrelease lock adcl %ecx,%eax
+[ 	]*152[ 	]+lock xrelease adcl %ecx,%eax
+[ 	]*153[ 	]+xacquire adcl \(%ecx\),%eax
+[ 	]*154[ 	]+xacquire lock adcl \(%ecx\),%eax
+[ 	]*155[ 	]+lock xacquire adcl \(%ecx\),%eax
+[ 	]*156[ 	]+xrelease adcl \(%ecx\),%eax
+[ 	]*157[ 	]+xrelease lock adcl \(%ecx\),%eax
+[ 	]*158[ 	]+lock xrelease adcl \(%ecx\),%eax
+[ 	]*159[ 	]+
+[ 	]*160[ 	]+\# Tests for op regs, regs/m16
+[ 	]*161[ 	]+xacquire btcw %ax,%cx
+[ 	]*162[ 	]+xacquire lock btcw %ax,%cx
+[ 	]*163[ 	]+lock xacquire btcw %ax,%cx
+[ 	]*164[ 	]+xrelease btcw %ax,%cx
+[ 	]*165[ 	]+xrelease lock btcw %ax,%cx
+[ 	]*166[ 	]+lock xrelease btcw %ax,%cx
+[ 	]*167[ 	]+xacquire btcw %ax,\(%ecx\)
+[ 	]*168[ 	]+xrelease btcw %ax,\(%ecx\)
+[ 	]*169[ 	]+
+[ 	]*170[ 	]+\# Tests for op regl regl/m32
+[ 	]*171[ 	]+xacquire btcl %eax,%ecx
+GAS LISTING .*
+
+
+[ 	]*172[ 	]+xacquire lock btcl %eax,%ecx
+[ 	]*173[ 	]+lock xacquire btcl %eax,%ecx
+[ 	]*174[ 	]+xrelease btcl %eax,%ecx
+[ 	]*175[ 	]+xrelease lock btcl %eax,%ecx
+[ 	]*176[ 	]+lock xrelease btcl %eax,%ecx
+[ 	]*177[ 	]+xacquire btcl %eax,\(%ecx\)
+[ 	]*178[ 	]+xrelease btcl %eax,\(%ecx\)
+[ 	]*179[ 	]+
+[ 	]*180[ 	]+\# Tests for op regb/m8
+[ 	]*181[ 	]+xacquire decb %cl
+[ 	]*182[ 	]+xacquire lock decb %cl
+[ 	]*183[ 	]+lock xacquire decb %cl
+[ 	]*184[ 	]+xrelease decb %cl
+[ 	]*185[ 	]+xrelease lock decb %cl
+[ 	]*186[ 	]+lock xrelease decb %cl
+[ 	]*187[ 	]+xacquire decb \(%ecx\)
+[ 	]*188[ 	]+xrelease decb \(%ecx\)
+[ 	]*189[ 	]+
+[ 	]*190[ 	]+\# Tests for op regs/m16
+[ 	]*191[ 	]+xacquire decw %cx
+[ 	]*192[ 	]+xacquire lock decw %cx
+[ 	]*193[ 	]+lock xacquire decw %cx
+[ 	]*194[ 	]+xrelease decw %cx
+[ 	]*195[ 	]+xrelease lock decw %cx
+[ 	]*196[ 	]+lock xrelease decw %cx
+[ 	]*197[ 	]+xacquire decw \(%ecx\)
+[ 	]*198[ 	]+xrelease decw \(%ecx\)
+[ 	]*199[ 	]+
+[ 	]*200[ 	]+\# Tests for op regl/m32
+[ 	]*201[ 	]+xacquire decl %ecx
+[ 	]*202[ 	]+xacquire lock decl %ecx
+[ 	]*203[ 	]+lock xacquire decl %ecx
+[ 	]*204[ 	]+xrelease decl %ecx
+[ 	]*205[ 	]+xrelease lock decl %ecx
+[ 	]*206[ 	]+lock xrelease decl %ecx
+[ 	]*207[ 	]+xacquire decl \(%ecx\)
+[ 	]*208[ 	]+xrelease decl \(%ecx\)
+[ 	]*209[ 	]+
+[ 	]*210[ 	]+\# Tests for op m64
+[ 	]*211[ 	]+xacquire cmpxchg8bq \(%ecx\)
+[ 	]*212[ 	]+xrelease cmpxchg8bq \(%ecx\)
+[ 	]*213[ 	]+
+[ 	]*214[ 	]+\# Tests for op regb, regb/m8
+[ 	]*215[ 	]+xacquire cmpxchgb %cl,%al
+[ 	]*216[ 	]+xacquire lock cmpxchgb %cl,%al
+[ 	]*217[ 	]+lock xacquire cmpxchgb %cl,%al
+[ 	]*218[ 	]+xrelease cmpxchgb %cl,%al
+[ 	]*219[ 	]+xrelease lock cmpxchgb %cl,%al
+[ 	]*220[ 	]+lock xrelease cmpxchgb %cl,%al
+[ 	]*221[ 	]+xacquire cmpxchgb %cl,\(%ecx\)
+[ 	]*222[ 	]+xrelease cmpxchgb %cl,\(%ecx\)
+[ 	]*223[ 	]+
+[ 	]*224[ 	]+\.intel_syntax noprefix
+[ 	]*225[ 	]+
+[ 	]*226[ 	]+\# Tests for op imm8 al
+[ 	]*227[ 	]+xacquire adc al,100
+[ 	]*228[ 	]+xacquire lock adc al,100
+GAS LISTING .*
+
+
+[ 	]*229[ 	]+lock xacquire adc al,100
+[ 	]*230[ 	]+xrelease adc al,100
+[ 	]*231[ 	]+xrelease lock adc al,100
+[ 	]*232[ 	]+lock xrelease adc al,100
+[ 	]*233[ 	]+
+[ 	]*234[ 	]+\# Tests for op imm16 ax
+[ 	]*235[ 	]+xacquire adc ax,1000
+[ 	]*236[ 	]+xacquire lock adc ax,1000
+[ 	]*237[ 	]+lock xacquire adc ax,1000
+[ 	]*238[ 	]+xrelease adc ax,1000
+[ 	]*239[ 	]+xrelease lock adc ax,1000
+[ 	]*240[ 	]+lock xrelease adc ax,1000
+[ 	]*241[ 	]+
+[ 	]*242[ 	]+\# Tests for op imm32 eax
+[ 	]*243[ 	]+xacquire adc eax,10000000
+[ 	]*244[ 	]+xacquire lock adc eax,10000000
+[ 	]*245[ 	]+lock xacquire adc eax,10000000
+[ 	]*246[ 	]+xrelease adc eax,10000000
+[ 	]*247[ 	]+xrelease lock adc eax,10000000
+[ 	]*248[ 	]+lock xrelease adc eax,10000000
+[ 	]*249[ 	]+
+[ 	]*250[ 	]+\# Tests for op imm8 regb/m8
+[ 	]*251[ 	]+xacquire adc cl,100
+[ 	]*252[ 	]+xacquire lock adc cl,100
+[ 	]*253[ 	]+lock xacquire adc cl,100
+[ 	]*254[ 	]+xrelease adc cl,100
+[ 	]*255[ 	]+xrelease lock adc cl,100
+[ 	]*256[ 	]+lock xrelease adc cl,100
+[ 	]*257[ 	]+xacquire adc BYTE PTR \[ecx\],100
+[ 	]*258[ 	]+xrelease adc BYTE PTR \[ecx\],100
+[ 	]*259[ 	]+
+[ 	]*260[ 	]+\# Tests for op imm16 regs/m16
+[ 	]*261[ 	]+xacquire adc cx,1000
+[ 	]*262[ 	]+xacquire lock adc cx,1000
+[ 	]*263[ 	]+lock xacquire adc cx,1000
+[ 	]*264[ 	]+xrelease adc cx,1000
+[ 	]*265[ 	]+xrelease lock adc cx,1000
+[ 	]*266[ 	]+lock xrelease adc cx,1000
+[ 	]*267[ 	]+xacquire adc WORD PTR \[ecx\],1000
+[ 	]*268[ 	]+xrelease adc WORD PTR \[ecx\],1000
+[ 	]*269[ 	]+
+[ 	]*270[ 	]+\# Tests for op imm32 regl/m32
+[ 	]*271[ 	]+xacquire adc ecx,10000000
+[ 	]*272[ 	]+xacquire lock adc ecx,10000000
+[ 	]*273[ 	]+lock xacquire adc ecx,10000000
+[ 	]*274[ 	]+xrelease adc ecx,10000000
+[ 	]*275[ 	]+xrelease lock adc ecx,10000000
+[ 	]*276[ 	]+lock xrelease adc ecx,10000000
+[ 	]*277[ 	]+xacquire adc DWORD PTR \[ecx\],10000000
+[ 	]*278[ 	]+xrelease adc DWORD PTR \[ecx\],10000000
+[ 	]*279[ 	]+
+[ 	]*280[ 	]+\# Tests for op imm8 regs/m16
+[ 	]*281[ 	]+xacquire adc cx,100
+[ 	]*282[ 	]+xacquire lock adc cx,100
+[ 	]*283[ 	]+lock xacquire adc cx,100
+[ 	]*284[ 	]+xrelease adc cx,100
+[ 	]*285[ 	]+xrelease lock adc cx,100
+GAS LISTING .*
+
+
+[ 	]*286[ 	]+lock xrelease adc cx,100
+[ 	]*287[ 	]+xacquire adc WORD PTR \[ecx\],100
+[ 	]*288[ 	]+xrelease adc WORD PTR \[ecx\],100
+[ 	]*289[ 	]+
+[ 	]*290[ 	]+\# Tests for op imm8 regl/m32
+[ 	]*291[ 	]+xacquire adc ecx,100
+[ 	]*292[ 	]+xacquire lock adc ecx,100
+[ 	]*293[ 	]+lock xacquire adc ecx,100
+[ 	]*294[ 	]+xrelease adc ecx,100
+[ 	]*295[ 	]+xrelease lock adc ecx,100
+[ 	]*296[ 	]+lock xrelease adc ecx,100
+[ 	]*297[ 	]+xacquire adc DWORD PTR \[ecx\],100
+[ 	]*298[ 	]+xrelease adc DWORD PTR \[ecx\],100
+[ 	]*299[ 	]+
+[ 	]*300[ 	]+\# Tests for op imm8 regb/m8
+[ 	]*301[ 	]+xacquire adc cl,100
+[ 	]*302[ 	]+xacquire lock adc cl,100
+[ 	]*303[ 	]+lock xacquire adc cl,100
+[ 	]*304[ 	]+xrelease adc cl,100
+[ 	]*305[ 	]+xrelease lock adc cl,100
+[ 	]*306[ 	]+lock xrelease adc cl,100
+[ 	]*307[ 	]+xacquire adc BYTE PTR \[ecx\],100
+[ 	]*308[ 	]+xrelease adc BYTE PTR \[ecx\],100
+[ 	]*309[ 	]+
+[ 	]*310[ 	]+\# Tests for op regb regb/m8
+[ 	]*311[ 	]+\# Tests for op regb/m8 regb
+[ 	]*312[ 	]+xacquire adc cl,al
+[ 	]*313[ 	]+xacquire lock adc cl,al
+[ 	]*314[ 	]+lock xacquire adc cl,al
+[ 	]*315[ 	]+xrelease adc cl,al
+[ 	]*316[ 	]+xrelease lock adc cl,al
+[ 	]*317[ 	]+lock xrelease adc cl,al
+[ 	]*318[ 	]+xacquire adc BYTE PTR \[ecx\],al
+[ 	]*319[ 	]+xrelease adc BYTE PTR \[ecx\],al
+[ 	]*320[ 	]+xacquire adc al,cl
+[ 	]*321[ 	]+xacquire lock adc al,cl
+[ 	]*322[ 	]+lock xacquire adc al,cl
+[ 	]*323[ 	]+xrelease adc al,cl
+[ 	]*324[ 	]+xrelease lock adc al,cl
+[ 	]*325[ 	]+lock xrelease adc al,cl
+[ 	]*326[ 	]+xacquire adc al,BYTE PTR \[ecx\]
+[ 	]*327[ 	]+xacquire lock adc al,BYTE PTR \[ecx\]
+[ 	]*328[ 	]+lock xacquire adc al,BYTE PTR \[ecx\]
+[ 	]*329[ 	]+xrelease adc al,BYTE PTR \[ecx\]
+[ 	]*330[ 	]+xrelease lock adc al,BYTE PTR \[ecx\]
+[ 	]*331[ 	]+lock xrelease adc al,BYTE PTR \[ecx\]
+[ 	]*332[ 	]+
+[ 	]*333[ 	]+\# Tests for op regs regs/m16
+[ 	]*334[ 	]+\# Tests for op regs/m16 regs
+[ 	]*335[ 	]+xacquire adc cx,ax
+[ 	]*336[ 	]+xacquire lock adc cx,ax
+[ 	]*337[ 	]+lock xacquire adc cx,ax
+[ 	]*338[ 	]+xrelease adc cx,ax
+[ 	]*339[ 	]+xrelease lock adc cx,ax
+[ 	]*340[ 	]+lock xrelease adc cx,ax
+[ 	]*341[ 	]+xacquire adc WORD PTR \[ecx\],ax
+[ 	]*342[ 	]+xrelease adc WORD PTR \[ecx\],ax
+GAS LISTING .*
+
+
+[ 	]*343[ 	]+xacquire adc ax,cx
+[ 	]*344[ 	]+xacquire lock adc ax,cx
+[ 	]*345[ 	]+lock xacquire adc ax,cx
+[ 	]*346[ 	]+xrelease adc ax,cx
+[ 	]*347[ 	]+xrelease lock adc ax,cx
+[ 	]*348[ 	]+lock xrelease adc ax,cx
+[ 	]*349[ 	]+xacquire adc ax,WORD PTR \[ecx\]
+[ 	]*350[ 	]+xacquire lock adc ax,WORD PTR \[ecx\]
+[ 	]*351[ 	]+lock xacquire adc ax,WORD PTR \[ecx\]
+[ 	]*352[ 	]+xrelease adc ax,WORD PTR \[ecx\]
+[ 	]*353[ 	]+xrelease lock adc ax,WORD PTR \[ecx\]
+[ 	]*354[ 	]+lock xrelease adc ax,WORD PTR \[ecx\]
+[ 	]*355[ 	]+
+[ 	]*356[ 	]+\# Tests for op regl regl/m32
+[ 	]*357[ 	]+\# Tests for op regl/m32 regl
+[ 	]*358[ 	]+xacquire adc ecx,eax
+[ 	]*359[ 	]+xacquire lock adc ecx,eax
+[ 	]*360[ 	]+lock xacquire adc ecx,eax
+[ 	]*361[ 	]+xrelease adc ecx,eax
+[ 	]*362[ 	]+xrelease lock adc ecx,eax
+[ 	]*363[ 	]+lock xrelease adc ecx,eax
+[ 	]*364[ 	]+xacquire adc DWORD PTR \[ecx\],eax
+[ 	]*365[ 	]+xrelease adc DWORD PTR \[ecx\],eax
+[ 	]*366[ 	]+xacquire adc eax,ecx
+[ 	]*367[ 	]+xacquire lock adc eax,ecx
+[ 	]*368[ 	]+lock xacquire adc eax,ecx
+[ 	]*369[ 	]+xrelease adc eax,ecx
+[ 	]*370[ 	]+xrelease lock adc eax,ecx
+[ 	]*371[ 	]+lock xrelease adc eax,ecx
+[ 	]*372[ 	]+xacquire adc eax,DWORD PTR \[ecx\]
+[ 	]*373[ 	]+xacquire lock adc eax,DWORD PTR \[ecx\]
+[ 	]*374[ 	]+lock xacquire adc eax,DWORD PTR \[ecx\]
+[ 	]*375[ 	]+xrelease adc eax,DWORD PTR \[ecx\]
+[ 	]*376[ 	]+xrelease lock adc eax,DWORD PTR \[ecx\]
+[ 	]*377[ 	]+lock xrelease adc eax,DWORD PTR \[ecx\]
+[ 	]*378[ 	]+
+[ 	]*379[ 	]+\# Tests for op regs, regs/m16
+[ 	]*380[ 	]+xacquire btc cx,ax
+[ 	]*381[ 	]+xacquire lock btc cx,ax
+[ 	]*382[ 	]+lock xacquire btc cx,ax
+[ 	]*383[ 	]+xrelease btc cx,ax
+[ 	]*384[ 	]+xrelease lock btc cx,ax
+[ 	]*385[ 	]+lock xrelease btc cx,ax
+[ 	]*386[ 	]+xacquire btc WORD PTR \[ecx\],ax
+[ 	]*387[ 	]+xrelease btc WORD PTR \[ecx\],ax
+[ 	]*388[ 	]+
+[ 	]*389[ 	]+\# Tests for op regl regl/m32
+[ 	]*390[ 	]+xacquire btc ecx,eax
+[ 	]*391[ 	]+xacquire lock btc ecx,eax
+[ 	]*392[ 	]+lock xacquire btc ecx,eax
+[ 	]*393[ 	]+xrelease btc ecx,eax
+[ 	]*394[ 	]+xrelease lock btc ecx,eax
+[ 	]*395[ 	]+lock xrelease btc ecx,eax
+[ 	]*396[ 	]+xacquire btc DWORD PTR \[ecx\],eax
+[ 	]*397[ 	]+xrelease btc DWORD PTR \[ecx\],eax
+[ 	]*398[ 	]+
+[ 	]*399[ 	]+\# Tests for op regb/m8
+GAS LISTING .*
+
+
+[ 	]*400[ 	]+xacquire dec cl
+[ 	]*401[ 	]+xacquire lock dec cl
+[ 	]*402[ 	]+lock xacquire dec cl
+[ 	]*403[ 	]+xrelease dec cl
+[ 	]*404[ 	]+xrelease lock dec cl
+[ 	]*405[ 	]+lock xrelease dec cl
+[ 	]*406[ 	]+xacquire dec BYTE PTR \[ecx\]
+[ 	]*407[ 	]+xrelease dec BYTE PTR \[ecx\]
+[ 	]*408[ 	]+
+[ 	]*409[ 	]+\# Tests for op regs/m16
+[ 	]*410[ 	]+xacquire dec cx
+[ 	]*411[ 	]+xacquire lock dec cx
+[ 	]*412[ 	]+lock xacquire dec cx
+[ 	]*413[ 	]+xrelease dec cx
+[ 	]*414[ 	]+xrelease lock dec cx
+[ 	]*415[ 	]+lock xrelease dec cx
+[ 	]*416[ 	]+xacquire dec WORD PTR \[ecx\]
+[ 	]*417[ 	]+xrelease dec WORD PTR \[ecx\]
+[ 	]*418[ 	]+
+[ 	]*419[ 	]+\# Tests for op regl/m32
+[ 	]*420[ 	]+xacquire dec ecx
+[ 	]*421[ 	]+xacquire lock dec ecx
+[ 	]*422[ 	]+lock xacquire dec ecx
+[ 	]*423[ 	]+xrelease dec ecx
+[ 	]*424[ 	]+xrelease lock dec ecx
+[ 	]*425[ 	]+lock xrelease dec ecx
+[ 	]*426[ 	]+xacquire dec DWORD PTR \[ecx\]
+[ 	]*427[ 	]+xrelease dec DWORD PTR \[ecx\]
+[ 	]*428[ 	]+
+[ 	]*429[ 	]+\# Tests for op m64
+[ 	]*430[ 	]+xacquire cmpxchg8b QWORD PTR \[ecx\]
+[ 	]*431[ 	]+xrelease cmpxchg8b QWORD PTR \[ecx\]
+[ 	]*432[ 	]+
+[ 	]*433[ 	]+\# Tests for op regb, regb/m8
+[ 	]*434[ 	]+xacquire cmpxchg al,cl
+[ 	]*435[ 	]+xacquire lock cmpxchg al,cl
+[ 	]*436[ 	]+lock xacquire cmpxchg al,cl
+[ 	]*437[ 	]+xrelease cmpxchg al,cl
+[ 	]*438[ 	]+xrelease lock cmpxchg al,cl
+[ 	]*439[ 	]+lock xrelease cmpxchg al,cl
+[ 	]*440[ 	]+xacquire cmpxchg BYTE PTR \[ecx\],cl
+[ 	]*441[ 	]+xrelease cmpxchg BYTE PTR \[ecx\],cl
diff --git a/gas/testsuite/gas/i386/hlebad.s b/gas/testsuite/gas/i386/hlebad.s
new file mode 100644
index 0000000..139fe93
--- /dev/null
+++ b/gas/testsuite/gas/i386/hlebad.s
@@ -0,0 +1,441 @@
+# Check 32bit unsupported HLE instructions
+
+	.allow_index_reg
+	.text
+_start:
+
+# Tests for op imm8 al
+	xacquire adc $100,%al
+	xacquire lock adc $100,%al
+	lock xacquire adc $100,%al
+	xrelease adc $100,%al
+	xrelease lock adc $100,%al
+	lock xrelease adc $100,%al
+
+# Tests for op imm16 ax
+	xacquire adc $1000,%ax
+	xacquire lock adc $1000,%ax
+	lock xacquire adc $1000,%ax
+	xrelease adc $1000,%ax
+	xrelease lock adc $1000,%ax
+	lock xrelease adc $1000,%ax
+
+# Tests for op imm32 eax
+	xacquire adc $10000000,%eax
+	xacquire lock adc $10000000,%eax
+	lock xacquire adc $10000000,%eax
+	xrelease adc $10000000,%eax
+	xrelease lock adc $10000000,%eax
+	lock xrelease adc $10000000,%eax
+
+# Tests for op imm8 regb/m8
+	xacquire adcb $100,%cl
+	xacquire lock adcb $100,%cl
+	lock xacquire adcb $100,%cl
+	xrelease adcb $100,%cl
+	xrelease lock adcb $100,%cl
+	lock xrelease adcb $100,%cl
+	xacquire adcb $100,(%ecx)
+	xrelease adcb $100,(%ecx)
+
+# Tests for op imm16 regs/m16
+	xacquire adcw $1000,%cx
+	xacquire lock adcw $1000,%cx
+	lock xacquire adcw $1000,%cx
+	xrelease adcw $1000,%cx
+	xrelease lock adcw $1000,%cx
+	lock xrelease adcw $1000,%cx
+	xacquire adcw $1000,(%ecx)
+	xrelease adcw $1000,(%ecx)
+
+# Tests for op imm32 regl/m32
+	xacquire adcl $10000000,%ecx
+	xacquire lock adcl $10000000,%ecx
+	lock xacquire adcl $10000000,%ecx
+	xrelease adcl $10000000,%ecx
+	xrelease lock adcl $10000000,%ecx
+	lock xrelease adcl $10000000,%ecx
+	xacquire adcl $10000000,(%ecx)
+	xrelease adcl $10000000,(%ecx)
+
+# Tests for op imm8 regs/m16
+	xacquire adcw $100,%cx
+	xacquire lock adcw $100,%cx
+	lock xacquire adcw $100,%cx
+	xrelease adcw $100,%cx
+	xrelease lock adcw $100,%cx
+	lock xrelease adcw $100,%cx
+	xacquire adcw $100,(%ecx)
+	xrelease adcw $100,(%ecx)
+
+# Tests for op imm8 regl/m32
+	xacquire adcl $100,%ecx
+	xacquire lock adcl $100,%ecx
+	lock xacquire adcl $100,%ecx
+	xrelease adcl $100,%ecx
+	xrelease lock adcl $100,%ecx
+	lock xrelease adcl $100,%ecx
+	xacquire adcl $100,(%ecx)
+	xrelease adcl $100,(%ecx)
+
+# Tests for op imm8 regb/m8
+	xacquire adcb $100,%cl
+	xacquire lock adcb $100,%cl
+	lock xacquire adcb $100,%cl
+	xrelease adcb $100,%cl
+	xrelease lock adcb $100,%cl
+	lock xrelease adcb $100,%cl
+	xacquire adcb $100,(%ecx)
+	xrelease adcb $100,(%ecx)
+
+# Tests for op regb regb/m8
+# Tests for op regb/m8 regb
+	xacquire adcb %al,%cl
+	xacquire lock adcb %al,%cl
+	lock xacquire adcb %al,%cl
+	xrelease adcb %al,%cl
+	xrelease lock adcb %al,%cl
+	lock xrelease adcb %al,%cl
+	xacquire adcb %al,(%ecx)
+	xrelease adcb %al,(%ecx)
+	xacquire adcb %cl,%al
+	xacquire lock adcb %cl,%al
+	lock xacquire adcb %cl,%al
+	xrelease adcb %cl,%al
+	xrelease lock adcb %cl,%al
+	lock xrelease adcb %cl,%al
+	xacquire adcb (%ecx),%al
+	xacquire lock adcb (%ecx),%al
+	lock xacquire adcb (%ecx),%al
+	xrelease adcb (%ecx),%al
+	xrelease lock adcb (%ecx),%al
+	lock xrelease adcb (%ecx),%al
+
+# Tests for op regs regs/m16
+# Tests for op regs/m16 regs
+	xacquire adcw %ax,%cx
+	xacquire lock adcw %ax,%cx
+	lock xacquire adcw %ax,%cx
+	xrelease adcw %ax,%cx
+	xrelease lock adcw %ax,%cx
+	lock xrelease adcw %ax,%cx
+	xacquire adcw %ax,(%ecx)
+	xrelease adcw %ax,(%ecx)
+	xacquire adcw %cx,%ax
+	xacquire lock adcw %cx,%ax
+	lock xacquire adcw %cx,%ax
+	xrelease adcw %cx,%ax
+	xrelease lock adcw %cx,%ax
+	lock xrelease adcw %cx,%ax
+	xacquire adcw (%ecx),%ax
+	xacquire lock adcw (%ecx),%ax
+	lock xacquire adcw (%ecx),%ax
+	xrelease adcw (%ecx),%ax
+	xrelease lock adcw (%ecx),%ax
+	lock xrelease adcw (%ecx),%ax
+
+# Tests for op regl regl/m32
+# Tests for op regl/m32 regl
+	xacquire adcl %eax,%ecx
+	xacquire lock adcl %eax,%ecx
+	lock xacquire adcl %eax,%ecx
+	xrelease adcl %eax,%ecx
+	xrelease lock adcl %eax,%ecx
+	lock xrelease adcl %eax,%ecx
+	xacquire adcl %eax,(%ecx)
+	xrelease adcl %eax,(%ecx)
+	xacquire adcl %ecx,%eax
+	xacquire lock adcl %ecx,%eax
+	lock xacquire adcl %ecx,%eax
+	xrelease adcl %ecx,%eax
+	xrelease lock adcl %ecx,%eax
+	lock xrelease adcl %ecx,%eax
+	xacquire adcl (%ecx),%eax
+	xacquire lock adcl (%ecx),%eax
+	lock xacquire adcl (%ecx),%eax
+	xrelease adcl (%ecx),%eax
+	xrelease lock adcl (%ecx),%eax
+	lock xrelease adcl (%ecx),%eax
+
+# Tests for op regs, regs/m16
+	xacquire btcw %ax,%cx
+	xacquire lock btcw %ax,%cx
+	lock xacquire btcw %ax,%cx
+	xrelease btcw %ax,%cx
+	xrelease lock btcw %ax,%cx
+	lock xrelease btcw %ax,%cx
+	xacquire btcw %ax,(%ecx)
+	xrelease btcw %ax,(%ecx)
+
+# Tests for op regl regl/m32
+	xacquire btcl %eax,%ecx
+	xacquire lock btcl %eax,%ecx
+	lock xacquire btcl %eax,%ecx
+	xrelease btcl %eax,%ecx
+	xrelease lock btcl %eax,%ecx
+	lock xrelease btcl %eax,%ecx
+	xacquire btcl %eax,(%ecx)
+	xrelease btcl %eax,(%ecx)
+
+# Tests for op regb/m8
+	xacquire decb %cl
+	xacquire lock decb %cl
+	lock xacquire decb %cl
+	xrelease decb %cl
+	xrelease lock decb %cl
+	lock xrelease decb %cl
+	xacquire decb (%ecx)
+	xrelease decb (%ecx)
+
+# Tests for op regs/m16
+	xacquire decw %cx
+	xacquire lock decw %cx
+	lock xacquire decw %cx
+	xrelease decw %cx
+	xrelease lock decw %cx
+	lock xrelease decw %cx
+	xacquire decw (%ecx)
+	xrelease decw (%ecx)
+
+# Tests for op regl/m32
+	xacquire decl %ecx
+	xacquire lock decl %ecx
+	lock xacquire decl %ecx
+	xrelease decl %ecx
+	xrelease lock decl %ecx
+	lock xrelease decl %ecx
+	xacquire decl (%ecx)
+	xrelease decl (%ecx)
+
+# Tests for op m64
+	xacquire cmpxchg8bq (%ecx)
+	xrelease cmpxchg8bq (%ecx)
+
+# Tests for op regb, regb/m8
+	xacquire cmpxchgb %cl,%al
+	xacquire lock cmpxchgb %cl,%al
+	lock xacquire cmpxchgb %cl,%al
+	xrelease cmpxchgb %cl,%al
+	xrelease lock cmpxchgb %cl,%al
+	lock xrelease cmpxchgb %cl,%al
+	xacquire cmpxchgb %cl,(%ecx)
+	xrelease cmpxchgb %cl,(%ecx)
+
+	.intel_syntax noprefix
+
+# Tests for op imm8 al
+	xacquire adc al,100
+	xacquire lock adc al,100
+	lock xacquire adc al,100
+	xrelease adc al,100
+	xrelease lock adc al,100
+	lock xrelease adc al,100
+
+# Tests for op imm16 ax
+	xacquire adc ax,1000
+	xacquire lock adc ax,1000
+	lock xacquire adc ax,1000
+	xrelease adc ax,1000
+	xrelease lock adc ax,1000
+	lock xrelease adc ax,1000
+
+# Tests for op imm32 eax
+	xacquire adc eax,10000000
+	xacquire lock adc eax,10000000
+	lock xacquire adc eax,10000000
+	xrelease adc eax,10000000
+	xrelease lock adc eax,10000000
+	lock xrelease adc eax,10000000
+
+# Tests for op imm8 regb/m8
+	xacquire adc cl,100
+	xacquire lock adc cl,100
+	lock xacquire adc cl,100
+	xrelease adc cl,100
+	xrelease lock adc cl,100
+	lock xrelease adc cl,100
+	xacquire adc BYTE PTR [ecx],100
+	xrelease adc BYTE PTR [ecx],100
+
+# Tests for op imm16 regs/m16
+	xacquire adc cx,1000
+	xacquire lock adc cx,1000
+	lock xacquire adc cx,1000
+	xrelease adc cx,1000
+	xrelease lock adc cx,1000
+	lock xrelease adc cx,1000
+	xacquire adc WORD PTR [ecx],1000
+	xrelease adc WORD PTR [ecx],1000
+
+# Tests for op imm32 regl/m32
+	xacquire adc ecx,10000000
+	xacquire lock adc ecx,10000000
+	lock xacquire adc ecx,10000000
+	xrelease adc ecx,10000000
+	xrelease lock adc ecx,10000000
+	lock xrelease adc ecx,10000000
+	xacquire adc DWORD PTR [ecx],10000000
+	xrelease adc DWORD PTR [ecx],10000000
+
+# Tests for op imm8 regs/m16
+	xacquire adc cx,100
+	xacquire lock adc cx,100
+	lock xacquire adc cx,100
+	xrelease adc cx,100
+	xrelease lock adc cx,100
+	lock xrelease adc cx,100
+	xacquire adc WORD PTR [ecx],100
+	xrelease adc WORD PTR [ecx],100
+
+# Tests for op imm8 regl/m32
+	xacquire adc ecx,100
+	xacquire lock adc ecx,100
+	lock xacquire adc ecx,100
+	xrelease adc ecx,100
+	xrelease lock adc ecx,100
+	lock xrelease adc ecx,100
+	xacquire adc DWORD PTR [ecx],100
+	xrelease adc DWORD PTR [ecx],100
+
+# Tests for op imm8 regb/m8
+	xacquire adc cl,100
+	xacquire lock adc cl,100
+	lock xacquire adc cl,100
+	xrelease adc cl,100
+	xrelease lock adc cl,100
+	lock xrelease adc cl,100
+	xacquire adc BYTE PTR [ecx],100
+	xrelease adc BYTE PTR [ecx],100
+
+# Tests for op regb regb/m8
+# Tests for op regb/m8 regb
+	xacquire adc cl,al
+	xacquire lock adc cl,al
+	lock xacquire adc cl,al
+	xrelease adc cl,al
+	xrelease lock adc cl,al
+	lock xrelease adc cl,al
+	xacquire adc BYTE PTR [ecx],al
+	xrelease adc BYTE PTR [ecx],al
+	xacquire adc al,cl
+	xacquire lock adc al,cl
+	lock xacquire adc al,cl
+	xrelease adc al,cl
+	xrelease lock adc al,cl
+	lock xrelease adc al,cl
+	xacquire adc al,BYTE PTR [ecx]
+	xacquire lock adc al,BYTE PTR [ecx]
+	lock xacquire adc al,BYTE PTR [ecx]
+	xrelease adc al,BYTE PTR [ecx]
+	xrelease lock adc al,BYTE PTR [ecx]
+	lock xrelease adc al,BYTE PTR [ecx]
+
+# Tests for op regs regs/m16
+# Tests for op regs/m16 regs
+	xacquire adc cx,ax
+	xacquire lock adc cx,ax
+	lock xacquire adc cx,ax
+	xrelease adc cx,ax
+	xrelease lock adc cx,ax
+	lock xrelease adc cx,ax
+	xacquire adc WORD PTR [ecx],ax
+	xrelease adc WORD PTR [ecx],ax
+	xacquire adc ax,cx
+	xacquire lock adc ax,cx
+	lock xacquire adc ax,cx
+	xrelease adc ax,cx
+	xrelease lock adc ax,cx
+	lock xrelease adc ax,cx
+	xacquire adc ax,WORD PTR [ecx]
+	xacquire lock adc ax,WORD PTR [ecx]
+	lock xacquire adc ax,WORD PTR [ecx]
+	xrelease adc ax,WORD PTR [ecx]
+	xrelease lock adc ax,WORD PTR [ecx]
+	lock xrelease adc ax,WORD PTR [ecx]
+
+# Tests for op regl regl/m32
+# Tests for op regl/m32 regl
+	xacquire adc ecx,eax
+	xacquire lock adc ecx,eax
+	lock xacquire adc ecx,eax
+	xrelease adc ecx,eax
+	xrelease lock adc ecx,eax
+	lock xrelease adc ecx,eax
+	xacquire adc DWORD PTR [ecx],eax
+	xrelease adc DWORD PTR [ecx],eax
+	xacquire adc eax,ecx
+	xacquire lock adc eax,ecx
+	lock xacquire adc eax,ecx
+	xrelease adc eax,ecx
+	xrelease lock adc eax,ecx
+	lock xrelease adc eax,ecx
+	xacquire adc eax,DWORD PTR [ecx]
+	xacquire lock adc eax,DWORD PTR [ecx]
+	lock xacquire adc eax,DWORD PTR [ecx]
+	xrelease adc eax,DWORD PTR [ecx]
+	xrelease lock adc eax,DWORD PTR [ecx]
+	lock xrelease adc eax,DWORD PTR [ecx]
+
+# Tests for op regs, regs/m16
+	xacquire btc cx,ax
+	xacquire lock btc cx,ax
+	lock xacquire btc cx,ax
+	xrelease btc cx,ax
+	xrelease lock btc cx,ax
+	lock xrelease btc cx,ax
+	xacquire btc WORD PTR [ecx],ax
+	xrelease btc WORD PTR [ecx],ax
+
+# Tests for op regl regl/m32
+	xacquire btc ecx,eax
+	xacquire lock btc ecx,eax
+	lock xacquire btc ecx,eax
+	xrelease btc ecx,eax
+	xrelease lock btc ecx,eax
+	lock xrelease btc ecx,eax
+	xacquire btc DWORD PTR [ecx],eax
+	xrelease btc DWORD PTR [ecx],eax
+
+# Tests for op regb/m8
+	xacquire dec cl
+	xacquire lock dec cl
+	lock xacquire dec cl
+	xrelease dec cl
+	xrelease lock dec cl
+	lock xrelease dec cl
+	xacquire dec BYTE PTR [ecx]
+	xrelease dec BYTE PTR [ecx]
+
+# Tests for op regs/m16
+	xacquire dec cx
+	xacquire lock dec cx
+	lock xacquire dec cx
+	xrelease dec cx
+	xrelease lock dec cx
+	lock xrelease dec cx
+	xacquire dec WORD PTR [ecx]
+	xrelease dec WORD PTR [ecx]
+
+# Tests for op regl/m32
+	xacquire dec ecx
+	xacquire lock dec ecx
+	lock xacquire dec ecx
+	xrelease dec ecx
+	xrelease lock dec ecx
+	lock xrelease dec ecx
+	xacquire dec DWORD PTR [ecx]
+	xrelease dec DWORD PTR [ecx]
+
+# Tests for op m64
+	xacquire cmpxchg8b QWORD PTR [ecx]
+	xrelease cmpxchg8b QWORD PTR [ecx]
+
+# Tests for op regb, regb/m8
+	xacquire cmpxchg al,cl
+	xacquire lock cmpxchg al,cl
+	lock xacquire cmpxchg al,cl
+	xrelease cmpxchg al,cl
+	xrelease lock cmpxchg al,cl
+	lock xrelease cmpxchg al,cl
+	xacquire cmpxchg BYTE PTR [ecx],cl
+	xrelease cmpxchg BYTE PTR [ecx],cl
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index df37d2f..028cda4 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -186,6 +186,11 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "fma-intel"
     run_dump_test "fma-scalar"
     run_dump_test "fma-scalar-intel"
+    run_dump_test "hle"
+    run_dump_test "hle-intel"
+    run_list_test "hlebad" "-al"
+    run_dump_test "rtm"
+    run_dump_test "rtm-intel"
     run_dump_test "fma4"
     run_dump_test "lwp"
     run_dump_test "xop"
@@ -409,6 +414,11 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-fma-intel"
     run_dump_test "x86-64-fma-scalar"
     run_dump_test "x86-64-fma-scalar-intel"
+    run_dump_test "x86-64-hle"
+    run_dump_test "x86-64-hle-intel"
+    run_list_test "x86-64-hlebad" "-al"
+    run_dump_test "x86-64-rtm"
+    run_dump_test "x86-64-rtm-intel"
     run_dump_test "x86-64-fma4"
     run_dump_test "x86-64-lwp"
     run_dump_test "x86-64-xop"
diff --git a/gas/testsuite/gas/i386/rtm-intel.d b/gas/testsuite/gas/i386/rtm-intel.d
new file mode 100644
index 0000000..6758c71
--- /dev/null
+++ b/gas/testsuite/gas/i386/rtm-intel.d
@@ -0,0 +1,20 @@
+#objdump: -dwMintel
+#name: i386 RTM insns (Intel disassembly)
+#source: rtm.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ 	]*[a-f0-9]+:	c6 f8 08             	xabort 0x8
+[ 	]*[a-f0-9]+:	c7 f8 fa ff ff ff    	xbegin 3 <foo\+0x3>
+[ 	]*[a-f0-9]+:	c7 f8 00 00 00 00    	xbegin f <foo\+0xf>
+[ 	]*[a-f0-9]+:	0f 01 d5             	xend   
+[ 	]*[a-f0-9]+:	c6 f8 08             	xabort 0x8
+[ 	]*[a-f0-9]+:	c7 f8 fa ff ff ff    	xbegin 15 <foo\+0x15>
+[ 	]*[a-f0-9]+:	c7 f8 00 00 00 00    	xbegin 21 <foo\+0x21>
+[ 	]*[a-f0-9]+:	0f 01 d5             	xend   
+[ 	]*[a-f0-9]+:	0f 01 d6             	xtest  
+#pass
diff --git a/gas/testsuite/gas/i386/rtm.d b/gas/testsuite/gas/i386/rtm.d
new file mode 100644
index 0000000..ffdda50
--- /dev/null
+++ b/gas/testsuite/gas/i386/rtm.d
@@ -0,0 +1,19 @@
+#objdump: -dw
+#name: i386 RTM insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ 	]*[a-f0-9]+:	c6 f8 08             	xabort \$0x8
+[ 	]*[a-f0-9]+:	c7 f8 fa ff ff ff    	xbegin 3 <foo\+0x3>
+[ 	]*[a-f0-9]+:	c7 f8 00 00 00 00    	xbegin f <foo\+0xf>
+[ 	]*[a-f0-9]+:	0f 01 d5             	xend   
+[ 	]*[a-f0-9]+:	c6 f8 08             	xabort \$0x8
+[ 	]*[a-f0-9]+:	c7 f8 fa ff ff ff    	xbegin 15 <foo\+0x15>
+[ 	]*[a-f0-9]+:	c7 f8 00 00 00 00    	xbegin 21 <foo\+0x21>
+[ 	]*[a-f0-9]+:	0f 01 d5             	xend   
+[ 	]*[a-f0-9]+:	0f 01 d6             	xtest  
+#pass
diff --git a/gas/testsuite/gas/i386/rtm.s b/gas/testsuite/gas/i386/rtm.s
new file mode 100644
index 0000000..0891fcd
--- /dev/null
+++ b/gas/testsuite/gas/i386/rtm.s
@@ -0,0 +1,19 @@
+# Check RTM new instructions.
+
+	.text
+foo:
+	xabort $0x8
+1:
+	xbegin 1b
+	xbegin 2f
+2:
+	xend
+
+	.intel_syntax noprefix
+	xabort 0x8
+1:
+	xbegin 1b
+	xbegin 2f
+2:
+	xend
+	xtest
diff --git a/gas/testsuite/gas/i386/x86-64-hle-intel.d b/gas/testsuite/gas/i386/x86-64-hle-intel.d
new file mode 100644
index 0000000..1ec740d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-hle-intel.d
@@ -0,0 +1,1623 @@
+#objdump: -dwMintel
+#name: x86-64 HLE insns (Intel disassembly)
+#source: x86-64-hle.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease mov BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adc WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adc WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adc WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adc WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 11 e8 03 	lock xacquire adc WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 11 e8 03 	lock xrelease adc WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock add WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock add WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock add WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock add WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 01 e8 03 	lock xacquire add WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 01 e8 03 	lock xrelease add WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock and WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock and WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock and WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock and WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 21 e8 03 	lock xacquire and WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 21 e8 03 	lock xrelease and WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 c7 01 e8 03    	xrelease mov WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock or WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock or WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock or WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock or WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 09 e8 03 	lock xacquire or WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 09 e8 03 	lock xrelease or WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbb WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbb WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbb WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbb WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 19 e8 03 	lock xacquire sbb WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 19 e8 03 	lock xrelease sbb WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock sub WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock sub WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock sub WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock sub WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 29 e8 03 	lock xacquire sub WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 29 e8 03 	lock xrelease sub WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xor WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xor WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xor WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xor WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 31 e8 03 	lock xacquire xor WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 31 e8 03 	lock xrelease xor WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adc DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adc DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adc DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adc DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 11 80 96 98 00 	lock xacquire adc DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 11 80 96 98 00 	lock xrelease adc DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock add DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock add DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock add DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock add DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 01 80 96 98 00 	lock xacquire add DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 01 80 96 98 00 	lock xrelease add DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock and DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock and DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock and DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock and DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 21 80 96 98 00 	lock xacquire and DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 21 80 96 98 00 	lock xrelease and DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 c7 01 80 96 98 00 	xrelease mov DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock or DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock or DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock or DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock or DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 09 80 96 98 00 	lock xacquire or DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 09 80 96 98 00 	lock xrelease or DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbb DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbb DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbb DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbb DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 19 80 96 98 00 	lock xacquire sbb DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 19 80 96 98 00 	lock xrelease sbb DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock sub DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock sub DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock sub DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock sub DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 29 80 96 98 00 	lock xacquire sub DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 29 80 96 98 00 	lock xrelease sub DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xor DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xor DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xor DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xor DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 31 80 96 98 00 	lock xacquire xor DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 31 80 96 98 00 	lock xrelease xor DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 11 80 96 98 00 	xacquire lock adc QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 11 80 96 98 00 	xacquire lock adc QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 11 80 96 98 00 	xrelease lock adc QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 11 80 96 98 00 	xrelease lock adc QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 48 81 11 80 96 98 00 	lock xacquire adc QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 48 81 11 80 96 98 00 	lock xrelease adc QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 01 80 96 98 00 	xacquire lock add QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 01 80 96 98 00 	xacquire lock add QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 01 80 96 98 00 	xrelease lock add QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 01 80 96 98 00 	xrelease lock add QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 48 81 01 80 96 98 00 	lock xacquire add QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 48 81 01 80 96 98 00 	lock xrelease add QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 21 80 96 98 00 	xacquire lock and QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 21 80 96 98 00 	xacquire lock and QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 21 80 96 98 00 	xrelease lock and QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 21 80 96 98 00 	xrelease lock and QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 48 81 21 80 96 98 00 	lock xacquire and QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 48 81 21 80 96 98 00 	lock xrelease and QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 48 c7 01 80 96 98 00 	xrelease mov QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 09 80 96 98 00 	xacquire lock or QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 09 80 96 98 00 	xacquire lock or QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 09 80 96 98 00 	xrelease lock or QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 09 80 96 98 00 	xrelease lock or QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 48 81 09 80 96 98 00 	lock xacquire or QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 48 81 09 80 96 98 00 	lock xrelease or QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 19 80 96 98 00 	xacquire lock sbb QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 19 80 96 98 00 	xacquire lock sbb QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 19 80 96 98 00 	xrelease lock sbb QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 19 80 96 98 00 	xrelease lock sbb QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 48 81 19 80 96 98 00 	lock xacquire sbb QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 48 81 19 80 96 98 00 	lock xrelease sbb QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 29 80 96 98 00 	xacquire lock sub QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 29 80 96 98 00 	xacquire lock sub QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 29 80 96 98 00 	xrelease lock sub QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 29 80 96 98 00 	xrelease lock sub QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 48 81 29 80 96 98 00 	lock xacquire sub QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 48 81 29 80 96 98 00 	lock xrelease sub QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 31 80 96 98 00 	xacquire lock xor QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 31 80 96 98 00 	xacquire lock xor QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 31 80 96 98 00 	xrelease lock xor QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 31 80 96 98 00 	xrelease lock xor QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 48 81 31 80 96 98 00 	lock xacquire xor QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 48 81 31 80 96 98 00 	lock xrelease xor QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 11 64    	lock xacquire adc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 11 64    	lock xrelease adc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock add WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock add WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock add WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock add WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 01 64    	lock xacquire add WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 01 64    	lock xrelease add WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock and WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock and WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock and WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock and WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 21 64    	lock xacquire and WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 21 64    	lock xrelease and WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 39 64 	lock xacquire btc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 39 64 	lock xrelease btc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btr WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btr WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btr WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btr WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 31 64 	lock xacquire btr WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 31 64 	lock xrelease btr WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock bts WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock bts WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock bts WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock bts WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 29 64 	lock xacquire bts WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 29 64 	lock xrelease bts WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 c7 01 64 00    	xrelease mov WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock or WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock or WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock or WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock or WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 09 64    	lock xacquire or WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 09 64    	lock xrelease or WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbb WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbb WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbb WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbb WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 19 64    	lock xacquire sbb WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 19 64    	lock xrelease sbb WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock sub WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock sub WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock sub WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock sub WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 29 64    	lock xacquire sub WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 29 64    	lock xrelease sub WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xor WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xor WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xor WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xor WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 31 64    	lock xacquire xor WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 31 64    	lock xrelease xor WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 11 64       	lock xacquire adc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 11 64       	lock xrelease adc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock add DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock add DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock add DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock add DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 01 64       	lock xacquire add DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 01 64       	lock xrelease add DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock and DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock and DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock and DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock and DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 21 64       	lock xacquire and DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 21 64       	lock xrelease and DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 39 64    	lock xacquire btc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 39 64    	lock xrelease btc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btr DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btr DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btr DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btr DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 31 64    	lock xacquire btr DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 31 64    	lock xrelease btr DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock bts DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock bts DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock bts DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock bts DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 29 64    	lock xacquire bts DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 29 64    	lock xrelease bts DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 c7 01 64 00 00 00 	xrelease mov DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock or DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock or DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock or DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock or DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 09 64       	lock xacquire or DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 09 64       	lock xrelease or DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbb DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbb DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbb DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbb DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 19 64       	lock xacquire sbb DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 19 64       	lock xrelease sbb DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock sub DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock sub DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock sub DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock sub DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 29 64       	lock xacquire sub DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 29 64       	lock xrelease sub DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xor DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xor DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xor DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xor DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 31 64       	lock xacquire xor DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 31 64       	lock xrelease xor DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 11 64    	xacquire lock adc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 11 64    	xacquire lock adc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 11 64    	xrelease lock adc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 11 64    	xrelease lock adc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 83 11 64    	lock xacquire adc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 83 11 64    	lock xrelease adc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 01 64    	xacquire lock add QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 01 64    	xacquire lock add QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 01 64    	xrelease lock add QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 01 64    	xrelease lock add QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 83 01 64    	lock xacquire add QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 83 01 64    	lock xrelease add QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 21 64    	xacquire lock and QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 21 64    	xacquire lock and QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 21 64    	xrelease lock and QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 21 64    	xrelease lock and QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 83 21 64    	lock xacquire and QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 83 21 64    	lock xrelease and QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 39 64 	xacquire lock btc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 39 64 	xacquire lock btc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 39 64 	xrelease lock btc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 39 64 	xrelease lock btc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ba 39 64 	lock xacquire btc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ba 39 64 	lock xrelease btc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 31 64 	xacquire lock btr QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 31 64 	xacquire lock btr QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 31 64 	xrelease lock btr QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 31 64 	xrelease lock btr QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ba 31 64 	lock xacquire btr QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ba 31 64 	lock xrelease btr QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 29 64 	xacquire lock bts QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 29 64 	xacquire lock bts QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 29 64 	xrelease lock bts QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 29 64 	xrelease lock bts QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ba 29 64 	lock xacquire bts QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ba 29 64 	lock xrelease bts QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 48 c7 01 64 00 00 00 	xrelease mov QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 09 64    	xacquire lock or QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 09 64    	xacquire lock or QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 09 64    	xrelease lock or QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 09 64    	xrelease lock or QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 83 09 64    	lock xacquire or QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 83 09 64    	lock xrelease or QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 19 64    	xacquire lock sbb QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 19 64    	xacquire lock sbb QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 19 64    	xrelease lock sbb QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 19 64    	xrelease lock sbb QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 83 19 64    	lock xacquire sbb QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 83 19 64    	lock xrelease sbb QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 29 64    	xacquire lock sub QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 29 64    	xacquire lock sub QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 29 64    	xrelease lock sub QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 29 64    	xrelease lock sub QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 83 29 64    	lock xacquire sub QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 83 29 64    	lock xrelease sub QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 31 64    	xacquire lock xor QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 31 64    	xacquire lock xor QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 31 64    	xrelease lock xor QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 31 64    	xrelease lock xor QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 83 31 64    	lock xacquire xor QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 83 31 64    	lock xrelease xor QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease mov BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 10 01          	lock xacquire adc BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 10 01          	lock xrelease adc BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 00 01          	lock xacquire add BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 00 01          	lock xrelease add BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 20 01          	lock xacquire and BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 20 01          	lock xrelease and BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 88 01             	xrelease mov BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 08 01          	lock xacquire or BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 08 01          	lock xrelease or BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 18 01          	lock xacquire sbb BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 18 01          	lock xrelease sbb BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 28 01          	lock xacquire sub BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 28 01          	lock xrelease sub BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 86 01             	xacquire xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 86 01             	xrelease xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 86 01          	lock xacquire xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 86 01          	lock xrelease xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 30 01          	lock xacquire xor BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 30 01          	lock xrelease xor BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 11 01       	lock xacquire adc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 11 01       	lock xrelease adc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 01 01       	lock xacquire add WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 01 01       	lock xrelease add WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 21 01       	lock xacquire and WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 21 01       	lock xrelease and WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 89 01          	xrelease mov WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 09 01       	lock xacquire or WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 09 01       	lock xrelease or WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 19 01       	lock xacquire sbb WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 19 01       	lock xrelease sbb WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 29 01       	lock xacquire sub WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 29 01       	lock xrelease sub WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 87 01          	xacquire xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 87 01          	xrelease xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 87 01       	lock xacquire xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 87 01       	lock xrelease xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 31 01       	lock xacquire xor WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 31 01       	lock xrelease xor WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 11 01          	lock xacquire adc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 11 01          	lock xrelease adc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 01 01          	lock xacquire add DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 01 01          	lock xrelease add DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 21 01          	lock xacquire and DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 21 01          	lock xrelease and DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 89 01             	xrelease mov DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 09 01          	lock xacquire or DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 09 01          	lock xrelease or DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 19 01          	lock xacquire sbb DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 19 01          	lock xrelease sbb DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 29 01          	lock xacquire sub DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 29 01          	lock xrelease sub DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 87 01             	xacquire xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 87 01             	xrelease xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 87 01          	lock xacquire xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 87 01          	lock xrelease xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 31 01          	lock xacquire xor DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 31 01          	lock xrelease xor DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 48 11 01       	xacquire lock adc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 11 01       	xacquire lock adc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 11 01       	xrelease lock adc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 11 01       	xrelease lock adc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 11 01       	lock xacquire adc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 11 01       	lock xrelease adc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 01 01       	xacquire lock add QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 01 01       	xacquire lock add QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 01 01       	xrelease lock add QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 01 01       	xrelease lock add QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 01 01       	lock xacquire add QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 01 01       	lock xrelease add QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 21 01       	xacquire lock and QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 21 01       	xacquire lock and QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 21 01       	xrelease lock and QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 21 01       	xrelease lock and QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 21 01       	lock xacquire and QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 21 01       	lock xrelease and QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 48 89 01          	xrelease mov QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 09 01       	xacquire lock or QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 09 01       	xacquire lock or QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 09 01       	xrelease lock or QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 09 01       	xrelease lock or QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 09 01       	lock xacquire or QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 09 01       	lock xrelease or QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 19 01       	xacquire lock sbb QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 19 01       	xacquire lock sbb QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 19 01       	xrelease lock sbb QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 19 01       	xrelease lock sbb QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 19 01       	lock xacquire sbb QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 19 01       	lock xrelease sbb QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 29 01       	xacquire lock sub QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 29 01       	xacquire lock sub QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 29 01       	xrelease lock sub QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 29 01       	xrelease lock sub QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 29 01       	lock xacquire sub QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 29 01       	lock xrelease sub QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 87 01       	xacquire lock xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 87 01       	xacquire lock xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 48 87 01          	xacquire xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 87 01       	xrelease lock xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 87 01       	xrelease lock xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 48 87 01          	xrelease xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 87 01       	lock xacquire xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 87 01       	lock xrelease xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 31 01       	xacquire lock xor QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 31 01       	xacquire lock xor QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 31 01       	xrelease lock xor QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 31 01       	xrelease lock xor QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 31 01       	lock xacquire xor QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 31 01       	lock xrelease xor QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f bb 01    	lock xacquire btc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f bb 01    	lock xrelease btc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b3 01    	lock xacquire btr WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b3 01    	lock xrelease btr WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ab 01    	lock xacquire bts WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ab 01    	lock xrelease bts WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b1 01    	lock xacquire cmpxchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b1 01    	lock xrelease cmpxchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f c1 01    	lock xacquire xadd WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f c1 01    	lock xrelease xadd WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f bb 01       	lock xacquire btc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f bb 01       	lock xrelease btc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f b3 01       	lock xacquire btr DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f b3 01       	lock xrelease btr DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f ab 01       	lock xacquire bts DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f ab 01       	lock xrelease bts DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f b1 01       	lock xacquire cmpxchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f b1 01       	lock xrelease cmpxchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f c1 01       	lock xacquire xadd DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f c1 01       	lock xrelease xadd DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f bb 01    	xacquire lock btc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f bb 01    	xacquire lock btc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f bb 01    	xrelease lock btc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f bb 01    	xrelease lock btc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 0f bb 01    	lock xacquire btc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 0f bb 01    	lock xrelease btc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b3 01    	xacquire lock btr QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b3 01    	xacquire lock btr QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b3 01    	xrelease lock btr QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b3 01    	xrelease lock btr QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 0f b3 01    	lock xacquire btr QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 0f b3 01    	lock xrelease btr QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ab 01    	xacquire lock bts QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ab 01    	xacquire lock bts QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ab 01    	xrelease lock bts QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ab 01    	xrelease lock bts QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ab 01    	lock xacquire bts QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ab 01    	lock xrelease bts QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b1 01    	xacquire lock cmpxchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b1 01    	xacquire lock cmpxchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b1 01    	xrelease lock cmpxchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b1 01    	xrelease lock cmpxchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 0f b1 01    	lock xacquire cmpxchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 0f b1 01    	lock xrelease cmpxchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f c1 01    	xacquire lock xadd QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f c1 01    	xacquire lock xadd QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f c1 01    	xrelease lock xadd QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f c1 01    	xrelease lock xadd QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 0f c1 01    	lock xacquire xadd QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 0f c1 01    	lock xrelease xadd QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock dec BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock dec BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock dec BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock dec BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 fe 09          	lock xacquire dec BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 fe 09          	lock xrelease dec BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock inc BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock inc BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock inc BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock inc BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 fe 01          	lock xacquire inc BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 fe 01          	lock xrelease inc BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock neg BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock neg BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock neg BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock neg BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 f6 19          	lock xacquire neg BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 f6 19          	lock xrelease neg BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock not BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock not BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock not BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock not BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 f6 11          	lock xacquire not BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 f6 11          	lock xrelease not BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock dec WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock dec WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock dec WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock dec WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 09       	lock xacquire dec WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 09       	lock xrelease dec WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock inc WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock inc WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock inc WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock inc WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 01       	lock xacquire inc WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 01       	lock xrelease inc WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock neg WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock neg WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock neg WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock neg WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 19       	lock xacquire neg WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 19       	lock xrelease neg WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock not WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock not WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock not WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock not WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 11       	lock xacquire not WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 11       	lock xrelease not WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock dec DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock dec DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock dec DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock dec DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 ff 09          	lock xacquire dec DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 ff 09          	lock xrelease dec DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock inc DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock inc DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock inc DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock inc DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 ff 01          	lock xacquire inc DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 ff 01          	lock xrelease inc DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock neg DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock neg DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock neg DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock neg DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 f7 19          	lock xacquire neg DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 f7 19          	lock xrelease neg DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock not DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock not DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock not DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock not DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 f7 11          	lock xacquire not DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 f7 11          	lock xrelease not DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 09       	xacquire lock dec QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 09       	xacquire lock dec QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 09       	xrelease lock dec QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 09       	xrelease lock dec QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 48 ff 09       	lock xacquire dec QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 48 ff 09       	lock xrelease dec QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 01       	xacquire lock inc QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 01       	xacquire lock inc QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 01       	xrelease lock inc QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 01       	xrelease lock inc QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 48 ff 01       	lock xacquire inc QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 48 ff 01       	lock xrelease inc QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 19       	xacquire lock neg QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 19       	xacquire lock neg QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 19       	xrelease lock neg QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 19       	xrelease lock neg QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 48 f7 19       	lock xacquire neg QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 48 f7 19       	lock xrelease neg QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 11       	xacquire lock not QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 11       	xacquire lock not QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 11       	xrelease lock not QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 11       	xrelease lock not QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 48 f7 11       	lock xacquire not QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 48 f7 11       	lock xrelease not QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 0f c7 09       	lock xacquire cmpxchg8b QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 0f c7 09       	lock xrelease cmpxchg8b QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f0 f2 0f b0 09       	lock xacquire cmpxchg BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f0 f3 0f b0 09       	lock xrelease cmpxchg BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f0 f2 0f c0 09       	lock xacquire xadd BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f0 f3 0f c0 09       	lock xrelease xadd BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease mov BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adc WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adc WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adc WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adc WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 11 e8 03 	lock xacquire adc WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 11 e8 03 	lock xrelease adc WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock add WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock add WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock add WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock add WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 01 e8 03 	lock xacquire add WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 01 e8 03 	lock xrelease add WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock and WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock and WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock and WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock and WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 21 e8 03 	lock xacquire and WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 21 e8 03 	lock xrelease and WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 c7 01 e8 03    	xrelease mov WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock or WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock or WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock or WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock or WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 09 e8 03 	lock xacquire or WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 09 e8 03 	lock xrelease or WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbb WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbb WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbb WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbb WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 19 e8 03 	lock xacquire sbb WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 19 e8 03 	lock xrelease sbb WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock sub WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock sub WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock sub WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock sub WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 29 e8 03 	lock xacquire sub WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 29 e8 03 	lock xrelease sub WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xor WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xor WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xor WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xor WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f2 66 81 31 e8 03 	lock xacquire xor WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f0 f3 66 81 31 e8 03 	lock xrelease xor WORD PTR \[rcx\],0x3e8
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adc DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adc DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adc DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adc DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 11 80 96 98 00 	lock xacquire adc DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 11 80 96 98 00 	lock xrelease adc DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock add DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock add DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock add DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock add DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 01 80 96 98 00 	lock xacquire add DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 01 80 96 98 00 	lock xrelease add DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock and DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock and DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock and DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock and DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 21 80 96 98 00 	lock xacquire and DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 21 80 96 98 00 	lock xrelease and DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 c7 01 80 96 98 00 	xrelease mov DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock or DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock or DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock or DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock or DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 09 80 96 98 00 	lock xacquire or DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 09 80 96 98 00 	lock xrelease or DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbb DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbb DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbb DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbb DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 19 80 96 98 00 	lock xacquire sbb DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 19 80 96 98 00 	lock xrelease sbb DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock sub DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock sub DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock sub DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock sub DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 29 80 96 98 00 	lock xacquire sub DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 29 80 96 98 00 	lock xrelease sub DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xor DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xor DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xor DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xor DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 81 31 80 96 98 00 	lock xacquire xor DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 81 31 80 96 98 00 	lock xrelease xor DWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 11 80 96 98 00 	xacquire lock adc QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 11 80 96 98 00 	xacquire lock adc QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 11 80 96 98 00 	xrelease lock adc QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 11 80 96 98 00 	xrelease lock adc QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 48 81 11 80 96 98 00 	lock xacquire adc QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 48 81 11 80 96 98 00 	lock xrelease adc QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 01 80 96 98 00 	xacquire lock add QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 01 80 96 98 00 	xacquire lock add QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 01 80 96 98 00 	xrelease lock add QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 01 80 96 98 00 	xrelease lock add QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 48 81 01 80 96 98 00 	lock xacquire add QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 48 81 01 80 96 98 00 	lock xrelease add QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 21 80 96 98 00 	xacquire lock and QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 21 80 96 98 00 	xacquire lock and QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 21 80 96 98 00 	xrelease lock and QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 21 80 96 98 00 	xrelease lock and QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 48 81 21 80 96 98 00 	lock xacquire and QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 48 81 21 80 96 98 00 	lock xrelease and QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 48 c7 01 80 96 98 00 	xrelease mov QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 09 80 96 98 00 	xacquire lock or QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 09 80 96 98 00 	xacquire lock or QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 09 80 96 98 00 	xrelease lock or QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 09 80 96 98 00 	xrelease lock or QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 48 81 09 80 96 98 00 	lock xacquire or QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 48 81 09 80 96 98 00 	lock xrelease or QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 19 80 96 98 00 	xacquire lock sbb QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 19 80 96 98 00 	xacquire lock sbb QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 19 80 96 98 00 	xrelease lock sbb QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 19 80 96 98 00 	xrelease lock sbb QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 48 81 19 80 96 98 00 	lock xacquire sbb QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 48 81 19 80 96 98 00 	lock xrelease sbb QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 29 80 96 98 00 	xacquire lock sub QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 29 80 96 98 00 	xacquire lock sub QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 29 80 96 98 00 	xrelease lock sub QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 29 80 96 98 00 	xrelease lock sub QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 48 81 29 80 96 98 00 	lock xacquire sub QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 48 81 29 80 96 98 00 	lock xrelease sub QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 31 80 96 98 00 	xacquire lock xor QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f2 f0 48 81 31 80 96 98 00 	xacquire lock xor QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 31 80 96 98 00 	xrelease lock xor QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f3 f0 48 81 31 80 96 98 00 	xrelease lock xor QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f2 48 81 31 80 96 98 00 	lock xacquire xor QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	f0 f3 48 81 31 80 96 98 00 	lock xrelease xor QWORD PTR \[rcx\],0x989680
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 11 64    	lock xacquire adc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 11 64    	lock xrelease adc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock add WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock add WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock add WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock add WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 01 64    	lock xacquire add WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 01 64    	lock xrelease add WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock and WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock and WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock and WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock and WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 21 64    	lock xacquire and WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 21 64    	lock xrelease and WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 39 64 	lock xacquire btc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 39 64 	lock xrelease btc WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btr WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btr WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btr WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btr WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 31 64 	lock xacquire btr WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 31 64 	lock xrelease btr WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock bts WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock bts WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock bts WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock bts WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 29 64 	lock xacquire bts WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 29 64 	lock xrelease bts WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 c7 01 64 00    	xrelease mov WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock or WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock or WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock or WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock or WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 09 64    	lock xacquire or WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 09 64    	lock xrelease or WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbb WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbb WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbb WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbb WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 19 64    	lock xacquire sbb WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 19 64    	lock xrelease sbb WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock sub WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock sub WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock sub WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock sub WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 29 64    	lock xacquire sub WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 29 64    	lock xrelease sub WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xor WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xor WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xor WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xor WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 66 83 31 64    	lock xacquire xor WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 66 83 31 64    	lock xrelease xor WORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 11 64       	lock xacquire adc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 11 64       	lock xrelease adc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock add DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock add DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock add DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock add DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 01 64       	lock xacquire add DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 01 64       	lock xrelease add DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock and DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock and DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock and DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock and DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 21 64       	lock xacquire and DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 21 64       	lock xrelease and DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 39 64    	lock xacquire btc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 39 64    	lock xrelease btc DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btr DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btr DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btr DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btr DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 31 64    	lock xacquire btr DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 31 64    	lock xrelease btr DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock bts DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock bts DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock bts DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock bts DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 29 64    	lock xacquire bts DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 29 64    	lock xrelease bts DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 c7 01 64 00 00 00 	xrelease mov DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock or DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock or DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock or DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock or DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 09 64       	lock xacquire or DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 09 64       	lock xrelease or DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbb DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbb DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbb DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbb DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 19 64       	lock xacquire sbb DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 19 64       	lock xrelease sbb DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock sub DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock sub DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock sub DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock sub DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 29 64       	lock xacquire sub DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 29 64       	lock xrelease sub DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xor DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xor DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xor DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xor DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 83 31 64       	lock xacquire xor DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 83 31 64       	lock xrelease xor DWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 11 64    	xacquire lock adc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 11 64    	xacquire lock adc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 11 64    	xrelease lock adc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 11 64    	xrelease lock adc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 83 11 64    	lock xacquire adc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 83 11 64    	lock xrelease adc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 01 64    	xacquire lock add QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 01 64    	xacquire lock add QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 01 64    	xrelease lock add QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 01 64    	xrelease lock add QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 83 01 64    	lock xacquire add QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 83 01 64    	lock xrelease add QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 21 64    	xacquire lock and QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 21 64    	xacquire lock and QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 21 64    	xrelease lock and QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 21 64    	xrelease lock and QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 83 21 64    	lock xacquire and QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 83 21 64    	lock xrelease and QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 39 64 	xacquire lock btc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 39 64 	xacquire lock btc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 39 64 	xrelease lock btc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 39 64 	xrelease lock btc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ba 39 64 	lock xacquire btc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ba 39 64 	lock xrelease btc QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 31 64 	xacquire lock btr QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 31 64 	xacquire lock btr QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 31 64 	xrelease lock btr QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 31 64 	xrelease lock btr QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ba 31 64 	lock xacquire btr QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ba 31 64 	lock xrelease btr QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 29 64 	xacquire lock bts QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 29 64 	xacquire lock bts QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 29 64 	xrelease lock bts QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 29 64 	xrelease lock bts QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ba 29 64 	lock xacquire bts QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ba 29 64 	lock xrelease bts QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 48 c7 01 64 00 00 00 	xrelease mov QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 09 64    	xacquire lock or QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 09 64    	xacquire lock or QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 09 64    	xrelease lock or QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 09 64    	xrelease lock or QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 83 09 64    	lock xacquire or QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 83 09 64    	lock xrelease or QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 19 64    	xacquire lock sbb QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 19 64    	xacquire lock sbb QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 19 64    	xrelease lock sbb QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 19 64    	xrelease lock sbb QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 83 19 64    	lock xacquire sbb QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 83 19 64    	lock xrelease sbb QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 29 64    	xacquire lock sub QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 29 64    	xacquire lock sub QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 29 64    	xrelease lock sub QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 29 64    	xrelease lock sub QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 83 29 64    	lock xacquire sub QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 83 29 64    	lock xrelease sub QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 31 64    	xacquire lock xor QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 48 83 31 64    	xacquire lock xor QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 31 64    	xrelease lock xor QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 48 83 31 64    	xrelease lock xor QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 48 83 31 64    	lock xacquire xor QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 48 83 31 64    	lock xrelease xor QWORD PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adc BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease add BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease and BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease mov BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease or BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbb BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease sub BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xor BYTE PTR \[rcx\],0x64
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 10 01          	lock xacquire adc BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 10 01          	lock xrelease adc BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 00 01          	lock xacquire add BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 00 01          	lock xrelease add BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 20 01          	lock xacquire and BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 20 01          	lock xrelease and BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 88 01             	xrelease mov BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 08 01          	lock xacquire or BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 08 01          	lock xrelease or BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 18 01          	lock xacquire sbb BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 18 01          	lock xrelease sbb BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 28 01          	lock xacquire sub BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 28 01          	lock xrelease sub BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 86 01             	xacquire xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 86 01             	xrelease xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 86 01          	lock xacquire xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 86 01          	lock xrelease xchg BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f2 30 01          	lock xacquire xor BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	f0 f3 30 01          	lock xrelease xor BYTE PTR \[rcx\],al
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 11 01       	lock xacquire adc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 11 01       	lock xrelease adc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 01 01       	lock xacquire add WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 01 01       	lock xrelease add WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 21 01       	lock xacquire and WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 21 01       	lock xrelease and WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 89 01          	xrelease mov WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 09 01       	lock xacquire or WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 09 01       	lock xrelease or WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 19 01       	lock xacquire sbb WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 19 01       	lock xrelease sbb WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 29 01       	lock xacquire sub WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 29 01       	lock xrelease sub WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 87 01          	xacquire xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 87 01          	xrelease xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 87 01       	lock xacquire xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 87 01       	lock xrelease xchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 31 01       	lock xacquire xor WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 31 01       	lock xrelease xor WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 11 01          	lock xacquire adc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 11 01          	lock xrelease adc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 01 01          	lock xacquire add DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 01 01          	lock xrelease add DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 21 01          	lock xacquire and DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 21 01          	lock xrelease and DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 89 01             	xrelease mov DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 09 01          	lock xacquire or DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 09 01          	lock xrelease or DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 19 01          	lock xacquire sbb DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 19 01          	lock xrelease sbb DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 29 01          	lock xacquire sub DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 29 01          	lock xrelease sub DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 87 01             	xacquire xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 87 01             	xrelease xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 87 01          	lock xacquire xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 87 01          	lock xrelease xchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 31 01          	lock xacquire xor DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 31 01          	lock xrelease xor DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 48 11 01       	xacquire lock adc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 11 01       	xacquire lock adc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 11 01       	xrelease lock adc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 11 01       	xrelease lock adc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 11 01       	lock xacquire adc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 11 01       	lock xrelease adc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 01 01       	xacquire lock add QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 01 01       	xacquire lock add QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 01 01       	xrelease lock add QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 01 01       	xrelease lock add QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 01 01       	lock xacquire add QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 01 01       	lock xrelease add QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 21 01       	xacquire lock and QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 21 01       	xacquire lock and QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 21 01       	xrelease lock and QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 21 01       	xrelease lock and QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 21 01       	lock xacquire and QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 21 01       	lock xrelease and QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 48 89 01          	xrelease mov QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 09 01       	xacquire lock or QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 09 01       	xacquire lock or QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 09 01       	xrelease lock or QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 09 01       	xrelease lock or QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 09 01       	lock xacquire or QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 09 01       	lock xrelease or QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 19 01       	xacquire lock sbb QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 19 01       	xacquire lock sbb QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 19 01       	xrelease lock sbb QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 19 01       	xrelease lock sbb QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 19 01       	lock xacquire sbb QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 19 01       	lock xrelease sbb QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 29 01       	xacquire lock sub QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 29 01       	xacquire lock sub QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 29 01       	xrelease lock sub QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 29 01       	xrelease lock sub QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 29 01       	lock xacquire sub QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 29 01       	lock xrelease sub QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 87 01       	xacquire lock xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 87 01       	xacquire lock xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 48 87 01          	xacquire xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 87 01       	xrelease lock xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 87 01       	xrelease lock xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 48 87 01          	xrelease xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 87 01       	lock xacquire xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 87 01       	lock xrelease xchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 31 01       	xacquire lock xor QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 31 01       	xacquire lock xor QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 31 01       	xrelease lock xor QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 31 01       	xrelease lock xor QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 31 01       	lock xacquire xor QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 31 01       	lock xrelease xor QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f bb 01    	lock xacquire btc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f bb 01    	lock xrelease btc WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b3 01    	lock xacquire btr WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b3 01    	lock xrelease btr WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ab 01    	lock xacquire bts WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ab 01    	lock xrelease bts WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b1 01    	lock xacquire cmpxchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b1 01    	lock xrelease cmpxchg WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f2 66 0f c1 01    	lock xacquire xadd WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f0 f3 66 0f c1 01    	lock xrelease xadd WORD PTR \[rcx\],ax
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f bb 01       	lock xacquire btc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f bb 01       	lock xrelease btc DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f b3 01       	lock xacquire btr DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f b3 01       	lock xrelease btr DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f ab 01       	lock xacquire bts DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f ab 01       	lock xrelease bts DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f b1 01       	lock xacquire cmpxchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f b1 01       	lock xrelease cmpxchg DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f2 0f c1 01       	lock xacquire xadd DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f0 f3 0f c1 01       	lock xrelease xadd DWORD PTR \[rcx\],eax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f bb 01    	xacquire lock btc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f bb 01    	xacquire lock btc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f bb 01    	xrelease lock btc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f bb 01    	xrelease lock btc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 0f bb 01    	lock xacquire btc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 0f bb 01    	lock xrelease btc QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b3 01    	xacquire lock btr QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b3 01    	xacquire lock btr QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b3 01    	xrelease lock btr QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b3 01    	xrelease lock btr QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 0f b3 01    	lock xacquire btr QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 0f b3 01    	lock xrelease btr QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ab 01    	xacquire lock bts QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ab 01    	xacquire lock bts QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ab 01    	xrelease lock bts QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ab 01    	xrelease lock bts QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ab 01    	lock xacquire bts QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ab 01    	lock xrelease bts QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b1 01    	xacquire lock cmpxchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b1 01    	xacquire lock cmpxchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b1 01    	xrelease lock cmpxchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b1 01    	xrelease lock cmpxchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 0f b1 01    	lock xacquire cmpxchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 0f b1 01    	lock xrelease cmpxchg QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f c1 01    	xacquire lock xadd QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 48 0f c1 01    	xacquire lock xadd QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f c1 01    	xrelease lock xadd QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f3 f0 48 0f c1 01    	xrelease lock xadd QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f2 48 0f c1 01    	lock xacquire xadd QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f0 f3 48 0f c1 01    	lock xrelease xadd QWORD PTR \[rcx\],rax
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock dec BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock dec BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock dec BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock dec BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 fe 09          	lock xacquire dec BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 fe 09          	lock xrelease dec BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock inc BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock inc BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock inc BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock inc BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 fe 01          	lock xacquire inc BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 fe 01          	lock xrelease inc BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock neg BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock neg BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock neg BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock neg BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 f6 19          	lock xacquire neg BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 f6 19          	lock xrelease neg BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock not BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock not BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock not BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock not BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 f6 11          	lock xacquire not BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 f6 11          	lock xrelease not BYTE PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock dec WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock dec WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock dec WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock dec WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 09       	lock xacquire dec WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 09       	lock xrelease dec WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock inc WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock inc WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock inc WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock inc WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 01       	lock xacquire inc WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 01       	lock xrelease inc WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock neg WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock neg WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock neg WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock neg WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 19       	lock xacquire neg WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 19       	lock xrelease neg WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock not WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock not WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock not WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock not WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 11       	lock xacquire not WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 11       	lock xrelease not WORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock dec DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock dec DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock dec DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock dec DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 ff 09          	lock xacquire dec DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 ff 09          	lock xrelease dec DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock inc DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock inc DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock inc DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock inc DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 ff 01          	lock xacquire inc DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 ff 01          	lock xrelease inc DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock neg DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock neg DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock neg DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock neg DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 f7 19          	lock xacquire neg DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 f7 19          	lock xrelease neg DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock not DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock not DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock not DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock not DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 f7 11          	lock xacquire not DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 f7 11          	lock xrelease not DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 09       	xacquire lock dec QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 09       	xacquire lock dec QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 09       	xrelease lock dec QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 09       	xrelease lock dec QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 48 ff 09       	lock xacquire dec QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 48 ff 09       	lock xrelease dec QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 01       	xacquire lock inc QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 01       	xacquire lock inc QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 01       	xrelease lock inc QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 01       	xrelease lock inc QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 48 ff 01       	lock xacquire inc QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 48 ff 01       	lock xrelease inc QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 19       	xacquire lock neg QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 19       	xacquire lock neg QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 19       	xrelease lock neg QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 19       	xrelease lock neg QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 48 f7 19       	lock xacquire neg QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 48 f7 19       	lock xrelease neg QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 11       	xacquire lock not QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 11       	xacquire lock not QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 11       	xrelease lock not QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 11       	xrelease lock not QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 48 f7 11       	lock xacquire not QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 48 f7 11       	lock xrelease not QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f2 0f c7 09       	lock xacquire cmpxchg8b QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f0 f3 0f c7 09       	lock xrelease cmpxchg8b QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f0 f2 0f b0 09       	lock xacquire cmpxchg BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f0 f3 0f b0 09       	lock xrelease cmpxchg BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f0 f2 0f c0 09       	lock xacquire xadd BYTE PTR \[rcx\],cl
+[ 	]*[a-f0-9]+:	f0 f3 0f c0 09       	lock xrelease xadd BYTE PTR \[rcx\],cl
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-hle.d b/gas/testsuite/gas/i386/x86-64-hle.d
new file mode 100644
index 0000000..02fa28d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-hle.d
@@ -0,0 +1,1622 @@
+#objdump: -dw
+#name: x86-64 HLE insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease movb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adcw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adcw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adcw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adcw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 11 e8 03 	lock xacquire adcw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 11 e8 03 	lock xrelease adcw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock addw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock addw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock addw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock addw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 01 e8 03 	lock xacquire addw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 01 e8 03 	lock xrelease addw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock andw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock andw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock andw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock andw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 21 e8 03 	lock xacquire andw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 21 e8 03 	lock xrelease andw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 c7 01 e8 03    	xrelease movw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock orw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock orw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock orw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock orw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 09 e8 03 	lock xacquire orw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 09 e8 03 	lock xrelease orw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbbw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbbw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbbw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbbw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 19 e8 03 	lock xacquire sbbw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 19 e8 03 	lock xrelease sbbw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock subw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock subw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock subw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock subw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 29 e8 03 	lock xacquire subw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 29 e8 03 	lock xrelease subw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xorw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xorw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xorw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xorw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 31 e8 03 	lock xacquire xorw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 31 e8 03 	lock xrelease xorw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adcl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adcl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adcl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adcl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 11 80 96 98 00 	lock xacquire adcl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 11 80 96 98 00 	lock xrelease adcl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock addl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock addl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock addl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock addl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 01 80 96 98 00 	lock xacquire addl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 01 80 96 98 00 	lock xrelease addl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock andl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock andl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock andl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock andl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 21 80 96 98 00 	lock xacquire andl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 21 80 96 98 00 	lock xrelease andl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 c7 01 80 96 98 00 	xrelease movl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock orl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock orl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock orl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock orl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 09 80 96 98 00 	lock xacquire orl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 09 80 96 98 00 	lock xrelease orl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbbl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbbl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbbl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbbl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 19 80 96 98 00 	lock xacquire sbbl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 19 80 96 98 00 	lock xrelease sbbl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock subl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock subl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock subl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock subl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 29 80 96 98 00 	lock xacquire subl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 29 80 96 98 00 	lock xrelease subl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xorl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xorl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xorl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xorl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 31 80 96 98 00 	lock xacquire xorl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 31 80 96 98 00 	lock xrelease xorl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 11 80 96 98 00 	xacquire lock adcq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 11 80 96 98 00 	xacquire lock adcq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 11 80 96 98 00 	xrelease lock adcq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 11 80 96 98 00 	xrelease lock adcq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 81 11 80 96 98 00 	lock xacquire adcq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 81 11 80 96 98 00 	lock xrelease adcq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 01 80 96 98 00 	xacquire lock addq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 01 80 96 98 00 	xacquire lock addq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 01 80 96 98 00 	xrelease lock addq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 01 80 96 98 00 	xrelease lock addq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 81 01 80 96 98 00 	lock xacquire addq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 81 01 80 96 98 00 	lock xrelease addq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 21 80 96 98 00 	xacquire lock andq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 21 80 96 98 00 	xacquire lock andq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 21 80 96 98 00 	xrelease lock andq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 21 80 96 98 00 	xrelease lock andq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 81 21 80 96 98 00 	lock xacquire andq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 81 21 80 96 98 00 	lock xrelease andq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 48 c7 01 80 96 98 00 	xrelease movq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 09 80 96 98 00 	xacquire lock orq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 09 80 96 98 00 	xacquire lock orq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 09 80 96 98 00 	xrelease lock orq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 09 80 96 98 00 	xrelease lock orq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 81 09 80 96 98 00 	lock xacquire orq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 81 09 80 96 98 00 	lock xrelease orq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 19 80 96 98 00 	xacquire lock sbbq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 19 80 96 98 00 	xacquire lock sbbq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 19 80 96 98 00 	xrelease lock sbbq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 19 80 96 98 00 	xrelease lock sbbq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 81 19 80 96 98 00 	lock xacquire sbbq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 81 19 80 96 98 00 	lock xrelease sbbq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 29 80 96 98 00 	xacquire lock subq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 29 80 96 98 00 	xacquire lock subq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 29 80 96 98 00 	xrelease lock subq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 29 80 96 98 00 	xrelease lock subq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 81 29 80 96 98 00 	lock xacquire subq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 81 29 80 96 98 00 	lock xrelease subq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 31 80 96 98 00 	xacquire lock xorq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 31 80 96 98 00 	xacquire lock xorq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 31 80 96 98 00 	xrelease lock xorq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 31 80 96 98 00 	xrelease lock xorq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 81 31 80 96 98 00 	lock xacquire xorq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 81 31 80 96 98 00 	lock xrelease xorq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 11 64    	lock xacquire adcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 11 64    	lock xrelease adcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock addw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock addw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock addw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock addw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 01 64    	lock xacquire addw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 01 64    	lock xrelease addw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock andw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock andw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock andw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock andw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 21 64    	lock xacquire andw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 21 64    	lock xrelease andw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 39 64 	lock xacquire btcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 39 64 	lock xrelease btcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btrw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btrw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btrw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btrw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 31 64 	lock xacquire btrw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 31 64 	lock xrelease btrw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock btsw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock btsw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock btsw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock btsw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 29 64 	lock xacquire btsw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 29 64 	lock xrelease btsw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 c7 01 64 00    	xrelease movw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock orw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock orw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock orw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock orw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 09 64    	lock xacquire orw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 09 64    	lock xrelease orw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbbw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbbw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbbw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbbw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 19 64    	lock xacquire sbbw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 19 64    	lock xrelease sbbw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock subw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock subw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock subw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock subw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 29 64    	lock xacquire subw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 29 64    	lock xrelease subw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xorw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xorw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xorw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xorw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 31 64    	lock xacquire xorw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 31 64    	lock xrelease xorw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 11 64       	lock xacquire adcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 11 64       	lock xrelease adcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock addl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock addl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock addl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock addl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 01 64       	lock xacquire addl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 01 64       	lock xrelease addl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock andl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock andl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock andl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock andl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 21 64       	lock xacquire andl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 21 64       	lock xrelease andl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 39 64    	lock xacquire btcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 39 64    	lock xrelease btcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btrl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btrl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btrl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btrl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 31 64    	lock xacquire btrl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 31 64    	lock xrelease btrl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock btsl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock btsl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock btsl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock btsl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 29 64    	lock xacquire btsl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 29 64    	lock xrelease btsl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 c7 01 64 00 00 00 	xrelease movl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock orl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock orl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock orl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock orl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 09 64       	lock xacquire orl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 09 64       	lock xrelease orl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbbl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbbl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbbl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbbl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 19 64       	lock xacquire sbbl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 19 64       	lock xrelease sbbl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock subl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock subl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock subl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock subl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 29 64       	lock xacquire subl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 29 64       	lock xrelease subl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xorl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xorl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xorl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xorl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 31 64       	lock xacquire xorl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 31 64       	lock xrelease xorl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 11 64    	xacquire lock adcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 11 64    	xacquire lock adcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 11 64    	xrelease lock adcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 11 64    	xrelease lock adcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 83 11 64    	lock xacquire adcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 83 11 64    	lock xrelease adcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 01 64    	xacquire lock addq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 01 64    	xacquire lock addq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 01 64    	xrelease lock addq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 01 64    	xrelease lock addq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 83 01 64    	lock xacquire addq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 83 01 64    	lock xrelease addq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 21 64    	xacquire lock andq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 21 64    	xacquire lock andq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 21 64    	xrelease lock andq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 21 64    	xrelease lock andq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 83 21 64    	lock xacquire andq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 83 21 64    	lock xrelease andq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 39 64 	xacquire lock btcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 39 64 	xacquire lock btcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 39 64 	xrelease lock btcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 39 64 	xrelease lock btcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ba 39 64 	lock xacquire btcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ba 39 64 	lock xrelease btcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 31 64 	xacquire lock btrq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 31 64 	xacquire lock btrq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 31 64 	xrelease lock btrq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 31 64 	xrelease lock btrq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ba 31 64 	lock xacquire btrq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ba 31 64 	lock xrelease btrq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 29 64 	xacquire lock btsq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 29 64 	xacquire lock btsq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 29 64 	xrelease lock btsq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 29 64 	xrelease lock btsq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ba 29 64 	lock xacquire btsq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ba 29 64 	lock xrelease btsq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 48 c7 01 64 00 00 00 	xrelease movq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 09 64    	xacquire lock orq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 09 64    	xacquire lock orq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 09 64    	xrelease lock orq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 09 64    	xrelease lock orq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 83 09 64    	lock xacquire orq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 83 09 64    	lock xrelease orq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 19 64    	xacquire lock sbbq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 19 64    	xacquire lock sbbq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 19 64    	xrelease lock sbbq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 19 64    	xrelease lock sbbq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 83 19 64    	lock xacquire sbbq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 83 19 64    	lock xrelease sbbq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 29 64    	xacquire lock subq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 29 64    	xacquire lock subq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 29 64    	xrelease lock subq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 29 64    	xrelease lock subq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 83 29 64    	lock xacquire subq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 83 29 64    	lock xrelease subq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 31 64    	xacquire lock xorq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 31 64    	xacquire lock xorq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 31 64    	xrelease lock xorq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 31 64    	xrelease lock xorq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 83 31 64    	lock xacquire xorq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 83 31 64    	lock xrelease xorq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease movb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 10 01          	lock xacquire adc %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 10 01          	lock xrelease adc %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 00 01          	lock xacquire add %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 00 01          	lock xrelease add %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 20 01          	lock xacquire and %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 20 01          	lock xrelease and %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 88 01             	xrelease mov %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 08 01          	lock xacquire or %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 08 01          	lock xrelease or %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 18 01          	lock xacquire sbb %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 18 01          	lock xrelease sbb %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 28 01          	lock xacquire sub %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 28 01          	lock xrelease sub %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 86 01             	xacquire xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 86 01             	xrelease xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 86 01          	lock xacquire xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 86 01          	lock xrelease xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 30 01          	lock xacquire xor %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 30 01          	lock xrelease xor %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 11 01       	lock xacquire adc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 11 01       	lock xrelease adc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 01 01       	lock xacquire add %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 01 01       	lock xrelease add %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 21 01       	lock xacquire and %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 21 01       	lock xrelease and %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 89 01          	xrelease mov %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 09 01       	lock xacquire or %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 09 01       	lock xrelease or %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 19 01       	lock xacquire sbb %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 19 01       	lock xrelease sbb %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 29 01       	lock xacquire sub %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 29 01       	lock xrelease sub %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 87 01          	xacquire xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 87 01          	xrelease xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 87 01       	lock xacquire xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 87 01       	lock xrelease xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 31 01       	lock xacquire xor %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 31 01       	lock xrelease xor %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 11 01          	lock xacquire adc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 11 01          	lock xrelease adc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 01 01          	lock xacquire add %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 01 01          	lock xrelease add %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 21 01          	lock xacquire and %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 21 01          	lock xrelease and %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 89 01             	xrelease mov %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 09 01          	lock xacquire or %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 09 01          	lock xrelease or %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 19 01          	lock xacquire sbb %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 19 01          	lock xrelease sbb %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 29 01          	lock xacquire sub %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 29 01          	lock xrelease sub %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 87 01             	xacquire xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 87 01             	xrelease xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 87 01          	lock xacquire xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 87 01          	lock xrelease xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 31 01          	lock xacquire xor %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 31 01          	lock xrelease xor %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 11 01       	xacquire lock adc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 11 01       	xacquire lock adc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 11 01       	xrelease lock adc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 11 01       	xrelease lock adc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 11 01       	lock xacquire adc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 11 01       	lock xrelease adc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 01 01       	xacquire lock add %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 01 01       	xacquire lock add %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 01 01       	xrelease lock add %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 01 01       	xrelease lock add %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 01 01       	lock xacquire add %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 01 01       	lock xrelease add %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 21 01       	xacquire lock and %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 21 01       	xacquire lock and %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 21 01       	xrelease lock and %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 21 01       	xrelease lock and %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 21 01       	lock xacquire and %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 21 01       	lock xrelease and %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 48 89 01          	xrelease mov %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 09 01       	xacquire lock or %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 09 01       	xacquire lock or %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 09 01       	xrelease lock or %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 09 01       	xrelease lock or %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 09 01       	lock xacquire or %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 09 01       	lock xrelease or %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 19 01       	xacquire lock sbb %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 19 01       	xacquire lock sbb %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 19 01       	xrelease lock sbb %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 19 01       	xrelease lock sbb %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 19 01       	lock xacquire sbb %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 19 01       	lock xrelease sbb %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 29 01       	xacquire lock sub %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 29 01       	xacquire lock sub %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 29 01       	xrelease lock sub %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 29 01       	xrelease lock sub %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 29 01       	lock xacquire sub %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 29 01       	lock xrelease sub %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 87 01       	xacquire lock xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 87 01       	xacquire lock xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 48 87 01          	xacquire xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 87 01       	xrelease lock xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 87 01       	xrelease lock xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 48 87 01          	xrelease xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 87 01       	lock xacquire xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 87 01       	lock xrelease xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 31 01       	xacquire lock xor %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 31 01       	xacquire lock xor %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 31 01       	xrelease lock xor %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 31 01       	xrelease lock xor %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 31 01       	lock xacquire xor %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 31 01       	lock xrelease xor %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f bb 01    	lock xacquire btc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f bb 01    	lock xrelease btc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b3 01    	lock xacquire btr %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b3 01    	lock xrelease btr %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ab 01    	lock xacquire bts %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ab 01    	lock xrelease bts %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b1 01    	lock xacquire cmpxchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b1 01    	lock xrelease cmpxchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f c1 01    	lock xacquire xadd %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f c1 01    	lock xrelease xadd %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f bb 01       	lock xacquire btc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f bb 01       	lock xrelease btc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f b3 01       	lock xacquire btr %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f b3 01       	lock xrelease btr %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ab 01       	lock xacquire bts %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ab 01       	lock xrelease bts %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f b1 01       	lock xacquire cmpxchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f b1 01       	lock xrelease cmpxchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f c1 01       	lock xacquire xadd %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f c1 01       	lock xrelease xadd %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f bb 01    	xacquire lock btc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f bb 01    	xacquire lock btc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f bb 01    	xrelease lock btc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f bb 01    	xrelease lock btc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f bb 01    	lock xacquire btc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f bb 01    	lock xrelease btc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b3 01    	xacquire lock btr %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b3 01    	xacquire lock btr %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b3 01    	xrelease lock btr %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b3 01    	xrelease lock btr %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f b3 01    	lock xacquire btr %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f b3 01    	lock xrelease btr %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ab 01    	xacquire lock bts %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ab 01    	xacquire lock bts %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ab 01    	xrelease lock bts %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ab 01    	xrelease lock bts %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ab 01    	lock xacquire bts %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ab 01    	lock xrelease bts %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b1 01    	xacquire lock cmpxchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b1 01    	xacquire lock cmpxchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b1 01    	xrelease lock cmpxchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b1 01    	xrelease lock cmpxchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f b1 01    	lock xacquire cmpxchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f b1 01    	lock xrelease cmpxchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f c1 01    	xacquire lock xadd %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f c1 01    	xacquire lock xadd %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f c1 01    	xrelease lock xadd %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f c1 01    	xrelease lock xadd %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f c1 01    	lock xacquire xadd %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f c1 01    	lock xrelease xadd %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock decb \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock decb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock decb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock decb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 fe 09          	lock xacquire decb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 fe 09          	lock xrelease decb \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock incb \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock incb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock incb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock incb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 fe 01          	lock xacquire incb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 fe 01          	lock xrelease incb \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock negb \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock negb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock negb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock negb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 f6 19          	lock xacquire negb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 f6 19          	lock xrelease negb \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock notb \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock notb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock notb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock notb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 f6 11          	lock xacquire notb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 f6 11          	lock xrelease notb \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock decw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock decw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock decw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock decw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 09       	lock xacquire decw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 09       	lock xrelease decw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock incw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock incw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock incw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock incw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 01       	lock xacquire incw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 01       	lock xrelease incw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock negw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock negw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock negw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock negw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 19       	lock xacquire negw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 19       	lock xrelease negw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock notw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock notw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock notw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock notw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 11       	lock xacquire notw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 11       	lock xrelease notw \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock decl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock decl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock decl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock decl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 ff 09          	lock xacquire decl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 ff 09          	lock xrelease decl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock incl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock incl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock incl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock incl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 ff 01          	lock xacquire incl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 ff 01          	lock xrelease incl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock negl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock negl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock negl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock negl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 f7 19          	lock xacquire negl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 f7 19          	lock xrelease negl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock notl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock notl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock notl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock notl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 f7 11          	lock xacquire notl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 f7 11          	lock xrelease notl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 09       	xacquire lock decq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 09       	xacquire lock decq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 09       	xrelease lock decq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 09       	xrelease lock decq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 ff 09       	lock xacquire decq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 ff 09       	lock xrelease decq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 01       	xacquire lock incq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 01       	xacquire lock incq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 01       	xrelease lock incq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 01       	xrelease lock incq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 ff 01       	lock xacquire incq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 ff 01       	lock xrelease incq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 19       	xacquire lock negq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 19       	xacquire lock negq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 19       	xrelease lock negq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 19       	xrelease lock negq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 f7 19       	lock xacquire negq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 f7 19       	lock xrelease negq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 11       	xacquire lock notq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 11       	xacquire lock notq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 11       	xrelease lock notq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 11       	xrelease lock notq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 f7 11       	lock xacquire notq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 f7 11       	lock xrelease notq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f c7 09       	lock xacquire cmpxchg8b \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f c7 09       	lock xrelease cmpxchg8b \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f b0 09       	lock xacquire cmpxchg %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f b0 09       	lock xrelease cmpxchg %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f c0 09       	lock xacquire xadd %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f c0 09       	lock xrelease xadd %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease movb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adcw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 11 e8 03 	xacquire lock adcw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adcw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 11 e8 03 	xrelease lock adcw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 11 e8 03 	lock xacquire adcw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 11 e8 03 	lock xrelease adcw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock addw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 01 e8 03 	xacquire lock addw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock addw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 01 e8 03 	xrelease lock addw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 01 e8 03 	lock xacquire addw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 01 e8 03 	lock xrelease addw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock andw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 21 e8 03 	xacquire lock andw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock andw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 21 e8 03 	xrelease lock andw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 21 e8 03 	lock xacquire andw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 21 e8 03 	lock xrelease andw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 c7 01 e8 03    	xrelease movw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock orw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 09 e8 03 	xacquire lock orw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock orw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 09 e8 03 	xrelease lock orw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 09 e8 03 	lock xacquire orw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 09 e8 03 	lock xrelease orw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbbw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 19 e8 03 	xacquire lock sbbw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbbw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 19 e8 03 	xrelease lock sbbw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 19 e8 03 	lock xacquire sbbw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 19 e8 03 	lock xrelease sbbw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock subw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 29 e8 03 	xacquire lock subw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock subw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 29 e8 03 	xrelease lock subw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 29 e8 03 	lock xacquire subw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 29 e8 03 	lock xrelease subw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xorw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 81 31 e8 03 	xacquire lock xorw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xorw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 81 31 e8 03 	xrelease lock xorw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 81 31 e8 03 	lock xacquire xorw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 81 31 e8 03 	lock xrelease xorw \$0x3e8,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adcl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 11 80 96 98 00 	xacquire lock adcl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adcl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 11 80 96 98 00 	xrelease lock adcl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 11 80 96 98 00 	lock xacquire adcl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 11 80 96 98 00 	lock xrelease adcl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock addl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 01 80 96 98 00 	xacquire lock addl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock addl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 01 80 96 98 00 	xrelease lock addl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 01 80 96 98 00 	lock xacquire addl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 01 80 96 98 00 	lock xrelease addl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock andl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 21 80 96 98 00 	xacquire lock andl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock andl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 21 80 96 98 00 	xrelease lock andl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 21 80 96 98 00 	lock xacquire andl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 21 80 96 98 00 	lock xrelease andl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 c7 01 80 96 98 00 	xrelease movl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock orl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 09 80 96 98 00 	xacquire lock orl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock orl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 09 80 96 98 00 	xrelease lock orl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 09 80 96 98 00 	lock xacquire orl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 09 80 96 98 00 	lock xrelease orl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbbl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 19 80 96 98 00 	xacquire lock sbbl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbbl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 19 80 96 98 00 	xrelease lock sbbl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 19 80 96 98 00 	lock xacquire sbbl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 19 80 96 98 00 	lock xrelease sbbl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock subl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 29 80 96 98 00 	xacquire lock subl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock subl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 29 80 96 98 00 	xrelease lock subl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 29 80 96 98 00 	lock xacquire subl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 29 80 96 98 00 	lock xrelease subl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xorl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 81 31 80 96 98 00 	xacquire lock xorl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xorl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 81 31 80 96 98 00 	xrelease lock xorl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 81 31 80 96 98 00 	lock xacquire xorl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 81 31 80 96 98 00 	lock xrelease xorl \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 11 80 96 98 00 	xacquire lock adcq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 11 80 96 98 00 	xacquire lock adcq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 11 80 96 98 00 	xrelease lock adcq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 11 80 96 98 00 	xrelease lock adcq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 81 11 80 96 98 00 	lock xacquire adcq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 81 11 80 96 98 00 	lock xrelease adcq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 01 80 96 98 00 	xacquire lock addq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 01 80 96 98 00 	xacquire lock addq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 01 80 96 98 00 	xrelease lock addq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 01 80 96 98 00 	xrelease lock addq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 81 01 80 96 98 00 	lock xacquire addq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 81 01 80 96 98 00 	lock xrelease addq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 21 80 96 98 00 	xacquire lock andq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 21 80 96 98 00 	xacquire lock andq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 21 80 96 98 00 	xrelease lock andq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 21 80 96 98 00 	xrelease lock andq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 81 21 80 96 98 00 	lock xacquire andq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 81 21 80 96 98 00 	lock xrelease andq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 48 c7 01 80 96 98 00 	xrelease movq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 09 80 96 98 00 	xacquire lock orq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 09 80 96 98 00 	xacquire lock orq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 09 80 96 98 00 	xrelease lock orq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 09 80 96 98 00 	xrelease lock orq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 81 09 80 96 98 00 	lock xacquire orq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 81 09 80 96 98 00 	lock xrelease orq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 19 80 96 98 00 	xacquire lock sbbq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 19 80 96 98 00 	xacquire lock sbbq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 19 80 96 98 00 	xrelease lock sbbq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 19 80 96 98 00 	xrelease lock sbbq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 81 19 80 96 98 00 	lock xacquire sbbq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 81 19 80 96 98 00 	lock xrelease sbbq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 29 80 96 98 00 	xacquire lock subq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 29 80 96 98 00 	xacquire lock subq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 29 80 96 98 00 	xrelease lock subq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 29 80 96 98 00 	xrelease lock subq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 81 29 80 96 98 00 	lock xacquire subq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 81 29 80 96 98 00 	lock xrelease subq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 31 80 96 98 00 	xacquire lock xorq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 81 31 80 96 98 00 	xacquire lock xorq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 31 80 96 98 00 	xrelease lock xorq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 81 31 80 96 98 00 	xrelease lock xorq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 81 31 80 96 98 00 	lock xacquire xorq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 81 31 80 96 98 00 	lock xrelease xorq \$0x989680,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 11 64    	xacquire lock adcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 11 64    	xrelease lock adcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 11 64    	lock xacquire adcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 11 64    	lock xrelease adcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock addw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 01 64    	xacquire lock addw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock addw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 01 64    	xrelease lock addw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 01 64    	lock xacquire addw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 01 64    	lock xrelease addw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock andw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 21 64    	xacquire lock andw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock andw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 21 64    	xrelease lock andw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 21 64    	lock xacquire andw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 21 64    	lock xrelease andw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 39 64 	xacquire lock btcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 39 64 	xrelease lock btcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 39 64 	lock xacquire btcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 39 64 	lock xrelease btcw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btrw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 31 64 	xacquire lock btrw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btrw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 31 64 	xrelease lock btrw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 31 64 	lock xacquire btrw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 31 64 	lock xrelease btrw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock btsw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ba 29 64 	xacquire lock btsw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock btsw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ba 29 64 	xrelease lock btsw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ba 29 64 	lock xacquire btsw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ba 29 64 	lock xrelease btsw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 c7 01 64 00    	xrelease movw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock orw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 09 64    	xacquire lock orw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock orw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 09 64    	xrelease lock orw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 09 64    	lock xacquire orw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 09 64    	lock xrelease orw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbbw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 19 64    	xacquire lock sbbw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbbw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 19 64    	xrelease lock sbbw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 19 64    	lock xacquire sbbw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 19 64    	lock xrelease sbbw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock subw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 29 64    	xacquire lock subw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock subw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 29 64    	xrelease lock subw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 29 64    	lock xacquire subw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 29 64    	lock xrelease subw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xorw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 83 31 64    	xacquire lock xorw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xorw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 83 31 64    	xrelease lock xorw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 83 31 64    	lock xacquire xorw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 83 31 64    	lock xrelease xorw \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 11 64       	xacquire lock adcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 11 64       	xrelease lock adcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 11 64       	lock xacquire adcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 11 64       	lock xrelease adcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock addl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 01 64       	xacquire lock addl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock addl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 01 64       	xrelease lock addl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 01 64       	lock xacquire addl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 01 64       	lock xrelease addl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock andl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 21 64       	xacquire lock andl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock andl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 21 64       	xrelease lock andl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 21 64       	lock xacquire andl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 21 64       	lock xrelease andl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 39 64    	xacquire lock btcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 39 64    	xrelease lock btcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 39 64    	lock xacquire btcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 39 64    	lock xrelease btcl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btrl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 31 64    	xacquire lock btrl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btrl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 31 64    	xrelease lock btrl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 31 64    	lock xacquire btrl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 31 64    	lock xrelease btrl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock btsl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ba 29 64    	xacquire lock btsl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock btsl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ba 29 64    	xrelease lock btsl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ba 29 64    	lock xacquire btsl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ba 29 64    	lock xrelease btsl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 c7 01 64 00 00 00 	xrelease movl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock orl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 09 64       	xacquire lock orl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock orl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 09 64       	xrelease lock orl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 09 64       	lock xacquire orl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 09 64       	lock xrelease orl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbbl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 19 64       	xacquire lock sbbl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbbl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 19 64       	xrelease lock sbbl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 19 64       	lock xacquire sbbl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 19 64       	lock xrelease sbbl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock subl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 29 64       	xacquire lock subl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock subl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 29 64       	xrelease lock subl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 29 64       	lock xacquire subl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 29 64       	lock xrelease subl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xorl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 83 31 64       	xacquire lock xorl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xorl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 83 31 64       	xrelease lock xorl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 83 31 64       	lock xacquire xorl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 83 31 64       	lock xrelease xorl \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 11 64    	xacquire lock adcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 11 64    	xacquire lock adcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 11 64    	xrelease lock adcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 11 64    	xrelease lock adcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 83 11 64    	lock xacquire adcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 83 11 64    	lock xrelease adcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 01 64    	xacquire lock addq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 01 64    	xacquire lock addq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 01 64    	xrelease lock addq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 01 64    	xrelease lock addq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 83 01 64    	lock xacquire addq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 83 01 64    	lock xrelease addq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 21 64    	xacquire lock andq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 21 64    	xacquire lock andq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 21 64    	xrelease lock andq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 21 64    	xrelease lock andq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 83 21 64    	lock xacquire andq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 83 21 64    	lock xrelease andq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 39 64 	xacquire lock btcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 39 64 	xacquire lock btcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 39 64 	xrelease lock btcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 39 64 	xrelease lock btcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ba 39 64 	lock xacquire btcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ba 39 64 	lock xrelease btcq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 31 64 	xacquire lock btrq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 31 64 	xacquire lock btrq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 31 64 	xrelease lock btrq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 31 64 	xrelease lock btrq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ba 31 64 	lock xacquire btrq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ba 31 64 	lock xrelease btrq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 29 64 	xacquire lock btsq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ba 29 64 	xacquire lock btsq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 29 64 	xrelease lock btsq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ba 29 64 	xrelease lock btsq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ba 29 64 	lock xacquire btsq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ba 29 64 	lock xrelease btsq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 48 c7 01 64 00 00 00 	xrelease movq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 09 64    	xacquire lock orq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 09 64    	xacquire lock orq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 09 64    	xrelease lock orq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 09 64    	xrelease lock orq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 83 09 64    	lock xacquire orq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 83 09 64    	lock xrelease orq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 19 64    	xacquire lock sbbq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 19 64    	xacquire lock sbbq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 19 64    	xrelease lock sbbq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 19 64    	xrelease lock sbbq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 83 19 64    	lock xacquire sbbq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 83 19 64    	lock xrelease sbbq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 29 64    	xacquire lock subq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 29 64    	xacquire lock subq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 29 64    	xrelease lock subq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 29 64    	xrelease lock subq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 83 29 64    	lock xacquire subq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 83 29 64    	lock xrelease subq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 31 64    	xacquire lock xorq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 83 31 64    	xacquire lock xorq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 31 64    	xrelease lock xorq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 83 31 64    	xrelease lock xorq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 83 31 64    	lock xacquire xorq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 83 31 64    	lock xrelease xorq \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 11 64       	xacquire lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 11 64       	xrelease lock adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 11 64       	lock xacquire adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 11 64       	lock xrelease adcb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 01 64       	xacquire lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 01 64       	xrelease lock addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 01 64       	lock xacquire addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 01 64       	lock xrelease addb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 21 64       	xacquire lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 21 64       	xrelease lock andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 21 64       	lock xacquire andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 21 64       	lock xrelease andb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 c6 01 64          	xrelease movb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 09 64       	xacquire lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 09 64       	xrelease lock orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 09 64       	lock xacquire orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 09 64       	lock xrelease orb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 19 64       	xacquire lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 19 64       	xrelease lock sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 19 64       	lock xacquire sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 19 64       	lock xrelease sbbb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 29 64       	xacquire lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 29 64       	xrelease lock subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 29 64       	lock xacquire subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 29 64       	lock xrelease subb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 80 31 64       	xacquire lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 80 31 64       	xrelease lock xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 80 31 64       	lock xacquire xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 80 31 64       	lock xrelease xorb \$0x64,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 10 01          	xacquire lock adc %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 10 01          	xrelease lock adc %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 10 01          	lock xacquire adc %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 10 01          	lock xrelease adc %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 00 01          	xacquire lock add %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 00 01          	xrelease lock add %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 00 01          	lock xacquire add %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 00 01          	lock xrelease add %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 20 01          	xacquire lock and %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 20 01          	xrelease lock and %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 20 01          	lock xacquire and %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 20 01          	lock xrelease and %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 88 01             	xrelease mov %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 08 01          	xacquire lock or %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 08 01          	xrelease lock or %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 08 01          	lock xacquire or %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 08 01          	lock xrelease or %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 18 01          	xacquire lock sbb %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 18 01          	xrelease lock sbb %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 18 01          	lock xacquire sbb %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 18 01          	lock xrelease sbb %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 28 01          	xacquire lock sub %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 28 01          	xrelease lock sub %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 28 01          	lock xacquire sub %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 28 01          	lock xrelease sub %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 86 01          	xacquire lock xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 86 01             	xacquire xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 86 01          	xrelease lock xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 86 01             	xrelease xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 86 01          	lock xacquire xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 86 01          	lock xrelease xchg %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 30 01          	xacquire lock xor %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 30 01          	xrelease lock xor %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 30 01          	lock xacquire xor %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 30 01          	lock xrelease xor %al,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 11 01       	xacquire lock adc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 11 01       	xrelease lock adc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 11 01       	lock xacquire adc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 11 01       	lock xrelease adc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 01 01       	xacquire lock add %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 01 01       	xrelease lock add %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 01 01       	lock xacquire add %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 01 01       	lock xrelease add %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 21 01       	xacquire lock and %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 21 01       	xrelease lock and %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 21 01       	lock xacquire and %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 21 01       	lock xrelease and %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 89 01          	xrelease mov %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 09 01       	xacquire lock or %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 09 01       	xrelease lock or %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 09 01       	lock xacquire or %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 09 01       	lock xrelease or %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 19 01       	xacquire lock sbb %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 19 01       	xrelease lock sbb %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 19 01       	lock xacquire sbb %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 19 01       	lock xrelease sbb %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 29 01       	xacquire lock sub %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 29 01       	xrelease lock sub %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 29 01       	lock xacquire sub %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 29 01       	lock xrelease sub %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 87 01       	xacquire lock xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 87 01          	xacquire xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 87 01       	xrelease lock xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 87 01          	xrelease xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 87 01       	lock xacquire xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 87 01       	lock xrelease xchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 31 01       	xacquire lock xor %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 31 01       	xrelease lock xor %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 31 01       	lock xacquire xor %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 31 01       	lock xrelease xor %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 11 01          	xacquire lock adc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 11 01          	xrelease lock adc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 11 01          	lock xacquire adc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 11 01          	lock xrelease adc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 01 01          	xacquire lock add %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 01 01          	xrelease lock add %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 01 01          	lock xacquire add %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 01 01          	lock xrelease add %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 21 01          	xacquire lock and %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 21 01          	xrelease lock and %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 21 01          	lock xacquire and %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 21 01          	lock xrelease and %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 89 01             	xrelease mov %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 09 01          	xacquire lock or %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 09 01          	xrelease lock or %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 09 01          	lock xacquire or %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 09 01          	lock xrelease or %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 19 01          	xacquire lock sbb %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 19 01          	xrelease lock sbb %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 19 01          	lock xacquire sbb %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 19 01          	lock xrelease sbb %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 29 01          	xacquire lock sub %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 29 01          	xrelease lock sub %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 29 01          	lock xacquire sub %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 29 01          	lock xrelease sub %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 87 01          	xacquire lock xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 87 01             	xacquire xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 87 01          	xrelease lock xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 87 01             	xrelease xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 87 01          	lock xacquire xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 87 01          	lock xrelease xchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 31 01          	xacquire lock xor %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 31 01          	xrelease lock xor %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 31 01          	lock xacquire xor %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 31 01          	lock xrelease xor %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 11 01       	xacquire lock adc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 11 01       	xacquire lock adc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 11 01       	xrelease lock adc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 11 01       	xrelease lock adc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 11 01       	lock xacquire adc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 11 01       	lock xrelease adc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 01 01       	xacquire lock add %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 01 01       	xacquire lock add %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 01 01       	xrelease lock add %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 01 01       	xrelease lock add %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 01 01       	lock xacquire add %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 01 01       	lock xrelease add %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 21 01       	xacquire lock and %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 21 01       	xacquire lock and %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 21 01       	xrelease lock and %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 21 01       	xrelease lock and %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 21 01       	lock xacquire and %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 21 01       	lock xrelease and %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 48 89 01          	xrelease mov %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 09 01       	xacquire lock or %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 09 01       	xacquire lock or %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 09 01       	xrelease lock or %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 09 01       	xrelease lock or %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 09 01       	lock xacquire or %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 09 01       	lock xrelease or %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 19 01       	xacquire lock sbb %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 19 01       	xacquire lock sbb %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 19 01       	xrelease lock sbb %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 19 01       	xrelease lock sbb %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 19 01       	lock xacquire sbb %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 19 01       	lock xrelease sbb %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 29 01       	xacquire lock sub %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 29 01       	xacquire lock sub %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 29 01       	xrelease lock sub %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 29 01       	xrelease lock sub %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 29 01       	lock xacquire sub %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 29 01       	lock xrelease sub %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 87 01       	xacquire lock xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 87 01       	xacquire lock xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 48 87 01          	xacquire xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 87 01       	xrelease lock xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 87 01       	xrelease lock xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 48 87 01          	xrelease xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 87 01       	lock xacquire xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 87 01       	lock xrelease xchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 31 01       	xacquire lock xor %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 31 01       	xacquire lock xor %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 31 01       	xrelease lock xor %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 31 01       	xrelease lock xor %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 31 01       	lock xacquire xor %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 31 01       	lock xrelease xor %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f bb 01    	xacquire lock btc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f bb 01    	xrelease lock btc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f bb 01    	lock xacquire btc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f bb 01    	lock xrelease btc %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b3 01    	xacquire lock btr %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b3 01    	xrelease lock btr %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b3 01    	lock xacquire btr %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b3 01    	lock xrelease btr %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f ab 01    	xacquire lock bts %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f ab 01    	xrelease lock bts %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f ab 01    	lock xacquire bts %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f ab 01    	lock xrelease bts %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f b1 01    	xacquire lock cmpxchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f b1 01    	xrelease lock cmpxchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f b1 01    	lock xacquire cmpxchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f b1 01    	lock xrelease cmpxchg %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 0f c1 01    	xacquire lock xadd %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 0f c1 01    	xrelease lock xadd %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 0f c1 01    	lock xacquire xadd %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 0f c1 01    	lock xrelease xadd %ax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f bb 01       	xacquire lock btc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f bb 01       	xrelease lock btc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f bb 01       	lock xacquire btc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f bb 01       	lock xrelease btc %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b3 01       	xacquire lock btr %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b3 01       	xrelease lock btr %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f b3 01       	lock xacquire btr %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f b3 01       	lock xrelease btr %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f ab 01       	xacquire lock bts %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f ab 01       	xrelease lock bts %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f ab 01       	lock xacquire bts %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f ab 01       	lock xrelease bts %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b1 01       	xacquire lock cmpxchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b1 01       	xrelease lock cmpxchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f b1 01       	lock xacquire cmpxchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f b1 01       	lock xrelease cmpxchg %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c1 01       	xacquire lock xadd %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c1 01       	xrelease lock xadd %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f c1 01       	lock xacquire xadd %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f c1 01       	lock xrelease xadd %eax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f bb 01    	xacquire lock btc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f bb 01    	xacquire lock btc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f bb 01    	xrelease lock btc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f bb 01    	xrelease lock btc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f bb 01    	lock xacquire btc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f bb 01    	lock xrelease btc %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b3 01    	xacquire lock btr %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b3 01    	xacquire lock btr %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b3 01    	xrelease lock btr %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b3 01    	xrelease lock btr %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f b3 01    	lock xacquire btr %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f b3 01    	lock xrelease btr %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ab 01    	xacquire lock bts %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f ab 01    	xacquire lock bts %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ab 01    	xrelease lock bts %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f ab 01    	xrelease lock bts %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f ab 01    	lock xacquire bts %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f ab 01    	lock xrelease bts %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b1 01    	xacquire lock cmpxchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f b1 01    	xacquire lock cmpxchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b1 01    	xrelease lock cmpxchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f b1 01    	xrelease lock cmpxchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f b1 01    	lock xacquire cmpxchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f b1 01    	lock xrelease cmpxchg %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f c1 01    	xacquire lock xadd %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 0f c1 01    	xacquire lock xadd %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f c1 01    	xrelease lock xadd %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 0f c1 01    	xrelease lock xadd %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 0f c1 01    	lock xacquire xadd %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 0f c1 01    	lock xrelease xadd %rax,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock decb \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 09          	xacquire lock decb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock decb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 09          	xrelease lock decb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 fe 09          	lock xacquire decb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 fe 09          	lock xrelease decb \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock incb \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 fe 01          	xacquire lock incb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock incb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 fe 01          	xrelease lock incb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 fe 01          	lock xacquire incb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 fe 01          	lock xrelease incb \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock negb \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 19          	xacquire lock negb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock negb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 19          	xrelease lock negb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 f6 19          	lock xacquire negb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 f6 19          	lock xrelease negb \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock notb \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f6 11          	xacquire lock notb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock notb \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f6 11          	xrelease lock notb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 f6 11          	lock xacquire notb \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 f6 11          	lock xrelease notb \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock decw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 09       	xacquire lock decw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock decw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 09       	xrelease lock decw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 09       	lock xacquire decw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 09       	lock xrelease decw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock incw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 ff 01       	xacquire lock incw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock incw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 ff 01       	xrelease lock incw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 ff 01       	lock xacquire incw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 ff 01       	lock xrelease incw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock negw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 19       	xacquire lock negw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock negw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 19       	xrelease lock negw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 19       	lock xacquire negw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 19       	lock xrelease negw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock notw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f2 f0 f7 11       	xacquire lock notw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock notw \(%rcx\)
+[ 	]*[a-f0-9]+:	66 f3 f0 f7 11       	xrelease lock notw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 66 f7 11       	lock xacquire notw \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 66 f7 11       	lock xrelease notw \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock decl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 09          	xacquire lock decl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock decl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 09          	xrelease lock decl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 ff 09          	lock xacquire decl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 ff 09          	lock xrelease decl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock incl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 ff 01          	xacquire lock incl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock incl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 ff 01          	xrelease lock incl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 ff 01          	lock xacquire incl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 ff 01          	lock xrelease incl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock negl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 19          	xacquire lock negl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock negl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 19          	xrelease lock negl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 f7 19          	lock xacquire negl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 f7 19          	lock xrelease negl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock notl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 f7 11          	xacquire lock notl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock notl \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 f7 11          	xrelease lock notl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 f7 11          	lock xacquire notl \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 f7 11          	lock xrelease notl \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 09       	xacquire lock decq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 09       	xacquire lock decq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 09       	xrelease lock decq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 09       	xrelease lock decq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 ff 09       	lock xacquire decq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 ff 09       	lock xrelease decq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 01       	xacquire lock incq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 ff 01       	xacquire lock incq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 01       	xrelease lock incq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 ff 01       	xrelease lock incq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 ff 01       	lock xacquire incq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 ff 01       	lock xrelease incq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 19       	xacquire lock negq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 19       	xacquire lock negq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 19       	xrelease lock negq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 19       	xrelease lock negq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 f7 19       	lock xacquire negq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 f7 19       	lock xrelease negq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 11       	xacquire lock notq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 48 f7 11       	xacquire lock notq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 11       	xrelease lock notq \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 48 f7 11       	xrelease lock notq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 48 f7 11       	lock xacquire notq \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 48 f7 11       	lock xrelease notq \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c7 09       	xacquire lock cmpxchg8b \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b \(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c7 09       	xrelease lock cmpxchg8b \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f c7 09       	lock xacquire cmpxchg8b \(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f c7 09       	lock xrelease cmpxchg8b \(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f b0 09       	xacquire lock cmpxchg %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f b0 09       	xrelease lock cmpxchg %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f b0 09       	lock xacquire cmpxchg %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f b0 09       	lock xrelease cmpxchg %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f2 f0 0f c0 09       	xacquire lock xadd %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f3 f0 0f c0 09       	xrelease lock xadd %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f2 0f c0 09       	lock xacquire xadd %cl,\(%rcx\)
+[ 	]*[a-f0-9]+:	f0 f3 0f c0 09       	lock xrelease xadd %cl,\(%rcx\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-hle.s b/gas/testsuite/gas/i386/x86-64-hle.s
new file mode 100644
index 0000000..82dec07
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-hle.s
@@ -0,0 +1,1717 @@
+# Check 64bit HLE instructions
+
+	.allow_index_reg
+	.text
+_start:
+
+
+# Tests for op imm32 rax
+
+# Tests for op imm8 regb/m8
+	xacquire lock adcb $100,(%rcx)
+	lock xacquire adcb $100,(%rcx)
+	xrelease lock adcb $100,(%rcx)
+	lock xrelease adcb $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; adcb $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; adcb $100,(%rcx)
+	xacquire lock addb $100,(%rcx)
+	lock xacquire addb $100,(%rcx)
+	xrelease lock addb $100,(%rcx)
+	lock xrelease addb $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; addb $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; addb $100,(%rcx)
+	xacquire lock andb $100,(%rcx)
+	lock xacquire andb $100,(%rcx)
+	xrelease lock andb $100,(%rcx)
+	lock xrelease andb $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; andb $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; andb $100,(%rcx)
+	xrelease movb $100,(%rcx)
+	xacquire lock orb $100,(%rcx)
+	lock xacquire orb $100,(%rcx)
+	xrelease lock orb $100,(%rcx)
+	lock xrelease orb $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; orb $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; orb $100,(%rcx)
+	xacquire lock sbbb $100,(%rcx)
+	lock xacquire sbbb $100,(%rcx)
+	xrelease lock sbbb $100,(%rcx)
+	lock xrelease sbbb $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; sbbb $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; sbbb $100,(%rcx)
+	xacquire lock subb $100,(%rcx)
+	lock xacquire subb $100,(%rcx)
+	xrelease lock subb $100,(%rcx)
+	lock xrelease subb $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; subb $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; subb $100,(%rcx)
+	xacquire lock xorb $100,(%rcx)
+	lock xacquire xorb $100,(%rcx)
+	xrelease lock xorb $100,(%rcx)
+	lock xrelease xorb $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; xorb $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; xorb $100,(%rcx)
+
+# Tests for op imm16 regs/m16
+	xacquire lock adcw $1000,(%rcx)
+	lock xacquire adcw $1000,(%rcx)
+	xrelease lock adcw $1000,(%rcx)
+	lock xrelease adcw $1000,(%rcx)
+	.byte 0xf0; .byte 0xf2; adcw $1000,(%rcx)
+	.byte 0xf0; .byte 0xf3; adcw $1000,(%rcx)
+	xacquire lock addw $1000,(%rcx)
+	lock xacquire addw $1000,(%rcx)
+	xrelease lock addw $1000,(%rcx)
+	lock xrelease addw $1000,(%rcx)
+	.byte 0xf0; .byte 0xf2; addw $1000,(%rcx)
+	.byte 0xf0; .byte 0xf3; addw $1000,(%rcx)
+	xacquire lock andw $1000,(%rcx)
+	lock xacquire andw $1000,(%rcx)
+	xrelease lock andw $1000,(%rcx)
+	lock xrelease andw $1000,(%rcx)
+	.byte 0xf0; .byte 0xf2; andw $1000,(%rcx)
+	.byte 0xf0; .byte 0xf3; andw $1000,(%rcx)
+	xrelease movw $1000,(%rcx)
+	xacquire lock orw $1000,(%rcx)
+	lock xacquire orw $1000,(%rcx)
+	xrelease lock orw $1000,(%rcx)
+	lock xrelease orw $1000,(%rcx)
+	.byte 0xf0; .byte 0xf2; orw $1000,(%rcx)
+	.byte 0xf0; .byte 0xf3; orw $1000,(%rcx)
+	xacquire lock sbbw $1000,(%rcx)
+	lock xacquire sbbw $1000,(%rcx)
+	xrelease lock sbbw $1000,(%rcx)
+	lock xrelease sbbw $1000,(%rcx)
+	.byte 0xf0; .byte 0xf2; sbbw $1000,(%rcx)
+	.byte 0xf0; .byte 0xf3; sbbw $1000,(%rcx)
+	xacquire lock subw $1000,(%rcx)
+	lock xacquire subw $1000,(%rcx)
+	xrelease lock subw $1000,(%rcx)
+	lock xrelease subw $1000,(%rcx)
+	.byte 0xf0; .byte 0xf2; subw $1000,(%rcx)
+	.byte 0xf0; .byte 0xf3; subw $1000,(%rcx)
+	xacquire lock xorw $1000,(%rcx)
+	lock xacquire xorw $1000,(%rcx)
+	xrelease lock xorw $1000,(%rcx)
+	lock xrelease xorw $1000,(%rcx)
+	.byte 0xf0; .byte 0xf2; xorw $1000,(%rcx)
+	.byte 0xf0; .byte 0xf3; xorw $1000,(%rcx)
+
+# Tests for op imm32 regl/m32
+	xacquire lock adcl $10000000,(%rcx)
+	lock xacquire adcl $10000000,(%rcx)
+	xrelease lock adcl $10000000,(%rcx)
+	lock xrelease adcl $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf2; adcl $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf3; adcl $10000000,(%rcx)
+	xacquire lock addl $10000000,(%rcx)
+	lock xacquire addl $10000000,(%rcx)
+	xrelease lock addl $10000000,(%rcx)
+	lock xrelease addl $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf2; addl $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf3; addl $10000000,(%rcx)
+	xacquire lock andl $10000000,(%rcx)
+	lock xacquire andl $10000000,(%rcx)
+	xrelease lock andl $10000000,(%rcx)
+	lock xrelease andl $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf2; andl $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf3; andl $10000000,(%rcx)
+	xrelease movl $10000000,(%rcx)
+	xacquire lock orl $10000000,(%rcx)
+	lock xacquire orl $10000000,(%rcx)
+	xrelease lock orl $10000000,(%rcx)
+	lock xrelease orl $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf2; orl $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf3; orl $10000000,(%rcx)
+	xacquire lock sbbl $10000000,(%rcx)
+	lock xacquire sbbl $10000000,(%rcx)
+	xrelease lock sbbl $10000000,(%rcx)
+	lock xrelease sbbl $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf2; sbbl $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf3; sbbl $10000000,(%rcx)
+	xacquire lock subl $10000000,(%rcx)
+	lock xacquire subl $10000000,(%rcx)
+	xrelease lock subl $10000000,(%rcx)
+	lock xrelease subl $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf2; subl $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf3; subl $10000000,(%rcx)
+	xacquire lock xorl $10000000,(%rcx)
+	lock xacquire xorl $10000000,(%rcx)
+	xrelease lock xorl $10000000,(%rcx)
+	lock xrelease xorl $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf2; xorl $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf3; xorl $10000000,(%rcx)
+
+# Tests for op imm32 regq/m64
+	xacquire lock adcq $10000000,(%rcx)
+	lock xacquire adcq $10000000,(%rcx)
+	xrelease lock adcq $10000000,(%rcx)
+	lock xrelease adcq $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf2; adcq $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf3; adcq $10000000,(%rcx)
+	xacquire lock addq $10000000,(%rcx)
+	lock xacquire addq $10000000,(%rcx)
+	xrelease lock addq $10000000,(%rcx)
+	lock xrelease addq $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf2; addq $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf3; addq $10000000,(%rcx)
+	xacquire lock andq $10000000,(%rcx)
+	lock xacquire andq $10000000,(%rcx)
+	xrelease lock andq $10000000,(%rcx)
+	lock xrelease andq $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf2; andq $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf3; andq $10000000,(%rcx)
+	xrelease movq $10000000,(%rcx)
+	xacquire lock orq $10000000,(%rcx)
+	lock xacquire orq $10000000,(%rcx)
+	xrelease lock orq $10000000,(%rcx)
+	lock xrelease orq $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf2; orq $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf3; orq $10000000,(%rcx)
+	xacquire lock sbbq $10000000,(%rcx)
+	lock xacquire sbbq $10000000,(%rcx)
+	xrelease lock sbbq $10000000,(%rcx)
+	lock xrelease sbbq $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf2; sbbq $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf3; sbbq $10000000,(%rcx)
+	xacquire lock subq $10000000,(%rcx)
+	lock xacquire subq $10000000,(%rcx)
+	xrelease lock subq $10000000,(%rcx)
+	lock xrelease subq $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf2; subq $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf3; subq $10000000,(%rcx)
+	xacquire lock xorq $10000000,(%rcx)
+	lock xacquire xorq $10000000,(%rcx)
+	xrelease lock xorq $10000000,(%rcx)
+	lock xrelease xorq $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf2; xorq $10000000,(%rcx)
+	.byte 0xf0; .byte 0xf3; xorq $10000000,(%rcx)
+
+# Tests for op imm8 regs/m16
+	xacquire lock adcw $100,(%rcx)
+	lock xacquire adcw $100,(%rcx)
+	xrelease lock adcw $100,(%rcx)
+	lock xrelease adcw $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; adcw $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; adcw $100,(%rcx)
+	xacquire lock addw $100,(%rcx)
+	lock xacquire addw $100,(%rcx)
+	xrelease lock addw $100,(%rcx)
+	lock xrelease addw $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; addw $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; addw $100,(%rcx)
+	xacquire lock andw $100,(%rcx)
+	lock xacquire andw $100,(%rcx)
+	xrelease lock andw $100,(%rcx)
+	lock xrelease andw $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; andw $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; andw $100,(%rcx)
+	xacquire lock btcw $100,(%rcx)
+	lock xacquire btcw $100,(%rcx)
+	xrelease lock btcw $100,(%rcx)
+	lock xrelease btcw $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; btcw $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; btcw $100,(%rcx)
+	xacquire lock btrw $100,(%rcx)
+	lock xacquire btrw $100,(%rcx)
+	xrelease lock btrw $100,(%rcx)
+	lock xrelease btrw $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; btrw $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; btrw $100,(%rcx)
+	xacquire lock btsw $100,(%rcx)
+	lock xacquire btsw $100,(%rcx)
+	xrelease lock btsw $100,(%rcx)
+	lock xrelease btsw $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; btsw $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; btsw $100,(%rcx)
+	xrelease movw $100,(%rcx)
+	xacquire lock orw $100,(%rcx)
+	lock xacquire orw $100,(%rcx)
+	xrelease lock orw $100,(%rcx)
+	lock xrelease orw $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; orw $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; orw $100,(%rcx)
+	xacquire lock sbbw $100,(%rcx)
+	lock xacquire sbbw $100,(%rcx)
+	xrelease lock sbbw $100,(%rcx)
+	lock xrelease sbbw $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; sbbw $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; sbbw $100,(%rcx)
+	xacquire lock subw $100,(%rcx)
+	lock xacquire subw $100,(%rcx)
+	xrelease lock subw $100,(%rcx)
+	lock xrelease subw $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; subw $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; subw $100,(%rcx)
+	xacquire lock xorw $100,(%rcx)
+	lock xacquire xorw $100,(%rcx)
+	xrelease lock xorw $100,(%rcx)
+	lock xrelease xorw $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; xorw $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; xorw $100,(%rcx)
+
+# Tests for op imm8 regl/m32
+	xacquire lock adcl $100,(%rcx)
+	lock xacquire adcl $100,(%rcx)
+	xrelease lock adcl $100,(%rcx)
+	lock xrelease adcl $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; adcl $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; adcl $100,(%rcx)
+	xacquire lock addl $100,(%rcx)
+	lock xacquire addl $100,(%rcx)
+	xrelease lock addl $100,(%rcx)
+	lock xrelease addl $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; addl $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; addl $100,(%rcx)
+	xacquire lock andl $100,(%rcx)
+	lock xacquire andl $100,(%rcx)
+	xrelease lock andl $100,(%rcx)
+	lock xrelease andl $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; andl $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; andl $100,(%rcx)
+	xacquire lock btcl $100,(%rcx)
+	lock xacquire btcl $100,(%rcx)
+	xrelease lock btcl $100,(%rcx)
+	lock xrelease btcl $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; btcl $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; btcl $100,(%rcx)
+	xacquire lock btrl $100,(%rcx)
+	lock xacquire btrl $100,(%rcx)
+	xrelease lock btrl $100,(%rcx)
+	lock xrelease btrl $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; btrl $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; btrl $100,(%rcx)
+	xacquire lock btsl $100,(%rcx)
+	lock xacquire btsl $100,(%rcx)
+	xrelease lock btsl $100,(%rcx)
+	lock xrelease btsl $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; btsl $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; btsl $100,(%rcx)
+	xrelease movl $100,(%rcx)
+	xacquire lock orl $100,(%rcx)
+	lock xacquire orl $100,(%rcx)
+	xrelease lock orl $100,(%rcx)
+	lock xrelease orl $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; orl $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; orl $100,(%rcx)
+	xacquire lock sbbl $100,(%rcx)
+	lock xacquire sbbl $100,(%rcx)
+	xrelease lock sbbl $100,(%rcx)
+	lock xrelease sbbl $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; sbbl $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; sbbl $100,(%rcx)
+	xacquire lock subl $100,(%rcx)
+	lock xacquire subl $100,(%rcx)
+	xrelease lock subl $100,(%rcx)
+	lock xrelease subl $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; subl $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; subl $100,(%rcx)
+	xacquire lock xorl $100,(%rcx)
+	lock xacquire xorl $100,(%rcx)
+	xrelease lock xorl $100,(%rcx)
+	lock xrelease xorl $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; xorl $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; xorl $100,(%rcx)
+
+# Tests for op imm8 regq/m64
+	xacquire lock adcq $100,(%rcx)
+	lock xacquire adcq $100,(%rcx)
+	xrelease lock adcq $100,(%rcx)
+	lock xrelease adcq $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; adcq $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; adcq $100,(%rcx)
+	xacquire lock addq $100,(%rcx)
+	lock xacquire addq $100,(%rcx)
+	xrelease lock addq $100,(%rcx)
+	lock xrelease addq $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; addq $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; addq $100,(%rcx)
+	xacquire lock andq $100,(%rcx)
+	lock xacquire andq $100,(%rcx)
+	xrelease lock andq $100,(%rcx)
+	lock xrelease andq $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; andq $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; andq $100,(%rcx)
+	xacquire lock btcq $100,(%rcx)
+	lock xacquire btcq $100,(%rcx)
+	xrelease lock btcq $100,(%rcx)
+	lock xrelease btcq $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; btcq $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; btcq $100,(%rcx)
+	xacquire lock btrq $100,(%rcx)
+	lock xacquire btrq $100,(%rcx)
+	xrelease lock btrq $100,(%rcx)
+	lock xrelease btrq $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; btrq $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; btrq $100,(%rcx)
+	xacquire lock btsq $100,(%rcx)
+	lock xacquire btsq $100,(%rcx)
+	xrelease lock btsq $100,(%rcx)
+	lock xrelease btsq $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; btsq $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; btsq $100,(%rcx)
+	xrelease movq $100,(%rcx)
+	xacquire lock orq $100,(%rcx)
+	lock xacquire orq $100,(%rcx)
+	xrelease lock orq $100,(%rcx)
+	lock xrelease orq $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; orq $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; orq $100,(%rcx)
+	xacquire lock sbbq $100,(%rcx)
+	lock xacquire sbbq $100,(%rcx)
+	xrelease lock sbbq $100,(%rcx)
+	lock xrelease sbbq $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; sbbq $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; sbbq $100,(%rcx)
+	xacquire lock subq $100,(%rcx)
+	lock xacquire subq $100,(%rcx)
+	xrelease lock subq $100,(%rcx)
+	lock xrelease subq $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; subq $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; subq $100,(%rcx)
+	xacquire lock xorq $100,(%rcx)
+	lock xacquire xorq $100,(%rcx)
+	xrelease lock xorq $100,(%rcx)
+	lock xrelease xorq $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; xorq $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; xorq $100,(%rcx)
+
+# Tests for op imm8 regb/m8
+	xacquire lock adcb $100,(%rcx)
+	lock xacquire adcb $100,(%rcx)
+	xrelease lock adcb $100,(%rcx)
+	lock xrelease adcb $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; adcb $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; adcb $100,(%rcx)
+	xacquire lock addb $100,(%rcx)
+	lock xacquire addb $100,(%rcx)
+	xrelease lock addb $100,(%rcx)
+	lock xrelease addb $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; addb $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; addb $100,(%rcx)
+	xacquire lock andb $100,(%rcx)
+	lock xacquire andb $100,(%rcx)
+	xrelease lock andb $100,(%rcx)
+	lock xrelease andb $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; andb $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; andb $100,(%rcx)
+	xrelease movb $100,(%rcx)
+	xacquire lock orb $100,(%rcx)
+	lock xacquire orb $100,(%rcx)
+	xrelease lock orb $100,(%rcx)
+	lock xrelease orb $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; orb $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; orb $100,(%rcx)
+	xacquire lock sbbb $100,(%rcx)
+	lock xacquire sbbb $100,(%rcx)
+	xrelease lock sbbb $100,(%rcx)
+	lock xrelease sbbb $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; sbbb $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; sbbb $100,(%rcx)
+	xacquire lock subb $100,(%rcx)
+	lock xacquire subb $100,(%rcx)
+	xrelease lock subb $100,(%rcx)
+	lock xrelease subb $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; subb $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; subb $100,(%rcx)
+	xacquire lock xorb $100,(%rcx)
+	lock xacquire xorb $100,(%rcx)
+	xrelease lock xorb $100,(%rcx)
+	lock xrelease xorb $100,(%rcx)
+	.byte 0xf0; .byte 0xf2; xorb $100,(%rcx)
+	.byte 0xf0; .byte 0xf3; xorb $100,(%rcx)
+
+# Tests for op regb regb/m8
+# Tests for op regb/m8 regb
+	xacquire lock adcb %al,(%rcx)
+	lock xacquire adcb %al,(%rcx)
+	xrelease lock adcb %al,(%rcx)
+	lock xrelease adcb %al,(%rcx)
+	.byte 0xf0; .byte 0xf2; adcb %al,(%rcx)
+	.byte 0xf0; .byte 0xf3; adcb %al,(%rcx)
+	xacquire lock addb %al,(%rcx)
+	lock xacquire addb %al,(%rcx)
+	xrelease lock addb %al,(%rcx)
+	lock xrelease addb %al,(%rcx)
+	.byte 0xf0; .byte 0xf2; addb %al,(%rcx)
+	.byte 0xf0; .byte 0xf3; addb %al,(%rcx)
+	xacquire lock andb %al,(%rcx)
+	lock xacquire andb %al,(%rcx)
+	xrelease lock andb %al,(%rcx)
+	lock xrelease andb %al,(%rcx)
+	.byte 0xf0; .byte 0xf2; andb %al,(%rcx)
+	.byte 0xf0; .byte 0xf3; andb %al,(%rcx)
+	xrelease movb %al,(%rcx)
+	xacquire lock orb %al,(%rcx)
+	lock xacquire orb %al,(%rcx)
+	xrelease lock orb %al,(%rcx)
+	lock xrelease orb %al,(%rcx)
+	.byte 0xf0; .byte 0xf2; orb %al,(%rcx)
+	.byte 0xf0; .byte 0xf3; orb %al,(%rcx)
+	xacquire lock sbbb %al,(%rcx)
+	lock xacquire sbbb %al,(%rcx)
+	xrelease lock sbbb %al,(%rcx)
+	lock xrelease sbbb %al,(%rcx)
+	.byte 0xf0; .byte 0xf2; sbbb %al,(%rcx)
+	.byte 0xf0; .byte 0xf3; sbbb %al,(%rcx)
+	xacquire lock subb %al,(%rcx)
+	lock xacquire subb %al,(%rcx)
+	xrelease lock subb %al,(%rcx)
+	lock xrelease subb %al,(%rcx)
+	.byte 0xf0; .byte 0xf2; subb %al,(%rcx)
+	.byte 0xf0; .byte 0xf3; subb %al,(%rcx)
+	xacquire lock xchgb %al,(%rcx)
+	lock xacquire xchgb %al,(%rcx)
+	xacquire xchgb %al,(%rcx)
+	xrelease lock xchgb %al,(%rcx)
+	lock xrelease xchgb %al,(%rcx)
+	xrelease xchgb %al,(%rcx)
+	.byte 0xf0; .byte 0xf2; xchgb %al,(%rcx)
+	.byte 0xf0; .byte 0xf3; xchgb %al,(%rcx)
+	xacquire lock xorb %al,(%rcx)
+	lock xacquire xorb %al,(%rcx)
+	xrelease lock xorb %al,(%rcx)
+	lock xrelease xorb %al,(%rcx)
+	.byte 0xf0; .byte 0xf2; xorb %al,(%rcx)
+	.byte 0xf0; .byte 0xf3; xorb %al,(%rcx)
+
+# Tests for op regs regs/m16
+# Tests for op regs/m16 regs
+	xacquire lock adcw %ax,(%rcx)
+	lock xacquire adcw %ax,(%rcx)
+	xrelease lock adcw %ax,(%rcx)
+	lock xrelease adcw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf2; adcw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf3; adcw %ax,(%rcx)
+	xacquire lock addw %ax,(%rcx)
+	lock xacquire addw %ax,(%rcx)
+	xrelease lock addw %ax,(%rcx)
+	lock xrelease addw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf2; addw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf3; addw %ax,(%rcx)
+	xacquire lock andw %ax,(%rcx)
+	lock xacquire andw %ax,(%rcx)
+	xrelease lock andw %ax,(%rcx)
+	lock xrelease andw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf2; andw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf3; andw %ax,(%rcx)
+	xrelease movw %ax,(%rcx)
+	xacquire lock orw %ax,(%rcx)
+	lock xacquire orw %ax,(%rcx)
+	xrelease lock orw %ax,(%rcx)
+	lock xrelease orw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf2; orw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf3; orw %ax,(%rcx)
+	xacquire lock sbbw %ax,(%rcx)
+	lock xacquire sbbw %ax,(%rcx)
+	xrelease lock sbbw %ax,(%rcx)
+	lock xrelease sbbw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf2; sbbw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf3; sbbw %ax,(%rcx)
+	xacquire lock subw %ax,(%rcx)
+	lock xacquire subw %ax,(%rcx)
+	xrelease lock subw %ax,(%rcx)
+	lock xrelease subw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf2; subw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf3; subw %ax,(%rcx)
+	xacquire lock xchgw %ax,(%rcx)
+	lock xacquire xchgw %ax,(%rcx)
+	xacquire xchgw %ax,(%rcx)
+	xrelease lock xchgw %ax,(%rcx)
+	lock xrelease xchgw %ax,(%rcx)
+	xrelease xchgw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf2; xchgw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf3; xchgw %ax,(%rcx)
+	xacquire lock xorw %ax,(%rcx)
+	lock xacquire xorw %ax,(%rcx)
+	xrelease lock xorw %ax,(%rcx)
+	lock xrelease xorw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf2; xorw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf3; xorw %ax,(%rcx)
+
+# Tests for op regl regl/m32
+# Tests for op regl/m32 regl
+	xacquire lock adcl %eax,(%rcx)
+	lock xacquire adcl %eax,(%rcx)
+	xrelease lock adcl %eax,(%rcx)
+	lock xrelease adcl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf2; adcl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf3; adcl %eax,(%rcx)
+	xacquire lock addl %eax,(%rcx)
+	lock xacquire addl %eax,(%rcx)
+	xrelease lock addl %eax,(%rcx)
+	lock xrelease addl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf2; addl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf3; addl %eax,(%rcx)
+	xacquire lock andl %eax,(%rcx)
+	lock xacquire andl %eax,(%rcx)
+	xrelease lock andl %eax,(%rcx)
+	lock xrelease andl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf2; andl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf3; andl %eax,(%rcx)
+	xrelease movl %eax,(%rcx)
+	xacquire lock orl %eax,(%rcx)
+	lock xacquire orl %eax,(%rcx)
+	xrelease lock orl %eax,(%rcx)
+	lock xrelease orl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf2; orl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf3; orl %eax,(%rcx)
+	xacquire lock sbbl %eax,(%rcx)
+	lock xacquire sbbl %eax,(%rcx)
+	xrelease lock sbbl %eax,(%rcx)
+	lock xrelease sbbl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf2; sbbl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf3; sbbl %eax,(%rcx)
+	xacquire lock subl %eax,(%rcx)
+	lock xacquire subl %eax,(%rcx)
+	xrelease lock subl %eax,(%rcx)
+	lock xrelease subl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf2; subl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf3; subl %eax,(%rcx)
+	xacquire lock xchgl %eax,(%rcx)
+	lock xacquire xchgl %eax,(%rcx)
+	xacquire xchgl %eax,(%rcx)
+	xrelease lock xchgl %eax,(%rcx)
+	lock xrelease xchgl %eax,(%rcx)
+	xrelease xchgl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf2; xchgl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf3; xchgl %eax,(%rcx)
+	xacquire lock xorl %eax,(%rcx)
+	lock xacquire xorl %eax,(%rcx)
+	xrelease lock xorl %eax,(%rcx)
+	lock xrelease xorl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf2; xorl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf3; xorl %eax,(%rcx)
+
+# Tests for op regq regq/m64
+# Tests for op regq/m64 regq
+	xacquire lock adcq %rax,(%rcx)
+	lock xacquire adcq %rax,(%rcx)
+	xrelease lock adcq %rax,(%rcx)
+	lock xrelease adcq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf2; adcq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf3; adcq %rax,(%rcx)
+	xacquire lock addq %rax,(%rcx)
+	lock xacquire addq %rax,(%rcx)
+	xrelease lock addq %rax,(%rcx)
+	lock xrelease addq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf2; addq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf3; addq %rax,(%rcx)
+	xacquire lock andq %rax,(%rcx)
+	lock xacquire andq %rax,(%rcx)
+	xrelease lock andq %rax,(%rcx)
+	lock xrelease andq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf2; andq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf3; andq %rax,(%rcx)
+	xrelease movq %rax,(%rcx)
+	xacquire lock orq %rax,(%rcx)
+	lock xacquire orq %rax,(%rcx)
+	xrelease lock orq %rax,(%rcx)
+	lock xrelease orq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf2; orq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf3; orq %rax,(%rcx)
+	xacquire lock sbbq %rax,(%rcx)
+	lock xacquire sbbq %rax,(%rcx)
+	xrelease lock sbbq %rax,(%rcx)
+	lock xrelease sbbq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf2; sbbq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf3; sbbq %rax,(%rcx)
+	xacquire lock subq %rax,(%rcx)
+	lock xacquire subq %rax,(%rcx)
+	xrelease lock subq %rax,(%rcx)
+	lock xrelease subq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf2; subq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf3; subq %rax,(%rcx)
+	xacquire lock xchgq %rax,(%rcx)
+	lock xacquire xchgq %rax,(%rcx)
+	xacquire xchgq %rax,(%rcx)
+	xrelease lock xchgq %rax,(%rcx)
+	lock xrelease xchgq %rax,(%rcx)
+	xrelease xchgq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf2; xchgq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf3; xchgq %rax,(%rcx)
+	xacquire lock xorq %rax,(%rcx)
+	lock xacquire xorq %rax,(%rcx)
+	xrelease lock xorq %rax,(%rcx)
+	lock xrelease xorq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf2; xorq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf3; xorq %rax,(%rcx)
+
+# Tests for op regs, regs/m16
+	xacquire lock btcw %ax,(%rcx)
+	lock xacquire btcw %ax,(%rcx)
+	xrelease lock btcw %ax,(%rcx)
+	lock xrelease btcw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf2; btcw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf3; btcw %ax,(%rcx)
+	xacquire lock btrw %ax,(%rcx)
+	lock xacquire btrw %ax,(%rcx)
+	xrelease lock btrw %ax,(%rcx)
+	lock xrelease btrw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf2; btrw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf3; btrw %ax,(%rcx)
+	xacquire lock btsw %ax,(%rcx)
+	lock xacquire btsw %ax,(%rcx)
+	xrelease lock btsw %ax,(%rcx)
+	lock xrelease btsw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf2; btsw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf3; btsw %ax,(%rcx)
+	xacquire lock cmpxchgw %ax,(%rcx)
+	lock xacquire cmpxchgw %ax,(%rcx)
+	xrelease lock cmpxchgw %ax,(%rcx)
+	lock xrelease cmpxchgw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf2; cmpxchgw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf3; cmpxchgw %ax,(%rcx)
+	xacquire lock xaddw %ax,(%rcx)
+	lock xacquire xaddw %ax,(%rcx)
+	xrelease lock xaddw %ax,(%rcx)
+	lock xrelease xaddw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf2; xaddw %ax,(%rcx)
+	.byte 0xf0; .byte 0xf3; xaddw %ax,(%rcx)
+
+# Tests for op regl regl/m32
+	xacquire lock btcl %eax,(%rcx)
+	lock xacquire btcl %eax,(%rcx)
+	xrelease lock btcl %eax,(%rcx)
+	lock xrelease btcl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf2; btcl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf3; btcl %eax,(%rcx)
+	xacquire lock btrl %eax,(%rcx)
+	lock xacquire btrl %eax,(%rcx)
+	xrelease lock btrl %eax,(%rcx)
+	lock xrelease btrl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf2; btrl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf3; btrl %eax,(%rcx)
+	xacquire lock btsl %eax,(%rcx)
+	lock xacquire btsl %eax,(%rcx)
+	xrelease lock btsl %eax,(%rcx)
+	lock xrelease btsl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf2; btsl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf3; btsl %eax,(%rcx)
+	xacquire lock cmpxchgl %eax,(%rcx)
+	lock xacquire cmpxchgl %eax,(%rcx)
+	xrelease lock cmpxchgl %eax,(%rcx)
+	lock xrelease cmpxchgl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf2; cmpxchgl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf3; cmpxchgl %eax,(%rcx)
+	xacquire lock xaddl %eax,(%rcx)
+	lock xacquire xaddl %eax,(%rcx)
+	xrelease lock xaddl %eax,(%rcx)
+	lock xrelease xaddl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf2; xaddl %eax,(%rcx)
+	.byte 0xf0; .byte 0xf3; xaddl %eax,(%rcx)
+
+# Tests for op regq regq/m64
+	xacquire lock btcq %rax,(%rcx)
+	lock xacquire btcq %rax,(%rcx)
+	xrelease lock btcq %rax,(%rcx)
+	lock xrelease btcq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf2; btcq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf3; btcq %rax,(%rcx)
+	xacquire lock btrq %rax,(%rcx)
+	lock xacquire btrq %rax,(%rcx)
+	xrelease lock btrq %rax,(%rcx)
+	lock xrelease btrq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf2; btrq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf3; btrq %rax,(%rcx)
+	xacquire lock btsq %rax,(%rcx)
+	lock xacquire btsq %rax,(%rcx)
+	xrelease lock btsq %rax,(%rcx)
+	lock xrelease btsq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf2; btsq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf3; btsq %rax,(%rcx)
+	xacquire lock cmpxchgq %rax,(%rcx)
+	lock xacquire cmpxchgq %rax,(%rcx)
+	xrelease lock cmpxchgq %rax,(%rcx)
+	lock xrelease cmpxchgq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf2; cmpxchgq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf3; cmpxchgq %rax,(%rcx)
+	xacquire lock xaddq %rax,(%rcx)
+	lock xacquire xaddq %rax,(%rcx)
+	xrelease lock xaddq %rax,(%rcx)
+	lock xrelease xaddq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf2; xaddq %rax,(%rcx)
+	.byte 0xf0; .byte 0xf3; xaddq %rax,(%rcx)
+
+# Tests for op regb/m8
+	xacquire lock decb (%rcx)
+	lock xacquire decb (%rcx)
+	xrelease lock decb (%rcx)
+	lock xrelease decb (%rcx)
+	.byte 0xf0; .byte 0xf2; decb (%rcx)
+	.byte 0xf0; .byte 0xf3; decb (%rcx)
+	xacquire lock incb (%rcx)
+	lock xacquire incb (%rcx)
+	xrelease lock incb (%rcx)
+	lock xrelease incb (%rcx)
+	.byte 0xf0; .byte 0xf2; incb (%rcx)
+	.byte 0xf0; .byte 0xf3; incb (%rcx)
+	xacquire lock negb (%rcx)
+	lock xacquire negb (%rcx)
+	xrelease lock negb (%rcx)
+	lock xrelease negb (%rcx)
+	.byte 0xf0; .byte 0xf2; negb (%rcx)
+	.byte 0xf0; .byte 0xf3; negb (%rcx)
+	xacquire lock notb (%rcx)
+	lock xacquire notb (%rcx)
+	xrelease lock notb (%rcx)
+	lock xrelease notb (%rcx)
+	.byte 0xf0; .byte 0xf2; notb (%rcx)
+	.byte 0xf0; .byte 0xf3; notb (%rcx)
+
+# Tests for op regs/m16
+	xacquire lock decw (%rcx)
+	lock xacquire decw (%rcx)
+	xrelease lock decw (%rcx)
+	lock xrelease decw (%rcx)
+	.byte 0xf0; .byte 0xf2; decw (%rcx)
+	.byte 0xf0; .byte 0xf3; decw (%rcx)
+	xacquire lock incw (%rcx)
+	lock xacquire incw (%rcx)
+	xrelease lock incw (%rcx)
+	lock xrelease incw (%rcx)
+	.byte 0xf0; .byte 0xf2; incw (%rcx)
+	.byte 0xf0; .byte 0xf3; incw (%rcx)
+	xacquire lock negw (%rcx)
+	lock xacquire negw (%rcx)
+	xrelease lock negw (%rcx)
+	lock xrelease negw (%rcx)
+	.byte 0xf0; .byte 0xf2; negw (%rcx)
+	.byte 0xf0; .byte 0xf3; negw (%rcx)
+	xacquire lock notw (%rcx)
+	lock xacquire notw (%rcx)
+	xrelease lock notw (%rcx)
+	lock xrelease notw (%rcx)
+	.byte 0xf0; .byte 0xf2; notw (%rcx)
+	.byte 0xf0; .byte 0xf3; notw (%rcx)
+
+# Tests for op regl/m32
+	xacquire lock decl (%rcx)
+	lock xacquire decl (%rcx)
+	xrelease lock decl (%rcx)
+	lock xrelease decl (%rcx)
+	.byte 0xf0; .byte 0xf2; decl (%rcx)
+	.byte 0xf0; .byte 0xf3; decl (%rcx)
+	xacquire lock incl (%rcx)
+	lock xacquire incl (%rcx)
+	xrelease lock incl (%rcx)
+	lock xrelease incl (%rcx)
+	.byte 0xf0; .byte 0xf2; incl (%rcx)
+	.byte 0xf0; .byte 0xf3; incl (%rcx)
+	xacquire lock negl (%rcx)
+	lock xacquire negl (%rcx)
+	xrelease lock negl (%rcx)
+	lock xrelease negl (%rcx)
+	.byte 0xf0; .byte 0xf2; negl (%rcx)
+	.byte 0xf0; .byte 0xf3; negl (%rcx)
+	xacquire lock notl (%rcx)
+	lock xacquire notl (%rcx)
+	xrelease lock notl (%rcx)
+	lock xrelease notl (%rcx)
+	.byte 0xf0; .byte 0xf2; notl (%rcx)
+	.byte 0xf0; .byte 0xf3; notl (%rcx)
+
+# Tests for op regq/m64
+	xacquire lock decq (%rcx)
+	lock xacquire decq (%rcx)
+	xrelease lock decq (%rcx)
+	lock xrelease decq (%rcx)
+	.byte 0xf0; .byte 0xf2; decq (%rcx)
+	.byte 0xf0; .byte 0xf3; decq (%rcx)
+	xacquire lock incq (%rcx)
+	lock xacquire incq (%rcx)
+	xrelease lock incq (%rcx)
+	lock xrelease incq (%rcx)
+	.byte 0xf0; .byte 0xf2; incq (%rcx)
+	.byte 0xf0; .byte 0xf3; incq (%rcx)
+	xacquire lock negq (%rcx)
+	lock xacquire negq (%rcx)
+	xrelease lock negq (%rcx)
+	lock xrelease negq (%rcx)
+	.byte 0xf0; .byte 0xf2; negq (%rcx)
+	.byte 0xf0; .byte 0xf3; negq (%rcx)
+	xacquire lock notq (%rcx)
+	lock xacquire notq (%rcx)
+	xrelease lock notq (%rcx)
+	lock xrelease notq (%rcx)
+	.byte 0xf0; .byte 0xf2; notq (%rcx)
+	.byte 0xf0; .byte 0xf3; notq (%rcx)
+
+# Tests for op m64
+	xacquire lock cmpxchg8bq (%rcx)
+	lock xacquire cmpxchg8bq (%rcx)
+	xrelease lock cmpxchg8bq (%rcx)
+	lock xrelease cmpxchg8bq (%rcx)
+	.byte 0xf0; .byte 0xf2; cmpxchg8bq (%rcx)
+	.byte 0xf0; .byte 0xf3; cmpxchg8bq (%rcx)
+
+# Tests for op regb, regb/m8
+	xacquire lock cmpxchgb %cl,(%rcx)
+	lock xacquire cmpxchgb %cl,(%rcx)
+	xrelease lock cmpxchgb %cl,(%rcx)
+	lock xrelease cmpxchgb %cl,(%rcx)
+	.byte 0xf0; .byte 0xf2; cmpxchgb %cl,(%rcx)
+	.byte 0xf0; .byte 0xf3; cmpxchgb %cl,(%rcx)
+	xacquire lock xaddb %cl,(%rcx)
+	lock xacquire xaddb %cl,(%rcx)
+	xrelease lock xaddb %cl,(%rcx)
+	lock xrelease xaddb %cl,(%rcx)
+	.byte 0xf0; .byte 0xf2; xaddb %cl,(%rcx)
+	.byte 0xf0; .byte 0xf3; xaddb %cl,(%rcx)
+
+	.intel_syntax noprefix
+
+
+# Tests for op imm32 rax
+
+# Tests for op imm8 regb/m8
+	xacquire lock adc BYTE PTR [rcx],100
+	lock xacquire adc BYTE PTR [rcx],100
+	xrelease lock adc BYTE PTR [rcx],100
+	lock xrelease adc BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; adc BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; adc BYTE PTR [rcx],100
+	xacquire lock add BYTE PTR [rcx],100
+	lock xacquire add BYTE PTR [rcx],100
+	xrelease lock add BYTE PTR [rcx],100
+	lock xrelease add BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; add BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; add BYTE PTR [rcx],100
+	xacquire lock and BYTE PTR [rcx],100
+	lock xacquire and BYTE PTR [rcx],100
+	xrelease lock and BYTE PTR [rcx],100
+	lock xrelease and BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; and BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; and BYTE PTR [rcx],100
+	xrelease mov BYTE PTR [rcx],100
+	xacquire lock or BYTE PTR [rcx],100
+	lock xacquire or BYTE PTR [rcx],100
+	xrelease lock or BYTE PTR [rcx],100
+	lock xrelease or BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; or BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; or BYTE PTR [rcx],100
+	xacquire lock sbb BYTE PTR [rcx],100
+	lock xacquire sbb BYTE PTR [rcx],100
+	xrelease lock sbb BYTE PTR [rcx],100
+	lock xrelease sbb BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; sbb BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; sbb BYTE PTR [rcx],100
+	xacquire lock sub BYTE PTR [rcx],100
+	lock xacquire sub BYTE PTR [rcx],100
+	xrelease lock sub BYTE PTR [rcx],100
+	lock xrelease sub BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; sub BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; sub BYTE PTR [rcx],100
+	xacquire lock xor BYTE PTR [rcx],100
+	lock xacquire xor BYTE PTR [rcx],100
+	xrelease lock xor BYTE PTR [rcx],100
+	lock xrelease xor BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; xor BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; xor BYTE PTR [rcx],100
+
+# Tests for op imm16 regs/m16
+	xacquire lock adc WORD PTR [rcx],1000
+	lock xacquire adc WORD PTR [rcx],1000
+	xrelease lock adc WORD PTR [rcx],1000
+	lock xrelease adc WORD PTR [rcx],1000
+	.byte 0xf0; .byte 0xf2; adc WORD PTR [rcx],1000
+	.byte 0xf0; .byte 0xf3; adc WORD PTR [rcx],1000
+	xacquire lock add WORD PTR [rcx],1000
+	lock xacquire add WORD PTR [rcx],1000
+	xrelease lock add WORD PTR [rcx],1000
+	lock xrelease add WORD PTR [rcx],1000
+	.byte 0xf0; .byte 0xf2; add WORD PTR [rcx],1000
+	.byte 0xf0; .byte 0xf3; add WORD PTR [rcx],1000
+	xacquire lock and WORD PTR [rcx],1000
+	lock xacquire and WORD PTR [rcx],1000
+	xrelease lock and WORD PTR [rcx],1000
+	lock xrelease and WORD PTR [rcx],1000
+	.byte 0xf0; .byte 0xf2; and WORD PTR [rcx],1000
+	.byte 0xf0; .byte 0xf3; and WORD PTR [rcx],1000
+	xrelease mov WORD PTR [rcx],1000
+	xacquire lock or WORD PTR [rcx],1000
+	lock xacquire or WORD PTR [rcx],1000
+	xrelease lock or WORD PTR [rcx],1000
+	lock xrelease or WORD PTR [rcx],1000
+	.byte 0xf0; .byte 0xf2; or WORD PTR [rcx],1000
+	.byte 0xf0; .byte 0xf3; or WORD PTR [rcx],1000
+	xacquire lock sbb WORD PTR [rcx],1000
+	lock xacquire sbb WORD PTR [rcx],1000
+	xrelease lock sbb WORD PTR [rcx],1000
+	lock xrelease sbb WORD PTR [rcx],1000
+	.byte 0xf0; .byte 0xf2; sbb WORD PTR [rcx],1000
+	.byte 0xf0; .byte 0xf3; sbb WORD PTR [rcx],1000
+	xacquire lock sub WORD PTR [rcx],1000
+	lock xacquire sub WORD PTR [rcx],1000
+	xrelease lock sub WORD PTR [rcx],1000
+	lock xrelease sub WORD PTR [rcx],1000
+	.byte 0xf0; .byte 0xf2; sub WORD PTR [rcx],1000
+	.byte 0xf0; .byte 0xf3; sub WORD PTR [rcx],1000
+	xacquire lock xor WORD PTR [rcx],1000
+	lock xacquire xor WORD PTR [rcx],1000
+	xrelease lock xor WORD PTR [rcx],1000
+	lock xrelease xor WORD PTR [rcx],1000
+	.byte 0xf0; .byte 0xf2; xor WORD PTR [rcx],1000
+	.byte 0xf0; .byte 0xf3; xor WORD PTR [rcx],1000
+
+# Tests for op imm32 regl/m32
+	xacquire lock adc DWORD PTR [rcx],10000000
+	lock xacquire adc DWORD PTR [rcx],10000000
+	xrelease lock adc DWORD PTR [rcx],10000000
+	lock xrelease adc DWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf2; adc DWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf3; adc DWORD PTR [rcx],10000000
+	xacquire lock add DWORD PTR [rcx],10000000
+	lock xacquire add DWORD PTR [rcx],10000000
+	xrelease lock add DWORD PTR [rcx],10000000
+	lock xrelease add DWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf2; add DWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf3; add DWORD PTR [rcx],10000000
+	xacquire lock and DWORD PTR [rcx],10000000
+	lock xacquire and DWORD PTR [rcx],10000000
+	xrelease lock and DWORD PTR [rcx],10000000
+	lock xrelease and DWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf2; and DWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf3; and DWORD PTR [rcx],10000000
+	xrelease mov DWORD PTR [rcx],10000000
+	xacquire lock or DWORD PTR [rcx],10000000
+	lock xacquire or DWORD PTR [rcx],10000000
+	xrelease lock or DWORD PTR [rcx],10000000
+	lock xrelease or DWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf2; or DWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf3; or DWORD PTR [rcx],10000000
+	xacquire lock sbb DWORD PTR [rcx],10000000
+	lock xacquire sbb DWORD PTR [rcx],10000000
+	xrelease lock sbb DWORD PTR [rcx],10000000
+	lock xrelease sbb DWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf2; sbb DWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf3; sbb DWORD PTR [rcx],10000000
+	xacquire lock sub DWORD PTR [rcx],10000000
+	lock xacquire sub DWORD PTR [rcx],10000000
+	xrelease lock sub DWORD PTR [rcx],10000000
+	lock xrelease sub DWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf2; sub DWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf3; sub DWORD PTR [rcx],10000000
+	xacquire lock xor DWORD PTR [rcx],10000000
+	lock xacquire xor DWORD PTR [rcx],10000000
+	xrelease lock xor DWORD PTR [rcx],10000000
+	lock xrelease xor DWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf2; xor DWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf3; xor DWORD PTR [rcx],10000000
+
+# Tests for op imm32 regq/m64
+	xacquire lock adc QWORD PTR [rcx],10000000
+	lock xacquire adc QWORD PTR [rcx],10000000
+	xrelease lock adc QWORD PTR [rcx],10000000
+	lock xrelease adc QWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf2; adc QWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf3; adc QWORD PTR [rcx],10000000
+	xacquire lock add QWORD PTR [rcx],10000000
+	lock xacquire add QWORD PTR [rcx],10000000
+	xrelease lock add QWORD PTR [rcx],10000000
+	lock xrelease add QWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf2; add QWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf3; add QWORD PTR [rcx],10000000
+	xacquire lock and QWORD PTR [rcx],10000000
+	lock xacquire and QWORD PTR [rcx],10000000
+	xrelease lock and QWORD PTR [rcx],10000000
+	lock xrelease and QWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf2; and QWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf3; and QWORD PTR [rcx],10000000
+	xrelease mov QWORD PTR [rcx],10000000
+	xacquire lock or QWORD PTR [rcx],10000000
+	lock xacquire or QWORD PTR [rcx],10000000
+	xrelease lock or QWORD PTR [rcx],10000000
+	lock xrelease or QWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf2; or QWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf3; or QWORD PTR [rcx],10000000
+	xacquire lock sbb QWORD PTR [rcx],10000000
+	lock xacquire sbb QWORD PTR [rcx],10000000
+	xrelease lock sbb QWORD PTR [rcx],10000000
+	lock xrelease sbb QWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf2; sbb QWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf3; sbb QWORD PTR [rcx],10000000
+	xacquire lock sub QWORD PTR [rcx],10000000
+	lock xacquire sub QWORD PTR [rcx],10000000
+	xrelease lock sub QWORD PTR [rcx],10000000
+	lock xrelease sub QWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf2; sub QWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf3; sub QWORD PTR [rcx],10000000
+	xacquire lock xor QWORD PTR [rcx],10000000
+	lock xacquire xor QWORD PTR [rcx],10000000
+	xrelease lock xor QWORD PTR [rcx],10000000
+	lock xrelease xor QWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf2; xor QWORD PTR [rcx],10000000
+	.byte 0xf0; .byte 0xf3; xor QWORD PTR [rcx],10000000
+
+# Tests for op imm8 regs/m16
+	xacquire lock adc WORD PTR [rcx],100
+	lock xacquire adc WORD PTR [rcx],100
+	xrelease lock adc WORD PTR [rcx],100
+	lock xrelease adc WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; adc WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; adc WORD PTR [rcx],100
+	xacquire lock add WORD PTR [rcx],100
+	lock xacquire add WORD PTR [rcx],100
+	xrelease lock add WORD PTR [rcx],100
+	lock xrelease add WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; add WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; add WORD PTR [rcx],100
+	xacquire lock and WORD PTR [rcx],100
+	lock xacquire and WORD PTR [rcx],100
+	xrelease lock and WORD PTR [rcx],100
+	lock xrelease and WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; and WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; and WORD PTR [rcx],100
+	xacquire lock btc WORD PTR [rcx],100
+	lock xacquire btc WORD PTR [rcx],100
+	xrelease lock btc WORD PTR [rcx],100
+	lock xrelease btc WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; btc WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; btc WORD PTR [rcx],100
+	xacquire lock btr WORD PTR [rcx],100
+	lock xacquire btr WORD PTR [rcx],100
+	xrelease lock btr WORD PTR [rcx],100
+	lock xrelease btr WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; btr WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; btr WORD PTR [rcx],100
+	xacquire lock bts WORD PTR [rcx],100
+	lock xacquire bts WORD PTR [rcx],100
+	xrelease lock bts WORD PTR [rcx],100
+	lock xrelease bts WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; bts WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; bts WORD PTR [rcx],100
+	xrelease mov WORD PTR [rcx],100
+	xacquire lock or WORD PTR [rcx],100
+	lock xacquire or WORD PTR [rcx],100
+	xrelease lock or WORD PTR [rcx],100
+	lock xrelease or WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; or WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; or WORD PTR [rcx],100
+	xacquire lock sbb WORD PTR [rcx],100
+	lock xacquire sbb WORD PTR [rcx],100
+	xrelease lock sbb WORD PTR [rcx],100
+	lock xrelease sbb WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; sbb WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; sbb WORD PTR [rcx],100
+	xacquire lock sub WORD PTR [rcx],100
+	lock xacquire sub WORD PTR [rcx],100
+	xrelease lock sub WORD PTR [rcx],100
+	lock xrelease sub WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; sub WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; sub WORD PTR [rcx],100
+	xacquire lock xor WORD PTR [rcx],100
+	lock xacquire xor WORD PTR [rcx],100
+	xrelease lock xor WORD PTR [rcx],100
+	lock xrelease xor WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; xor WORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; xor WORD PTR [rcx],100
+
+# Tests for op imm8 regl/m32
+	xacquire lock adc DWORD PTR [rcx],100
+	lock xacquire adc DWORD PTR [rcx],100
+	xrelease lock adc DWORD PTR [rcx],100
+	lock xrelease adc DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; adc DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; adc DWORD PTR [rcx],100
+	xacquire lock add DWORD PTR [rcx],100
+	lock xacquire add DWORD PTR [rcx],100
+	xrelease lock add DWORD PTR [rcx],100
+	lock xrelease add DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; add DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; add DWORD PTR [rcx],100
+	xacquire lock and DWORD PTR [rcx],100
+	lock xacquire and DWORD PTR [rcx],100
+	xrelease lock and DWORD PTR [rcx],100
+	lock xrelease and DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; and DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; and DWORD PTR [rcx],100
+	xacquire lock btc DWORD PTR [rcx],100
+	lock xacquire btc DWORD PTR [rcx],100
+	xrelease lock btc DWORD PTR [rcx],100
+	lock xrelease btc DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; btc DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; btc DWORD PTR [rcx],100
+	xacquire lock btr DWORD PTR [rcx],100
+	lock xacquire btr DWORD PTR [rcx],100
+	xrelease lock btr DWORD PTR [rcx],100
+	lock xrelease btr DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; btr DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; btr DWORD PTR [rcx],100
+	xacquire lock bts DWORD PTR [rcx],100
+	lock xacquire bts DWORD PTR [rcx],100
+	xrelease lock bts DWORD PTR [rcx],100
+	lock xrelease bts DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; bts DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; bts DWORD PTR [rcx],100
+	xrelease mov DWORD PTR [rcx],100
+	xacquire lock or DWORD PTR [rcx],100
+	lock xacquire or DWORD PTR [rcx],100
+	xrelease lock or DWORD PTR [rcx],100
+	lock xrelease or DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; or DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; or DWORD PTR [rcx],100
+	xacquire lock sbb DWORD PTR [rcx],100
+	lock xacquire sbb DWORD PTR [rcx],100
+	xrelease lock sbb DWORD PTR [rcx],100
+	lock xrelease sbb DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; sbb DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; sbb DWORD PTR [rcx],100
+	xacquire lock sub DWORD PTR [rcx],100
+	lock xacquire sub DWORD PTR [rcx],100
+	xrelease lock sub DWORD PTR [rcx],100
+	lock xrelease sub DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; sub DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; sub DWORD PTR [rcx],100
+	xacquire lock xor DWORD PTR [rcx],100
+	lock xacquire xor DWORD PTR [rcx],100
+	xrelease lock xor DWORD PTR [rcx],100
+	lock xrelease xor DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; xor DWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; xor DWORD PTR [rcx],100
+
+# Tests for op imm8 regq/m64
+	xacquire lock adc QWORD PTR [rcx],100
+	lock xacquire adc QWORD PTR [rcx],100
+	xrelease lock adc QWORD PTR [rcx],100
+	lock xrelease adc QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; adc QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; adc QWORD PTR [rcx],100
+	xacquire lock add QWORD PTR [rcx],100
+	lock xacquire add QWORD PTR [rcx],100
+	xrelease lock add QWORD PTR [rcx],100
+	lock xrelease add QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; add QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; add QWORD PTR [rcx],100
+	xacquire lock and QWORD PTR [rcx],100
+	lock xacquire and QWORD PTR [rcx],100
+	xrelease lock and QWORD PTR [rcx],100
+	lock xrelease and QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; and QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; and QWORD PTR [rcx],100
+	xacquire lock btc QWORD PTR [rcx],100
+	lock xacquire btc QWORD PTR [rcx],100
+	xrelease lock btc QWORD PTR [rcx],100
+	lock xrelease btc QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; btc QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; btc QWORD PTR [rcx],100
+	xacquire lock btr QWORD PTR [rcx],100
+	lock xacquire btr QWORD PTR [rcx],100
+	xrelease lock btr QWORD PTR [rcx],100
+	lock xrelease btr QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; btr QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; btr QWORD PTR [rcx],100
+	xacquire lock bts QWORD PTR [rcx],100
+	lock xacquire bts QWORD PTR [rcx],100
+	xrelease lock bts QWORD PTR [rcx],100
+	lock xrelease bts QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; bts QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; bts QWORD PTR [rcx],100
+	xrelease mov QWORD PTR [rcx],100
+	xacquire lock or QWORD PTR [rcx],100
+	lock xacquire or QWORD PTR [rcx],100
+	xrelease lock or QWORD PTR [rcx],100
+	lock xrelease or QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; or QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; or QWORD PTR [rcx],100
+	xacquire lock sbb QWORD PTR [rcx],100
+	lock xacquire sbb QWORD PTR [rcx],100
+	xrelease lock sbb QWORD PTR [rcx],100
+	lock xrelease sbb QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; sbb QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; sbb QWORD PTR [rcx],100
+	xacquire lock sub QWORD PTR [rcx],100
+	lock xacquire sub QWORD PTR [rcx],100
+	xrelease lock sub QWORD PTR [rcx],100
+	lock xrelease sub QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; sub QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; sub QWORD PTR [rcx],100
+	xacquire lock xor QWORD PTR [rcx],100
+	lock xacquire xor QWORD PTR [rcx],100
+	xrelease lock xor QWORD PTR [rcx],100
+	lock xrelease xor QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; xor QWORD PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; xor QWORD PTR [rcx],100
+
+# Tests for op imm8 regb/m8
+	xacquire lock adc BYTE PTR [rcx],100
+	lock xacquire adc BYTE PTR [rcx],100
+	xrelease lock adc BYTE PTR [rcx],100
+	lock xrelease adc BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; adc BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; adc BYTE PTR [rcx],100
+	xacquire lock add BYTE PTR [rcx],100
+	lock xacquire add BYTE PTR [rcx],100
+	xrelease lock add BYTE PTR [rcx],100
+	lock xrelease add BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; add BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; add BYTE PTR [rcx],100
+	xacquire lock and BYTE PTR [rcx],100
+	lock xacquire and BYTE PTR [rcx],100
+	xrelease lock and BYTE PTR [rcx],100
+	lock xrelease and BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; and BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; and BYTE PTR [rcx],100
+	xrelease mov BYTE PTR [rcx],100
+	xacquire lock or BYTE PTR [rcx],100
+	lock xacquire or BYTE PTR [rcx],100
+	xrelease lock or BYTE PTR [rcx],100
+	lock xrelease or BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; or BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; or BYTE PTR [rcx],100
+	xacquire lock sbb BYTE PTR [rcx],100
+	lock xacquire sbb BYTE PTR [rcx],100
+	xrelease lock sbb BYTE PTR [rcx],100
+	lock xrelease sbb BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; sbb BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; sbb BYTE PTR [rcx],100
+	xacquire lock sub BYTE PTR [rcx],100
+	lock xacquire sub BYTE PTR [rcx],100
+	xrelease lock sub BYTE PTR [rcx],100
+	lock xrelease sub BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; sub BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; sub BYTE PTR [rcx],100
+	xacquire lock xor BYTE PTR [rcx],100
+	lock xacquire xor BYTE PTR [rcx],100
+	xrelease lock xor BYTE PTR [rcx],100
+	lock xrelease xor BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf2; xor BYTE PTR [rcx],100
+	.byte 0xf0; .byte 0xf3; xor BYTE PTR [rcx],100
+
+# Tests for op regb regb/m8
+# Tests for op regb/m8 regb
+	xacquire lock adc BYTE PTR [rcx],al
+	lock xacquire adc BYTE PTR [rcx],al
+	xrelease lock adc BYTE PTR [rcx],al
+	lock xrelease adc BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf2; adc BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf3; adc BYTE PTR [rcx],al
+	xacquire lock add BYTE PTR [rcx],al
+	lock xacquire add BYTE PTR [rcx],al
+	xrelease lock add BYTE PTR [rcx],al
+	lock xrelease add BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf2; add BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf3; add BYTE PTR [rcx],al
+	xacquire lock and BYTE PTR [rcx],al
+	lock xacquire and BYTE PTR [rcx],al
+	xrelease lock and BYTE PTR [rcx],al
+	lock xrelease and BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf2; and BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf3; and BYTE PTR [rcx],al
+	xrelease mov BYTE PTR [rcx],al
+	xacquire lock or BYTE PTR [rcx],al
+	lock xacquire or BYTE PTR [rcx],al
+	xrelease lock or BYTE PTR [rcx],al
+	lock xrelease or BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf2; or BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf3; or BYTE PTR [rcx],al
+	xacquire lock sbb BYTE PTR [rcx],al
+	lock xacquire sbb BYTE PTR [rcx],al
+	xrelease lock sbb BYTE PTR [rcx],al
+	lock xrelease sbb BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf2; sbb BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf3; sbb BYTE PTR [rcx],al
+	xacquire lock sub BYTE PTR [rcx],al
+	lock xacquire sub BYTE PTR [rcx],al
+	xrelease lock sub BYTE PTR [rcx],al
+	lock xrelease sub BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf2; sub BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf3; sub BYTE PTR [rcx],al
+	xacquire lock xchg BYTE PTR [rcx],al
+	lock xacquire xchg BYTE PTR [rcx],al
+	xacquire xchg BYTE PTR [rcx],al
+	xrelease lock xchg BYTE PTR [rcx],al
+	lock xrelease xchg BYTE PTR [rcx],al
+	xrelease xchg BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf2; xchg BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf3; xchg BYTE PTR [rcx],al
+	xacquire lock xor BYTE PTR [rcx],al
+	lock xacquire xor BYTE PTR [rcx],al
+	xrelease lock xor BYTE PTR [rcx],al
+	lock xrelease xor BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf2; xor BYTE PTR [rcx],al
+	.byte 0xf0; .byte 0xf3; xor BYTE PTR [rcx],al
+
+# Tests for op regs regs/m16
+# Tests for op regs/m16 regs
+	xacquire lock adc WORD PTR [rcx],ax
+	lock xacquire adc WORD PTR [rcx],ax
+	xrelease lock adc WORD PTR [rcx],ax
+	lock xrelease adc WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf2; adc WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf3; adc WORD PTR [rcx],ax
+	xacquire lock add WORD PTR [rcx],ax
+	lock xacquire add WORD PTR [rcx],ax
+	xrelease lock add WORD PTR [rcx],ax
+	lock xrelease add WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf2; add WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf3; add WORD PTR [rcx],ax
+	xacquire lock and WORD PTR [rcx],ax
+	lock xacquire and WORD PTR [rcx],ax
+	xrelease lock and WORD PTR [rcx],ax
+	lock xrelease and WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf2; and WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf3; and WORD PTR [rcx],ax
+	xrelease mov WORD PTR [rcx],ax
+	xacquire lock or WORD PTR [rcx],ax
+	lock xacquire or WORD PTR [rcx],ax
+	xrelease lock or WORD PTR [rcx],ax
+	lock xrelease or WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf2; or WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf3; or WORD PTR [rcx],ax
+	xacquire lock sbb WORD PTR [rcx],ax
+	lock xacquire sbb WORD PTR [rcx],ax
+	xrelease lock sbb WORD PTR [rcx],ax
+	lock xrelease sbb WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf2; sbb WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf3; sbb WORD PTR [rcx],ax
+	xacquire lock sub WORD PTR [rcx],ax
+	lock xacquire sub WORD PTR [rcx],ax
+	xrelease lock sub WORD PTR [rcx],ax
+	lock xrelease sub WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf2; sub WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf3; sub WORD PTR [rcx],ax
+	xacquire lock xchg WORD PTR [rcx],ax
+	lock xacquire xchg WORD PTR [rcx],ax
+	xacquire xchg WORD PTR [rcx],ax
+	xrelease lock xchg WORD PTR [rcx],ax
+	lock xrelease xchg WORD PTR [rcx],ax
+	xrelease xchg WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf2; xchg WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf3; xchg WORD PTR [rcx],ax
+	xacquire lock xor WORD PTR [rcx],ax
+	lock xacquire xor WORD PTR [rcx],ax
+	xrelease lock xor WORD PTR [rcx],ax
+	lock xrelease xor WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf2; xor WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf3; xor WORD PTR [rcx],ax
+
+# Tests for op regl regl/m32
+# Tests for op regl/m32 regl
+	xacquire lock adc DWORD PTR [rcx],eax
+	lock xacquire adc DWORD PTR [rcx],eax
+	xrelease lock adc DWORD PTR [rcx],eax
+	lock xrelease adc DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf2; adc DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf3; adc DWORD PTR [rcx],eax
+	xacquire lock add DWORD PTR [rcx],eax
+	lock xacquire add DWORD PTR [rcx],eax
+	xrelease lock add DWORD PTR [rcx],eax
+	lock xrelease add DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf2; add DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf3; add DWORD PTR [rcx],eax
+	xacquire lock and DWORD PTR [rcx],eax
+	lock xacquire and DWORD PTR [rcx],eax
+	xrelease lock and DWORD PTR [rcx],eax
+	lock xrelease and DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf2; and DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf3; and DWORD PTR [rcx],eax
+	xrelease mov DWORD PTR [rcx],eax
+	xacquire lock or DWORD PTR [rcx],eax
+	lock xacquire or DWORD PTR [rcx],eax
+	xrelease lock or DWORD PTR [rcx],eax
+	lock xrelease or DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf2; or DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf3; or DWORD PTR [rcx],eax
+	xacquire lock sbb DWORD PTR [rcx],eax
+	lock xacquire sbb DWORD PTR [rcx],eax
+	xrelease lock sbb DWORD PTR [rcx],eax
+	lock xrelease sbb DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf2; sbb DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf3; sbb DWORD PTR [rcx],eax
+	xacquire lock sub DWORD PTR [rcx],eax
+	lock xacquire sub DWORD PTR [rcx],eax
+	xrelease lock sub DWORD PTR [rcx],eax
+	lock xrelease sub DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf2; sub DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf3; sub DWORD PTR [rcx],eax
+	xacquire lock xchg DWORD PTR [rcx],eax
+	lock xacquire xchg DWORD PTR [rcx],eax
+	xacquire xchg DWORD PTR [rcx],eax
+	xrelease lock xchg DWORD PTR [rcx],eax
+	lock xrelease xchg DWORD PTR [rcx],eax
+	xrelease xchg DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf2; xchg DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf3; xchg DWORD PTR [rcx],eax
+	xacquire lock xor DWORD PTR [rcx],eax
+	lock xacquire xor DWORD PTR [rcx],eax
+	xrelease lock xor DWORD PTR [rcx],eax
+	lock xrelease xor DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf2; xor DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf3; xor DWORD PTR [rcx],eax
+
+# Tests for op regq regq/m64
+# Tests for op regq/m64 regq
+	xacquire lock adc QWORD PTR [rcx],rax
+	lock xacquire adc QWORD PTR [rcx],rax
+	xrelease lock adc QWORD PTR [rcx],rax
+	lock xrelease adc QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf2; adc QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf3; adc QWORD PTR [rcx],rax
+	xacquire lock add QWORD PTR [rcx],rax
+	lock xacquire add QWORD PTR [rcx],rax
+	xrelease lock add QWORD PTR [rcx],rax
+	lock xrelease add QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf2; add QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf3; add QWORD PTR [rcx],rax
+	xacquire lock and QWORD PTR [rcx],rax
+	lock xacquire and QWORD PTR [rcx],rax
+	xrelease lock and QWORD PTR [rcx],rax
+	lock xrelease and QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf2; and QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf3; and QWORD PTR [rcx],rax
+	xrelease mov QWORD PTR [rcx],rax
+	xacquire lock or QWORD PTR [rcx],rax
+	lock xacquire or QWORD PTR [rcx],rax
+	xrelease lock or QWORD PTR [rcx],rax
+	lock xrelease or QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf2; or QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf3; or QWORD PTR [rcx],rax
+	xacquire lock sbb QWORD PTR [rcx],rax
+	lock xacquire sbb QWORD PTR [rcx],rax
+	xrelease lock sbb QWORD PTR [rcx],rax
+	lock xrelease sbb QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf2; sbb QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf3; sbb QWORD PTR [rcx],rax
+	xacquire lock sub QWORD PTR [rcx],rax
+	lock xacquire sub QWORD PTR [rcx],rax
+	xrelease lock sub QWORD PTR [rcx],rax
+	lock xrelease sub QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf2; sub QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf3; sub QWORD PTR [rcx],rax
+	xacquire lock xchg QWORD PTR [rcx],rax
+	lock xacquire xchg QWORD PTR [rcx],rax
+	xacquire xchg QWORD PTR [rcx],rax
+	xrelease lock xchg QWORD PTR [rcx],rax
+	lock xrelease xchg QWORD PTR [rcx],rax
+	xrelease xchg QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf2; xchg QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf3; xchg QWORD PTR [rcx],rax
+	xacquire lock xor QWORD PTR [rcx],rax
+	lock xacquire xor QWORD PTR [rcx],rax
+	xrelease lock xor QWORD PTR [rcx],rax
+	lock xrelease xor QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf2; xor QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf3; xor QWORD PTR [rcx],rax
+
+# Tests for op regs, regs/m16
+	xacquire lock btc WORD PTR [rcx],ax
+	lock xacquire btc WORD PTR [rcx],ax
+	xrelease lock btc WORD PTR [rcx],ax
+	lock xrelease btc WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf2; btc WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf3; btc WORD PTR [rcx],ax
+	xacquire lock btr WORD PTR [rcx],ax
+	lock xacquire btr WORD PTR [rcx],ax
+	xrelease lock btr WORD PTR [rcx],ax
+	lock xrelease btr WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf2; btr WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf3; btr WORD PTR [rcx],ax
+	xacquire lock bts WORD PTR [rcx],ax
+	lock xacquire bts WORD PTR [rcx],ax
+	xrelease lock bts WORD PTR [rcx],ax
+	lock xrelease bts WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf2; bts WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf3; bts WORD PTR [rcx],ax
+	xacquire lock cmpxchg WORD PTR [rcx],ax
+	lock xacquire cmpxchg WORD PTR [rcx],ax
+	xrelease lock cmpxchg WORD PTR [rcx],ax
+	lock xrelease cmpxchg WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf2; cmpxchg WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf3; cmpxchg WORD PTR [rcx],ax
+	xacquire lock xadd WORD PTR [rcx],ax
+	lock xacquire xadd WORD PTR [rcx],ax
+	xrelease lock xadd WORD PTR [rcx],ax
+	lock xrelease xadd WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf2; xadd WORD PTR [rcx],ax
+	.byte 0xf0; .byte 0xf3; xadd WORD PTR [rcx],ax
+
+# Tests for op regl regl/m32
+	xacquire lock btc DWORD PTR [rcx],eax
+	lock xacquire btc DWORD PTR [rcx],eax
+	xrelease lock btc DWORD PTR [rcx],eax
+	lock xrelease btc DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf2; btc DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf3; btc DWORD PTR [rcx],eax
+	xacquire lock btr DWORD PTR [rcx],eax
+	lock xacquire btr DWORD PTR [rcx],eax
+	xrelease lock btr DWORD PTR [rcx],eax
+	lock xrelease btr DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf2; btr DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf3; btr DWORD PTR [rcx],eax
+	xacquire lock bts DWORD PTR [rcx],eax
+	lock xacquire bts DWORD PTR [rcx],eax
+	xrelease lock bts DWORD PTR [rcx],eax
+	lock xrelease bts DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf2; bts DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf3; bts DWORD PTR [rcx],eax
+	xacquire lock cmpxchg DWORD PTR [rcx],eax
+	lock xacquire cmpxchg DWORD PTR [rcx],eax
+	xrelease lock cmpxchg DWORD PTR [rcx],eax
+	lock xrelease cmpxchg DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf2; cmpxchg DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf3; cmpxchg DWORD PTR [rcx],eax
+	xacquire lock xadd DWORD PTR [rcx],eax
+	lock xacquire xadd DWORD PTR [rcx],eax
+	xrelease lock xadd DWORD PTR [rcx],eax
+	lock xrelease xadd DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf2; xadd DWORD PTR [rcx],eax
+	.byte 0xf0; .byte 0xf3; xadd DWORD PTR [rcx],eax
+
+# Tests for op regq regq/m64
+	xacquire lock btc QWORD PTR [rcx],rax
+	lock xacquire btc QWORD PTR [rcx],rax
+	xrelease lock btc QWORD PTR [rcx],rax
+	lock xrelease btc QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf2; btc QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf3; btc QWORD PTR [rcx],rax
+	xacquire lock btr QWORD PTR [rcx],rax
+	lock xacquire btr QWORD PTR [rcx],rax
+	xrelease lock btr QWORD PTR [rcx],rax
+	lock xrelease btr QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf2; btr QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf3; btr QWORD PTR [rcx],rax
+	xacquire lock bts QWORD PTR [rcx],rax
+	lock xacquire bts QWORD PTR [rcx],rax
+	xrelease lock bts QWORD PTR [rcx],rax
+	lock xrelease bts QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf2; bts QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf3; bts QWORD PTR [rcx],rax
+	xacquire lock cmpxchg QWORD PTR [rcx],rax
+	lock xacquire cmpxchg QWORD PTR [rcx],rax
+	xrelease lock cmpxchg QWORD PTR [rcx],rax
+	lock xrelease cmpxchg QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf2; cmpxchg QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf3; cmpxchg QWORD PTR [rcx],rax
+	xacquire lock xadd QWORD PTR [rcx],rax
+	lock xacquire xadd QWORD PTR [rcx],rax
+	xrelease lock xadd QWORD PTR [rcx],rax
+	lock xrelease xadd QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf2; xadd QWORD PTR [rcx],rax
+	.byte 0xf0; .byte 0xf3; xadd QWORD PTR [rcx],rax
+
+# Tests for op regb/m8
+	xacquire lock dec BYTE PTR [rcx]
+	lock xacquire dec BYTE PTR [rcx]
+	xrelease lock dec BYTE PTR [rcx]
+	lock xrelease dec BYTE PTR [rcx]
+	.byte 0xf0; .byte 0xf2; dec BYTE PTR [rcx]
+	.byte 0xf0; .byte 0xf3; dec BYTE PTR [rcx]
+	xacquire lock inc BYTE PTR [rcx]
+	lock xacquire inc BYTE PTR [rcx]
+	xrelease lock inc BYTE PTR [rcx]
+	lock xrelease inc BYTE PTR [rcx]
+	.byte 0xf0; .byte 0xf2; inc BYTE PTR [rcx]
+	.byte 0xf0; .byte 0xf3; inc BYTE PTR [rcx]
+	xacquire lock neg BYTE PTR [rcx]
+	lock xacquire neg BYTE PTR [rcx]
+	xrelease lock neg BYTE PTR [rcx]
+	lock xrelease neg BYTE PTR [rcx]
+	.byte 0xf0; .byte 0xf2; neg BYTE PTR [rcx]
+	.byte 0xf0; .byte 0xf3; neg BYTE PTR [rcx]
+	xacquire lock not BYTE PTR [rcx]
+	lock xacquire not BYTE PTR [rcx]
+	xrelease lock not BYTE PTR [rcx]
+	lock xrelease not BYTE PTR [rcx]
+	.byte 0xf0; .byte 0xf2; not BYTE PTR [rcx]
+	.byte 0xf0; .byte 0xf3; not BYTE PTR [rcx]
+
+# Tests for op regs/m16
+	xacquire lock dec WORD PTR [rcx]
+	lock xacquire dec WORD PTR [rcx]
+	xrelease lock dec WORD PTR [rcx]
+	lock xrelease dec WORD PTR [rcx]
+	.byte 0xf0; .byte 0xf2; dec WORD PTR [rcx]
+	.byte 0xf0; .byte 0xf3; dec WORD PTR [rcx]
+	xacquire lock inc WORD PTR [rcx]
+	lock xacquire inc WORD PTR [rcx]
+	xrelease lock inc WORD PTR [rcx]
+	lock xrelease inc WORD PTR [rcx]
+	.byte 0xf0; .byte 0xf2; inc WORD PTR [rcx]
+	.byte 0xf0; .byte 0xf3; inc WORD PTR [rcx]
+	xacquire lock neg WORD PTR [rcx]
+	lock xacquire neg WORD PTR [rcx]
+	xrelease lock neg WORD PTR [rcx]
+	lock xrelease neg WORD PTR [rcx]
+	.byte 0xf0; .byte 0xf2; neg WORD PTR [rcx]
+	.byte 0xf0; .byte 0xf3; neg WORD PTR [rcx]
+	xacquire lock not WORD PTR [rcx]
+	lock xacquire not WORD PTR [rcx]
+	xrelease lock not WORD PTR [rcx]
+	lock xrelease not WORD PTR [rcx]
+	.byte 0xf0; .byte 0xf2; not WORD PTR [rcx]
+	.byte 0xf0; .byte 0xf3; not WORD PTR [rcx]
+
+# Tests for op regl/m32
+	xacquire lock dec DWORD PTR [rcx]
+	lock xacquire dec DWORD PTR [rcx]
+	xrelease lock dec DWORD PTR [rcx]
+	lock xrelease dec DWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf2; dec DWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf3; dec DWORD PTR [rcx]
+	xacquire lock inc DWORD PTR [rcx]
+	lock xacquire inc DWORD PTR [rcx]
+	xrelease lock inc DWORD PTR [rcx]
+	lock xrelease inc DWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf2; inc DWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf3; inc DWORD PTR [rcx]
+	xacquire lock neg DWORD PTR [rcx]
+	lock xacquire neg DWORD PTR [rcx]
+	xrelease lock neg DWORD PTR [rcx]
+	lock xrelease neg DWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf2; neg DWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf3; neg DWORD PTR [rcx]
+	xacquire lock not DWORD PTR [rcx]
+	lock xacquire not DWORD PTR [rcx]
+	xrelease lock not DWORD PTR [rcx]
+	lock xrelease not DWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf2; not DWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf3; not DWORD PTR [rcx]
+
+# Tests for op regq/m64
+	xacquire lock dec QWORD PTR [rcx]
+	lock xacquire dec QWORD PTR [rcx]
+	xrelease lock dec QWORD PTR [rcx]
+	lock xrelease dec QWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf2; dec QWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf3; dec QWORD PTR [rcx]
+	xacquire lock inc QWORD PTR [rcx]
+	lock xacquire inc QWORD PTR [rcx]
+	xrelease lock inc QWORD PTR [rcx]
+	lock xrelease inc QWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf2; inc QWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf3; inc QWORD PTR [rcx]
+	xacquire lock neg QWORD PTR [rcx]
+	lock xacquire neg QWORD PTR [rcx]
+	xrelease lock neg QWORD PTR [rcx]
+	lock xrelease neg QWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf2; neg QWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf3; neg QWORD PTR [rcx]
+	xacquire lock not QWORD PTR [rcx]
+	lock xacquire not QWORD PTR [rcx]
+	xrelease lock not QWORD PTR [rcx]
+	lock xrelease not QWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf2; not QWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf3; not QWORD PTR [rcx]
+
+# Tests for op m64
+	xacquire lock cmpxchg8b QWORD PTR [rcx]
+	lock xacquire cmpxchg8b QWORD PTR [rcx]
+	xrelease lock cmpxchg8b QWORD PTR [rcx]
+	lock xrelease cmpxchg8b QWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf2; cmpxchg8b QWORD PTR [rcx]
+	.byte 0xf0; .byte 0xf3; cmpxchg8b QWORD PTR [rcx]
+
+# Tests for op regb, regb/m8
+	xacquire lock cmpxchg BYTE PTR [rcx],cl
+	lock xacquire cmpxchg BYTE PTR [rcx],cl
+	xrelease lock cmpxchg BYTE PTR [rcx],cl
+	lock xrelease cmpxchg BYTE PTR [rcx],cl
+	.byte 0xf0; .byte 0xf2; cmpxchg BYTE PTR [rcx],cl
+	.byte 0xf0; .byte 0xf3; cmpxchg BYTE PTR [rcx],cl
+	xacquire lock xadd BYTE PTR [rcx],cl
+	lock xacquire xadd BYTE PTR [rcx],cl
+	xrelease lock xadd BYTE PTR [rcx],cl
+	lock xrelease xadd BYTE PTR [rcx],cl
+	.byte 0xf0; .byte 0xf2; xadd BYTE PTR [rcx],cl
+	.byte 0xf0; .byte 0xf3; xadd BYTE PTR [rcx],cl
diff --git a/gas/testsuite/gas/i386/x86-64-hlebad.l b/gas/testsuite/gas/i386/x86-64-hlebad.l
new file mode 100644
index 0000000..2193e56
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-hlebad.l
@@ -0,0 +1,1087 @@
+.*: Assembler messages:
+.*:8: Error: .*
+.*:9: Error: .*
+.*:10: Error: .*
+.*:11: Error: .*
+.*:12: Error: .*
+.*:13: Error: .*
+.*:16: Error: .*
+.*:17: Error: .*
+.*:18: Error: .*
+.*:19: Error: .*
+.*:20: Error: .*
+.*:21: Error: .*
+.*:24: Error: .*
+.*:25: Error: .*
+.*:26: Error: .*
+.*:27: Error: .*
+.*:28: Error: .*
+.*:29: Error: .*
+.*:33: Error: .*
+.*:34: Error: .*
+.*:35: Error: .*
+.*:36: Error: .*
+.*:37: Error: .*
+.*:38: Error: .*
+.*:41: Error: .*
+.*:42: Error: .*
+.*:43: Error: .*
+.*:44: Error: .*
+.*:45: Error: .*
+.*:46: Error: .*
+.*:47: Error: .*
+.*:48: Error: .*
+.*:51: Error: .*
+.*:52: Error: .*
+.*:53: Error: .*
+.*:54: Error: .*
+.*:55: Error: .*
+.*:56: Error: .*
+.*:57: Error: .*
+.*:58: Error: .*
+.*:61: Error: .*
+.*:62: Error: .*
+.*:63: Error: .*
+.*:64: Error: .*
+.*:65: Error: .*
+.*:66: Error: .*
+.*:67: Error: .*
+.*:68: Error: .*
+.*:71: Error: .*
+.*:72: Error: .*
+.*:73: Error: .*
+.*:74: Error: .*
+.*:75: Error: .*
+.*:76: Error: .*
+.*:77: Error: .*
+.*:78: Error: .*
+.*:81: Error: .*
+.*:82: Error: .*
+.*:83: Error: .*
+.*:84: Error: .*
+.*:85: Error: .*
+.*:86: Error: .*
+.*:87: Error: .*
+.*:88: Error: .*
+.*:91: Error: .*
+.*:92: Error: .*
+.*:93: Error: .*
+.*:94: Error: .*
+.*:95: Error: .*
+.*:96: Error: .*
+.*:97: Error: .*
+.*:98: Error: .*
+.*:101: Error: .*
+.*:102: Error: .*
+.*:103: Error: .*
+.*:104: Error: .*
+.*:105: Error: .*
+.*:106: Error: .*
+.*:107: Error: .*
+.*:108: Error: .*
+.*:111: Error: .*
+.*:112: Error: .*
+.*:113: Error: .*
+.*:114: Error: .*
+.*:115: Error: .*
+.*:116: Error: .*
+.*:117: Error: .*
+.*:118: Error: .*
+.*:122: Error: .*
+.*:123: Error: .*
+.*:124: Error: .*
+.*:125: Error: .*
+.*:126: Error: .*
+.*:127: Error: .*
+.*:128: Error: .*
+.*:129: Error: .*
+.*:130: Error: .*
+.*:131: Error: .*
+.*:132: Error: .*
+.*:133: Error: .*
+.*:134: Error: .*
+.*:135: Error: .*
+.*:136: Error: .*
+.*:137: Error: .*
+.*:138: Error: .*
+.*:139: Error: .*
+.*:140: Error: .*
+.*:141: Error: .*
+.*:145: Error: .*
+.*:146: Error: .*
+.*:147: Error: .*
+.*:148: Error: .*
+.*:149: Error: .*
+.*:150: Error: .*
+.*:151: Error: .*
+.*:152: Error: .*
+.*:153: Error: .*
+.*:154: Error: .*
+.*:155: Error: .*
+.*:156: Error: .*
+.*:157: Error: .*
+.*:158: Error: .*
+.*:159: Error: .*
+.*:160: Error: .*
+.*:161: Error: .*
+.*:162: Error: .*
+.*:163: Error: .*
+.*:164: Error: .*
+.*:168: Error: .*
+.*:169: Error: .*
+.*:170: Error: .*
+.*:171: Error: .*
+.*:172: Error: .*
+.*:173: Error: .*
+.*:174: Error: .*
+.*:175: Error: .*
+.*:176: Error: .*
+.*:177: Error: .*
+.*:178: Error: .*
+.*:179: Error: .*
+.*:180: Error: .*
+.*:181: Error: .*
+.*:182: Error: .*
+.*:183: Error: .*
+.*:184: Error: .*
+.*:185: Error: .*
+.*:186: Error: .*
+.*:187: Error: .*
+.*:191: Error: .*
+.*:192: Error: .*
+.*:193: Error: .*
+.*:194: Error: .*
+.*:195: Error: .*
+.*:196: Error: .*
+.*:197: Error: .*
+.*:198: Error: .*
+.*:199: Error: .*
+.*:200: Error: .*
+.*:201: Error: .*
+.*:202: Error: .*
+.*:203: Error: .*
+.*:204: Error: .*
+.*:205: Error: .*
+.*:206: Error: .*
+.*:207: Error: .*
+.*:208: Error: .*
+.*:209: Error: .*
+.*:210: Error: .*
+.*:213: Error: .*
+.*:214: Error: .*
+.*:215: Error: .*
+.*:216: Error: .*
+.*:217: Error: .*
+.*:218: Error: .*
+.*:219: Error: .*
+.*:220: Error: .*
+.*:223: Error: .*
+.*:224: Error: .*
+.*:225: Error: .*
+.*:226: Error: .*
+.*:227: Error: .*
+.*:228: Error: .*
+.*:229: Error: .*
+.*:230: Error: .*
+.*:233: Error: .*
+.*:234: Error: .*
+.*:235: Error: .*
+.*:236: Error: .*
+.*:237: Error: .*
+.*:238: Error: .*
+.*:239: Error: .*
+.*:240: Error: .*
+.*:243: Error: .*
+.*:244: Error: .*
+.*:245: Error: .*
+.*:246: Error: .*
+.*:247: Error: .*
+.*:248: Error: .*
+.*:249: Error: .*
+.*:250: Error: .*
+.*:253: Error: .*
+.*:254: Error: .*
+.*:255: Error: .*
+.*:256: Error: .*
+.*:257: Error: .*
+.*:258: Error: .*
+.*:259: Error: .*
+.*:260: Error: .*
+.*:263: Error: .*
+.*:264: Error: .*
+.*:265: Error: .*
+.*:266: Error: .*
+.*:267: Error: .*
+.*:268: Error: .*
+.*:269: Error: .*
+.*:270: Error: .*
+.*:273: Error: .*
+.*:274: Error: .*
+.*:275: Error: .*
+.*:276: Error: .*
+.*:277: Error: .*
+.*:278: Error: .*
+.*:279: Error: .*
+.*:280: Error: .*
+.*:283: Error: .*
+.*:284: Error: .*
+.*:287: Error: .*
+.*:288: Error: .*
+.*:289: Error: .*
+.*:290: Error: .*
+.*:291: Error: .*
+.*:292: Error: .*
+.*:293: Error: .*
+.*:294: Error: .*
+.*:299: Error: .*
+.*:300: Error: .*
+.*:301: Error: .*
+.*:302: Error: .*
+.*:303: Error: .*
+.*:304: Error: .*
+.*:307: Error: .*
+.*:308: Error: .*
+.*:309: Error: .*
+.*:310: Error: .*
+.*:311: Error: .*
+.*:312: Error: .*
+.*:315: Error: .*
+.*:316: Error: .*
+.*:317: Error: .*
+.*:318: Error: .*
+.*:319: Error: .*
+.*:320: Error: .*
+.*:324: Error: .*
+.*:325: Error: .*
+.*:326: Error: .*
+.*:327: Error: .*
+.*:328: Error: .*
+.*:329: Error: .*
+.*:332: Error: .*
+.*:333: Error: .*
+.*:334: Error: .*
+.*:335: Error: .*
+.*:336: Error: .*
+.*:337: Error: .*
+.*:338: Error: .*
+.*:339: Error: .*
+.*:342: Error: .*
+.*:343: Error: .*
+.*:344: Error: .*
+.*:345: Error: .*
+.*:346: Error: .*
+.*:347: Error: .*
+.*:348: Error: .*
+.*:349: Error: .*
+.*:352: Error: .*
+.*:353: Error: .*
+.*:354: Error: .*
+.*:355: Error: .*
+.*:356: Error: .*
+.*:357: Error: .*
+.*:358: Error: .*
+.*:359: Error: .*
+.*:362: Error: .*
+.*:363: Error: .*
+.*:364: Error: .*
+.*:365: Error: .*
+.*:366: Error: .*
+.*:367: Error: .*
+.*:368: Error: .*
+.*:369: Error: .*
+.*:372: Error: .*
+.*:373: Error: .*
+.*:374: Error: .*
+.*:375: Error: .*
+.*:376: Error: .*
+.*:377: Error: .*
+.*:378: Error: .*
+.*:379: Error: .*
+.*:382: Error: .*
+.*:383: Error: .*
+.*:384: Error: .*
+.*:385: Error: .*
+.*:386: Error: .*
+.*:387: Error: .*
+.*:388: Error: .*
+.*:389: Error: .*
+.*:392: Error: .*
+.*:393: Error: .*
+.*:394: Error: .*
+.*:395: Error: .*
+.*:396: Error: .*
+.*:397: Error: .*
+.*:398: Error: .*
+.*:399: Error: .*
+.*:402: Error: .*
+.*:403: Error: .*
+.*:404: Error: .*
+.*:405: Error: .*
+.*:406: Error: .*
+.*:407: Error: .*
+.*:408: Error: .*
+.*:409: Error: .*
+.*:413: Error: .*
+.*:414: Error: .*
+.*:415: Error: .*
+.*:416: Error: .*
+.*:417: Error: .*
+.*:418: Error: .*
+.*:419: Error: .*
+.*:420: Error: .*
+.*:421: Error: .*
+.*:422: Error: .*
+.*:423: Error: .*
+.*:424: Error: .*
+.*:425: Error: .*
+.*:426: Error: .*
+.*:427: Error: .*
+.*:428: Error: .*
+.*:429: Error: .*
+.*:430: Error: .*
+.*:431: Error: .*
+.*:432: Error: .*
+.*:436: Error: .*
+.*:437: Error: .*
+.*:438: Error: .*
+.*:439: Error: .*
+.*:440: Error: .*
+.*:441: Error: .*
+.*:442: Error: .*
+.*:443: Error: .*
+.*:444: Error: .*
+.*:445: Error: .*
+.*:446: Error: .*
+.*:447: Error: .*
+.*:448: Error: .*
+.*:449: Error: .*
+.*:450: Error: .*
+.*:451: Error: .*
+.*:452: Error: .*
+.*:453: Error: .*
+.*:454: Error: .*
+.*:455: Error: .*
+.*:459: Error: .*
+.*:460: Error: .*
+.*:461: Error: .*
+.*:462: Error: .*
+.*:463: Error: .*
+.*:464: Error: .*
+.*:465: Error: .*
+.*:466: Error: .*
+.*:467: Error: .*
+.*:468: Error: .*
+.*:469: Error: .*
+.*:470: Error: .*
+.*:471: Error: .*
+.*:472: Error: .*
+.*:473: Error: .*
+.*:474: Error: .*
+.*:475: Error: .*
+.*:476: Error: .*
+.*:477: Error: .*
+.*:478: Error: .*
+.*:482: Error: .*
+.*:483: Error: .*
+.*:484: Error: .*
+.*:485: Error: .*
+.*:486: Error: .*
+.*:487: Error: .*
+.*:488: Error: .*
+.*:489: Error: .*
+.*:490: Error: .*
+.*:491: Error: .*
+.*:492: Error: .*
+.*:493: Error: .*
+.*:494: Error: .*
+.*:495: Error: .*
+.*:496: Error: .*
+.*:497: Error: .*
+.*:498: Error: .*
+.*:499: Error: .*
+.*:500: Error: .*
+.*:501: Error: .*
+.*:504: Error: .*
+.*:505: Error: .*
+.*:506: Error: .*
+.*:507: Error: .*
+.*:508: Error: .*
+.*:509: Error: .*
+.*:510: Error: .*
+.*:511: Error: .*
+.*:514: Error: .*
+.*:515: Error: .*
+.*:516: Error: .*
+.*:517: Error: .*
+.*:518: Error: .*
+.*:519: Error: .*
+.*:520: Error: .*
+.*:521: Error: .*
+.*:524: Error: .*
+.*:525: Error: .*
+.*:526: Error: .*
+.*:527: Error: .*
+.*:528: Error: .*
+.*:529: Error: .*
+.*:530: Error: .*
+.*:531: Error: .*
+.*:534: Error: .*
+.*:535: Error: .*
+.*:536: Error: .*
+.*:537: Error: .*
+.*:538: Error: .*
+.*:539: Error: .*
+.*:540: Error: .*
+.*:541: Error: .*
+.*:544: Error: .*
+.*:545: Error: .*
+.*:546: Error: .*
+.*:547: Error: .*
+.*:548: Error: .*
+.*:549: Error: .*
+.*:550: Error: .*
+.*:551: Error: .*
+.*:554: Error: .*
+.*:555: Error: .*
+.*:556: Error: .*
+.*:557: Error: .*
+.*:558: Error: .*
+.*:559: Error: .*
+.*:560: Error: .*
+.*:561: Error: .*
+.*:564: Error: .*
+.*:565: Error: .*
+.*:566: Error: .*
+.*:567: Error: .*
+.*:568: Error: .*
+.*:569: Error: .*
+.*:570: Error: .*
+.*:571: Error: .*
+.*:574: Error: .*
+.*:575: Error: .*
+.*:578: Error: .*
+.*:579: Error: .*
+.*:580: Error: .*
+.*:581: Error: .*
+.*:582: Error: .*
+.*:583: Error: .*
+.*:584: Error: .*
+.*:585: Error: .*
+GAS LISTING .*
+
+
+[ 	]*1[ 	]+\# Check 64bit unsupported HLE instructions
+[ 	]*2[ 	]+
+[ 	]*3[ 	]+\.allow_index_reg
+[ 	]*4[ 	]+\.text
+[ 	]*5[ 	]+_start:
+[ 	]*6[ 	]+
+[ 	]*7[ 	]+\# Tests for op imm8 al
+[ 	]*8[ 	]+xacquire adc \$100,%al
+[ 	]*9[ 	]+xacquire lock adc \$100,%al
+[ 	]*10[ 	]+lock xacquire adc \$100,%al
+[ 	]*11[ 	]+xrelease adc \$100,%al
+[ 	]*12[ 	]+xrelease lock adc \$100,%al
+[ 	]*13[ 	]+lock xrelease adc \$100,%al
+[ 	]*14[ 	]+
+[ 	]*15[ 	]+\# Tests for op imm16 ax
+[ 	]*16[ 	]+xacquire adc \$1000,%ax
+[ 	]*17[ 	]+xacquire lock adc \$1000,%ax
+[ 	]*18[ 	]+lock xacquire adc \$1000,%ax
+[ 	]*19[ 	]+xrelease adc \$1000,%ax
+[ 	]*20[ 	]+xrelease lock adc \$1000,%ax
+[ 	]*21[ 	]+lock xrelease adc \$1000,%ax
+[ 	]*22[ 	]+
+[ 	]*23[ 	]+\# Tests for op imm32 eax
+[ 	]*24[ 	]+xacquire adc \$10000000,%eax
+[ 	]*25[ 	]+xacquire lock adc \$10000000,%eax
+[ 	]*26[ 	]+lock xacquire adc \$10000000,%eax
+[ 	]*27[ 	]+xrelease adc \$10000000,%eax
+[ 	]*28[ 	]+xrelease lock adc \$10000000,%eax
+[ 	]*29[ 	]+lock xrelease adc \$10000000,%eax
+[ 	]*30[ 	]+
+[ 	]*31[ 	]+
+[ 	]*32[ 	]+\# Tests for op imm32 rax
+[ 	]*33[ 	]+xacquire adc \$10000000,%rax
+[ 	]*34[ 	]+xacquire lock adc \$10000000,%rax
+[ 	]*35[ 	]+lock xacquire adc \$10000000,%rax
+[ 	]*36[ 	]+xrelease adc \$10000000,%rax
+[ 	]*37[ 	]+xrelease lock adc \$10000000,%rax
+[ 	]*38[ 	]+lock xrelease adc \$10000000,%rax
+[ 	]*39[ 	]+
+[ 	]*40[ 	]+\# Tests for op imm8 regb/m8
+[ 	]*41[ 	]+xacquire adcb \$100,%cl
+[ 	]*42[ 	]+xacquire lock adcb \$100,%cl
+[ 	]*43[ 	]+lock xacquire adcb \$100,%cl
+[ 	]*44[ 	]+xrelease adcb \$100,%cl
+[ 	]*45[ 	]+xrelease lock adcb \$100,%cl
+[ 	]*46[ 	]+lock xrelease adcb \$100,%cl
+[ 	]*47[ 	]+xacquire adcb \$100,\(%rcx\)
+[ 	]*48[ 	]+xrelease adcb \$100,\(%rcx\)
+[ 	]*49[ 	]+
+[ 	]*50[ 	]+\# Tests for op imm16 regs/m16
+[ 	]*51[ 	]+xacquire adcw \$1000,%cx
+[ 	]*52[ 	]+xacquire lock adcw \$1000,%cx
+[ 	]*53[ 	]+lock xacquire adcw \$1000,%cx
+[ 	]*54[ 	]+xrelease adcw \$1000,%cx
+[ 	]*55[ 	]+xrelease lock adcw \$1000,%cx
+[ 	]*56[ 	]+lock xrelease adcw \$1000,%cx
+[ 	]*57[ 	]+xacquire adcw \$1000,\(%rcx\)
+GAS LISTING .*
+
+
+[ 	]*58[ 	]+xrelease adcw \$1000,\(%rcx\)
+[ 	]*59[ 	]+
+[ 	]*60[ 	]+\# Tests for op imm32 regl/m32
+[ 	]*61[ 	]+xacquire adcl \$10000000,%ecx
+[ 	]*62[ 	]+xacquire lock adcl \$10000000,%ecx
+[ 	]*63[ 	]+lock xacquire adcl \$10000000,%ecx
+[ 	]*64[ 	]+xrelease adcl \$10000000,%ecx
+[ 	]*65[ 	]+xrelease lock adcl \$10000000,%ecx
+[ 	]*66[ 	]+lock xrelease adcl \$10000000,%ecx
+[ 	]*67[ 	]+xacquire adcl \$10000000,\(%rcx\)
+[ 	]*68[ 	]+xrelease adcl \$10000000,\(%rcx\)
+[ 	]*69[ 	]+
+[ 	]*70[ 	]+\# Tests for op imm32 regq/m64
+[ 	]*71[ 	]+xacquire adcq \$10000000,%rcx
+[ 	]*72[ 	]+xacquire lock adcq \$10000000,%rcx
+[ 	]*73[ 	]+lock xacquire adcq \$10000000,%rcx
+[ 	]*74[ 	]+xrelease adcq \$10000000,%rcx
+[ 	]*75[ 	]+xrelease lock adcq \$10000000,%rcx
+[ 	]*76[ 	]+lock xrelease adcq \$10000000,%rcx
+[ 	]*77[ 	]+xacquire adcq \$10000000,\(%rcx\)
+[ 	]*78[ 	]+xrelease adcq \$10000000,\(%rcx\)
+[ 	]*79[ 	]+
+[ 	]*80[ 	]+\# Tests for op imm8 regs/m16
+[ 	]*81[ 	]+xacquire adcw \$100,%cx
+[ 	]*82[ 	]+xacquire lock adcw \$100,%cx
+[ 	]*83[ 	]+lock xacquire adcw \$100,%cx
+[ 	]*84[ 	]+xrelease adcw \$100,%cx
+[ 	]*85[ 	]+xrelease lock adcw \$100,%cx
+[ 	]*86[ 	]+lock xrelease adcw \$100,%cx
+[ 	]*87[ 	]+xacquire adcw \$100,\(%rcx\)
+[ 	]*88[ 	]+xrelease adcw \$100,\(%rcx\)
+[ 	]*89[ 	]+
+[ 	]*90[ 	]+\# Tests for op imm8 regl/m32
+[ 	]*91[ 	]+xacquire adcl \$100,%ecx
+[ 	]*92[ 	]+xacquire lock adcl \$100,%ecx
+[ 	]*93[ 	]+lock xacquire adcl \$100,%ecx
+[ 	]*94[ 	]+xrelease adcl \$100,%ecx
+[ 	]*95[ 	]+xrelease lock adcl \$100,%ecx
+[ 	]*96[ 	]+lock xrelease adcl \$100,%ecx
+[ 	]*97[ 	]+xacquire adcl \$100,\(%rcx\)
+[ 	]*98[ 	]+xrelease adcl \$100,\(%rcx\)
+[ 	]*99[ 	]+
+[ 	]*100[ 	]+\# Tests for op imm8 regq/m64
+[ 	]*101[ 	]+xacquire adcq \$100,%rcx
+[ 	]*102[ 	]+xacquire lock adcq \$100,%rcx
+[ 	]*103[ 	]+lock xacquire adcq \$100,%rcx
+[ 	]*104[ 	]+xrelease adcq \$100,%rcx
+[ 	]*105[ 	]+xrelease lock adcq \$100,%rcx
+[ 	]*106[ 	]+lock xrelease adcq \$100,%rcx
+[ 	]*107[ 	]+xacquire adcq \$100,\(%rcx\)
+[ 	]*108[ 	]+xrelease adcq \$100,\(%rcx\)
+[ 	]*109[ 	]+
+[ 	]*110[ 	]+\# Tests for op imm8 regb/m8
+[ 	]*111[ 	]+xacquire adcb \$100,%cl
+[ 	]*112[ 	]+xacquire lock adcb \$100,%cl
+[ 	]*113[ 	]+lock xacquire adcb \$100,%cl
+[ 	]*114[ 	]+xrelease adcb \$100,%cl
+GAS LISTING .*
+
+
+[ 	]*115[ 	]+xrelease lock adcb \$100,%cl
+[ 	]*116[ 	]+lock xrelease adcb \$100,%cl
+[ 	]*117[ 	]+xacquire adcb \$100,\(%rcx\)
+[ 	]*118[ 	]+xrelease adcb \$100,\(%rcx\)
+[ 	]*119[ 	]+
+[ 	]*120[ 	]+\# Tests for op regb regb/m8
+[ 	]*121[ 	]+\# Tests for op regb/m8 regb
+[ 	]*122[ 	]+xacquire adcb %al,%cl
+[ 	]*123[ 	]+xacquire lock adcb %al,%cl
+[ 	]*124[ 	]+lock xacquire adcb %al,%cl
+[ 	]*125[ 	]+xrelease adcb %al,%cl
+[ 	]*126[ 	]+xrelease lock adcb %al,%cl
+[ 	]*127[ 	]+lock xrelease adcb %al,%cl
+[ 	]*128[ 	]+xacquire adcb %al,\(%rcx\)
+[ 	]*129[ 	]+xrelease adcb %al,\(%rcx\)
+[ 	]*130[ 	]+xacquire adcb %cl,%al
+[ 	]*131[ 	]+xacquire lock adcb %cl,%al
+[ 	]*132[ 	]+lock xacquire adcb %cl,%al
+[ 	]*133[ 	]+xrelease adcb %cl,%al
+[ 	]*134[ 	]+xrelease lock adcb %cl,%al
+[ 	]*135[ 	]+lock xrelease adcb %cl,%al
+[ 	]*136[ 	]+xacquire adcb \(%rcx\),%al
+[ 	]*137[ 	]+xacquire lock adcb \(%rcx\),%al
+[ 	]*138[ 	]+lock xacquire adcb \(%rcx\),%al
+[ 	]*139[ 	]+xrelease adcb \(%rcx\),%al
+[ 	]*140[ 	]+xrelease lock adcb \(%rcx\),%al
+[ 	]*141[ 	]+lock xrelease adcb \(%rcx\),%al
+[ 	]*142[ 	]+
+[ 	]*143[ 	]+\# Tests for op regs regs/m16
+[ 	]*144[ 	]+\# Tests for op regs/m16 regs
+[ 	]*145[ 	]+xacquire adcw %ax,%cx
+[ 	]*146[ 	]+xacquire lock adcw %ax,%cx
+[ 	]*147[ 	]+lock xacquire adcw %ax,%cx
+[ 	]*148[ 	]+xrelease adcw %ax,%cx
+[ 	]*149[ 	]+xrelease lock adcw %ax,%cx
+[ 	]*150[ 	]+lock xrelease adcw %ax,%cx
+[ 	]*151[ 	]+xacquire adcw %ax,\(%rcx\)
+[ 	]*152[ 	]+xrelease adcw %ax,\(%rcx\)
+[ 	]*153[ 	]+xacquire adcw %cx,%ax
+[ 	]*154[ 	]+xacquire lock adcw %cx,%ax
+[ 	]*155[ 	]+lock xacquire adcw %cx,%ax
+[ 	]*156[ 	]+xrelease adcw %cx,%ax
+[ 	]*157[ 	]+xrelease lock adcw %cx,%ax
+[ 	]*158[ 	]+lock xrelease adcw %cx,%ax
+[ 	]*159[ 	]+xacquire adcw \(%rcx\),%ax
+[ 	]*160[ 	]+xacquire lock adcw \(%rcx\),%ax
+[ 	]*161[ 	]+lock xacquire adcw \(%rcx\),%ax
+[ 	]*162[ 	]+xrelease adcw \(%rcx\),%ax
+[ 	]*163[ 	]+xrelease lock adcw \(%rcx\),%ax
+[ 	]*164[ 	]+lock xrelease adcw \(%rcx\),%ax
+[ 	]*165[ 	]+
+[ 	]*166[ 	]+\# Tests for op regl regl/m32
+[ 	]*167[ 	]+\# Tests for op regl/m32 regl
+[ 	]*168[ 	]+xacquire adcl %eax,%ecx
+[ 	]*169[ 	]+xacquire lock adcl %eax,%ecx
+[ 	]*170[ 	]+lock xacquire adcl %eax,%ecx
+[ 	]*171[ 	]+xrelease adcl %eax,%ecx
+GAS LISTING .*
+
+
+[ 	]*172[ 	]+xrelease lock adcl %eax,%ecx
+[ 	]*173[ 	]+lock xrelease adcl %eax,%ecx
+[ 	]*174[ 	]+xacquire adcl %eax,\(%rcx\)
+[ 	]*175[ 	]+xrelease adcl %eax,\(%rcx\)
+[ 	]*176[ 	]+xacquire adcl %ecx,%eax
+[ 	]*177[ 	]+xacquire lock adcl %ecx,%eax
+[ 	]*178[ 	]+lock xacquire adcl %ecx,%eax
+[ 	]*179[ 	]+xrelease adcl %ecx,%eax
+[ 	]*180[ 	]+xrelease lock adcl %ecx,%eax
+[ 	]*181[ 	]+lock xrelease adcl %ecx,%eax
+[ 	]*182[ 	]+xacquire adcl \(%rcx\),%eax
+[ 	]*183[ 	]+xacquire lock adcl \(%rcx\),%eax
+[ 	]*184[ 	]+lock xacquire adcl \(%rcx\),%eax
+[ 	]*185[ 	]+xrelease adcl \(%rcx\),%eax
+[ 	]*186[ 	]+xrelease lock adcl \(%rcx\),%eax
+[ 	]*187[ 	]+lock xrelease adcl \(%rcx\),%eax
+[ 	]*188[ 	]+
+[ 	]*189[ 	]+\# Tests for op regq regq/m64
+[ 	]*190[ 	]+\# Tests for op regq/m64 regq
+[ 	]*191[ 	]+xacquire adcq %rax,%rcx
+[ 	]*192[ 	]+xacquire lock adcq %rax,%rcx
+[ 	]*193[ 	]+lock xacquire adcq %rax,%rcx
+[ 	]*194[ 	]+xrelease adcq %rax,%rcx
+[ 	]*195[ 	]+xrelease lock adcq %rax,%rcx
+[ 	]*196[ 	]+lock xrelease adcq %rax,%rcx
+[ 	]*197[ 	]+xacquire adcq %rax,\(%rcx\)
+[ 	]*198[ 	]+xrelease adcq %rax,\(%rcx\)
+[ 	]*199[ 	]+xacquire adcq %rcx,%rax
+[ 	]*200[ 	]+xacquire lock adcq %rcx,%rax
+[ 	]*201[ 	]+lock xacquire adcq %rcx,%rax
+[ 	]*202[ 	]+xrelease adcq %rcx,%rax
+[ 	]*203[ 	]+xrelease lock adcq %rcx,%rax
+[ 	]*204[ 	]+lock xrelease adcq %rcx,%rax
+[ 	]*205[ 	]+xacquire adcq \(%rcx\),%rax
+[ 	]*206[ 	]+xacquire lock adcq \(%rcx\),%rax
+[ 	]*207[ 	]+lock xacquire adcq \(%rcx\),%rax
+[ 	]*208[ 	]+xrelease adcq \(%rcx\),%rax
+[ 	]*209[ 	]+xrelease lock adcq \(%rcx\),%rax
+[ 	]*210[ 	]+lock xrelease adcq \(%rcx\),%rax
+[ 	]*211[ 	]+
+[ 	]*212[ 	]+\# Tests for op regs, regs/m16
+[ 	]*213[ 	]+xacquire btcw %ax,%cx
+[ 	]*214[ 	]+xacquire lock btcw %ax,%cx
+[ 	]*215[ 	]+lock xacquire btcw %ax,%cx
+[ 	]*216[ 	]+xrelease btcw %ax,%cx
+[ 	]*217[ 	]+xrelease lock btcw %ax,%cx
+[ 	]*218[ 	]+lock xrelease btcw %ax,%cx
+[ 	]*219[ 	]+xacquire btcw %ax,\(%rcx\)
+[ 	]*220[ 	]+xrelease btcw %ax,\(%rcx\)
+[ 	]*221[ 	]+
+[ 	]*222[ 	]+\# Tests for op regl regl/m32
+[ 	]*223[ 	]+xacquire btcl %eax,%ecx
+[ 	]*224[ 	]+xacquire lock btcl %eax,%ecx
+[ 	]*225[ 	]+lock xacquire btcl %eax,%ecx
+[ 	]*226[ 	]+xrelease btcl %eax,%ecx
+[ 	]*227[ 	]+xrelease lock btcl %eax,%ecx
+[ 	]*228[ 	]+lock xrelease btcl %eax,%ecx
+GAS LISTING .*
+
+
+[ 	]*229[ 	]+xacquire btcl %eax,\(%rcx\)
+[ 	]*230[ 	]+xrelease btcl %eax,\(%rcx\)
+[ 	]*231[ 	]+
+[ 	]*232[ 	]+\# Tests for op regq regq/m64
+[ 	]*233[ 	]+xacquire btcq %rax,%rcx
+[ 	]*234[ 	]+xacquire lock btcq %rax,%rcx
+[ 	]*235[ 	]+lock xacquire btcq %rax,%rcx
+[ 	]*236[ 	]+xrelease btcq %rax,%rcx
+[ 	]*237[ 	]+xrelease lock btcq %rax,%rcx
+[ 	]*238[ 	]+lock xrelease btcq %rax,%rcx
+[ 	]*239[ 	]+xacquire btcq %rax,\(%rcx\)
+[ 	]*240[ 	]+xrelease btcq %rax,\(%rcx\)
+[ 	]*241[ 	]+
+[ 	]*242[ 	]+\# Tests for op regb/m8
+[ 	]*243[ 	]+xacquire decb %cl
+[ 	]*244[ 	]+xacquire lock decb %cl
+[ 	]*245[ 	]+lock xacquire decb %cl
+[ 	]*246[ 	]+xrelease decb %cl
+[ 	]*247[ 	]+xrelease lock decb %cl
+[ 	]*248[ 	]+lock xrelease decb %cl
+[ 	]*249[ 	]+xacquire decb \(%rcx\)
+[ 	]*250[ 	]+xrelease decb \(%rcx\)
+[ 	]*251[ 	]+
+[ 	]*252[ 	]+\# Tests for op regs/m16
+[ 	]*253[ 	]+xacquire decw %cx
+[ 	]*254[ 	]+xacquire lock decw %cx
+[ 	]*255[ 	]+lock xacquire decw %cx
+[ 	]*256[ 	]+xrelease decw %cx
+[ 	]*257[ 	]+xrelease lock decw %cx
+[ 	]*258[ 	]+lock xrelease decw %cx
+[ 	]*259[ 	]+xacquire decw \(%rcx\)
+[ 	]*260[ 	]+xrelease decw \(%rcx\)
+[ 	]*261[ 	]+
+[ 	]*262[ 	]+\# Tests for op regl/m32
+[ 	]*263[ 	]+xacquire decl %ecx
+[ 	]*264[ 	]+xacquire lock decl %ecx
+[ 	]*265[ 	]+lock xacquire decl %ecx
+[ 	]*266[ 	]+xrelease decl %ecx
+[ 	]*267[ 	]+xrelease lock decl %ecx
+[ 	]*268[ 	]+lock xrelease decl %ecx
+[ 	]*269[ 	]+xacquire decl \(%rcx\)
+[ 	]*270[ 	]+xrelease decl \(%rcx\)
+[ 	]*271[ 	]+
+[ 	]*272[ 	]+\# Tests for op regq/m64
+[ 	]*273[ 	]+xacquire decq %rcx
+[ 	]*274[ 	]+xacquire lock decq %rcx
+[ 	]*275[ 	]+lock xacquire decq %rcx
+[ 	]*276[ 	]+xrelease decq %rcx
+[ 	]*277[ 	]+xrelease lock decq %rcx
+[ 	]*278[ 	]+lock xrelease decq %rcx
+[ 	]*279[ 	]+xacquire decq \(%rcx\)
+[ 	]*280[ 	]+xrelease decq \(%rcx\)
+[ 	]*281[ 	]+
+[ 	]*282[ 	]+\# Tests for op m64
+[ 	]*283[ 	]+xacquire cmpxchg8bq \(%rcx\)
+[ 	]*284[ 	]+xrelease cmpxchg8bq \(%rcx\)
+[ 	]*285[ 	]+
+GAS LISTING .*
+
+
+[ 	]*286[ 	]+\# Tests for op regb, regb/m8
+[ 	]*287[ 	]+xacquire cmpxchgb %cl,%al
+[ 	]*288[ 	]+xacquire lock cmpxchgb %cl,%al
+[ 	]*289[ 	]+lock xacquire cmpxchgb %cl,%al
+[ 	]*290[ 	]+xrelease cmpxchgb %cl,%al
+[ 	]*291[ 	]+xrelease lock cmpxchgb %cl,%al
+[ 	]*292[ 	]+lock xrelease cmpxchgb %cl,%al
+[ 	]*293[ 	]+xacquire cmpxchgb %cl,\(%rcx\)
+[ 	]*294[ 	]+xrelease cmpxchgb %cl,\(%rcx\)
+[ 	]*295[ 	]+
+[ 	]*296[ 	]+\.intel_syntax noprefix
+[ 	]*297[ 	]+
+[ 	]*298[ 	]+\# Tests for op imm8 al
+[ 	]*299[ 	]+xacquire adc al,100
+[ 	]*300[ 	]+xacquire lock adc al,100
+[ 	]*301[ 	]+lock xacquire adc al,100
+[ 	]*302[ 	]+xrelease adc al,100
+[ 	]*303[ 	]+xrelease lock adc al,100
+[ 	]*304[ 	]+lock xrelease adc al,100
+[ 	]*305[ 	]+
+[ 	]*306[ 	]+\# Tests for op imm16 ax
+[ 	]*307[ 	]+xacquire adc ax,1000
+[ 	]*308[ 	]+xacquire lock adc ax,1000
+[ 	]*309[ 	]+lock xacquire adc ax,1000
+[ 	]*310[ 	]+xrelease adc ax,1000
+[ 	]*311[ 	]+xrelease lock adc ax,1000
+[ 	]*312[ 	]+lock xrelease adc ax,1000
+[ 	]*313[ 	]+
+[ 	]*314[ 	]+\# Tests for op imm32 eax
+[ 	]*315[ 	]+xacquire adc eax,10000000
+[ 	]*316[ 	]+xacquire lock adc eax,10000000
+[ 	]*317[ 	]+lock xacquire adc eax,10000000
+[ 	]*318[ 	]+xrelease adc eax,10000000
+[ 	]*319[ 	]+xrelease lock adc eax,10000000
+[ 	]*320[ 	]+lock xrelease adc eax,10000000
+[ 	]*321[ 	]+
+[ 	]*322[ 	]+
+[ 	]*323[ 	]+\# Tests for op imm32 rax
+[ 	]*324[ 	]+xacquire adc rax,10000000
+[ 	]*325[ 	]+xacquire lock adc rax,10000000
+[ 	]*326[ 	]+lock xacquire adc rax,10000000
+[ 	]*327[ 	]+xrelease adc rax,10000000
+[ 	]*328[ 	]+xrelease lock adc rax,10000000
+[ 	]*329[ 	]+lock xrelease adc rax,10000000
+[ 	]*330[ 	]+
+[ 	]*331[ 	]+\# Tests for op imm8 regb/m8
+[ 	]*332[ 	]+xacquire adc cl,100
+[ 	]*333[ 	]+xacquire lock adc cl,100
+[ 	]*334[ 	]+lock xacquire adc cl,100
+[ 	]*335[ 	]+xrelease adc cl,100
+[ 	]*336[ 	]+xrelease lock adc cl,100
+[ 	]*337[ 	]+lock xrelease adc cl,100
+[ 	]*338[ 	]+xacquire adc BYTE PTR \[rcx\],100
+[ 	]*339[ 	]+xrelease adc BYTE PTR \[rcx\],100
+[ 	]*340[ 	]+
+[ 	]*341[ 	]+\# Tests for op imm16 regs/m16
+[ 	]*342[ 	]+xacquire adc cx,1000
+GAS LISTING .*
+
+
+[ 	]*343[ 	]+xacquire lock adc cx,1000
+[ 	]*344[ 	]+lock xacquire adc cx,1000
+[ 	]*345[ 	]+xrelease adc cx,1000
+[ 	]*346[ 	]+xrelease lock adc cx,1000
+[ 	]*347[ 	]+lock xrelease adc cx,1000
+[ 	]*348[ 	]+xacquire adc WORD PTR \[rcx\],1000
+[ 	]*349[ 	]+xrelease adc WORD PTR \[rcx\],1000
+[ 	]*350[ 	]+
+[ 	]*351[ 	]+\# Tests for op imm32 regl/m32
+[ 	]*352[ 	]+xacquire adc ecx,10000000
+[ 	]*353[ 	]+xacquire lock adc ecx,10000000
+[ 	]*354[ 	]+lock xacquire adc ecx,10000000
+[ 	]*355[ 	]+xrelease adc ecx,10000000
+[ 	]*356[ 	]+xrelease lock adc ecx,10000000
+[ 	]*357[ 	]+lock xrelease adc ecx,10000000
+[ 	]*358[ 	]+xacquire adc DWORD PTR \[rcx\],10000000
+[ 	]*359[ 	]+xrelease adc DWORD PTR \[rcx\],10000000
+[ 	]*360[ 	]+
+[ 	]*361[ 	]+\# Tests for op imm32 regq/m64
+[ 	]*362[ 	]+xacquire adc rcx,10000000
+[ 	]*363[ 	]+xacquire lock adc rcx,10000000
+[ 	]*364[ 	]+lock xacquire adc rcx,10000000
+[ 	]*365[ 	]+xrelease adc rcx,10000000
+[ 	]*366[ 	]+xrelease lock adc rcx,10000000
+[ 	]*367[ 	]+lock xrelease adc rcx,10000000
+[ 	]*368[ 	]+xacquire adc QWORD PTR \[rcx\],10000000
+[ 	]*369[ 	]+xrelease adc QWORD PTR \[rcx\],10000000
+[ 	]*370[ 	]+
+[ 	]*371[ 	]+\# Tests for op imm8 regs/m16
+[ 	]*372[ 	]+xacquire adc cx,100
+[ 	]*373[ 	]+xacquire lock adc cx,100
+[ 	]*374[ 	]+lock xacquire adc cx,100
+[ 	]*375[ 	]+xrelease adc cx,100
+[ 	]*376[ 	]+xrelease lock adc cx,100
+[ 	]*377[ 	]+lock xrelease adc cx,100
+[ 	]*378[ 	]+xacquire adc WORD PTR \[rcx\],100
+[ 	]*379[ 	]+xrelease adc WORD PTR \[rcx\],100
+[ 	]*380[ 	]+
+[ 	]*381[ 	]+\# Tests for op imm8 regl/m32
+[ 	]*382[ 	]+xacquire adc ecx,100
+[ 	]*383[ 	]+xacquire lock adc ecx,100
+[ 	]*384[ 	]+lock xacquire adc ecx,100
+[ 	]*385[ 	]+xrelease adc ecx,100
+[ 	]*386[ 	]+xrelease lock adc ecx,100
+[ 	]*387[ 	]+lock xrelease adc ecx,100
+[ 	]*388[ 	]+xacquire adc DWORD PTR \[rcx\],100
+[ 	]*389[ 	]+xrelease adc DWORD PTR \[rcx\],100
+[ 	]*390[ 	]+
+[ 	]*391[ 	]+\# Tests for op imm8 regq/m64
+[ 	]*392[ 	]+xacquire adc rcx,100
+[ 	]*393[ 	]+xacquire lock adc rcx,100
+[ 	]*394[ 	]+lock xacquire adc rcx,100
+[ 	]*395[ 	]+xrelease adc rcx,100
+[ 	]*396[ 	]+xrelease lock adc rcx,100
+[ 	]*397[ 	]+lock xrelease adc rcx,100
+[ 	]*398[ 	]+xacquire adc QWORD PTR \[rcx\],100
+[ 	]*399[ 	]+xrelease adc QWORD PTR \[rcx\],100
+GAS LISTING .*
+
+
+[ 	]*400[ 	]+
+[ 	]*401[ 	]+\# Tests for op imm8 regb/m8
+[ 	]*402[ 	]+xacquire adc cl,100
+[ 	]*403[ 	]+xacquire lock adc cl,100
+[ 	]*404[ 	]+lock xacquire adc cl,100
+[ 	]*405[ 	]+xrelease adc cl,100
+[ 	]*406[ 	]+xrelease lock adc cl,100
+[ 	]*407[ 	]+lock xrelease adc cl,100
+[ 	]*408[ 	]+xacquire adc BYTE PTR \[rcx\],100
+[ 	]*409[ 	]+xrelease adc BYTE PTR \[rcx\],100
+[ 	]*410[ 	]+
+[ 	]*411[ 	]+\# Tests for op regb regb/m8
+[ 	]*412[ 	]+\# Tests for op regb/m8 regb
+[ 	]*413[ 	]+xacquire adc cl,al
+[ 	]*414[ 	]+xacquire lock adc cl,al
+[ 	]*415[ 	]+lock xacquire adc cl,al
+[ 	]*416[ 	]+xrelease adc cl,al
+[ 	]*417[ 	]+xrelease lock adc cl,al
+[ 	]*418[ 	]+lock xrelease adc cl,al
+[ 	]*419[ 	]+xacquire adc BYTE PTR \[rcx\],al
+[ 	]*420[ 	]+xrelease adc BYTE PTR \[rcx\],al
+[ 	]*421[ 	]+xacquire adc al,cl
+[ 	]*422[ 	]+xacquire lock adc al,cl
+[ 	]*423[ 	]+lock xacquire adc al,cl
+[ 	]*424[ 	]+xrelease adc al,cl
+[ 	]*425[ 	]+xrelease lock adc al,cl
+[ 	]*426[ 	]+lock xrelease adc al,cl
+[ 	]*427[ 	]+xacquire adc al,BYTE PTR \[rcx\]
+[ 	]*428[ 	]+xacquire lock adc al,BYTE PTR \[rcx\]
+[ 	]*429[ 	]+lock xacquire adc al,BYTE PTR \[rcx\]
+[ 	]*430[ 	]+xrelease adc al,BYTE PTR \[rcx\]
+[ 	]*431[ 	]+xrelease lock adc al,BYTE PTR \[rcx\]
+[ 	]*432[ 	]+lock xrelease adc al,BYTE PTR \[rcx\]
+[ 	]*433[ 	]+
+[ 	]*434[ 	]+\# Tests for op regs regs/m16
+[ 	]*435[ 	]+\# Tests for op regs/m16 regs
+[ 	]*436[ 	]+xacquire adc cx,ax
+[ 	]*437[ 	]+xacquire lock adc cx,ax
+[ 	]*438[ 	]+lock xacquire adc cx,ax
+[ 	]*439[ 	]+xrelease adc cx,ax
+[ 	]*440[ 	]+xrelease lock adc cx,ax
+[ 	]*441[ 	]+lock xrelease adc cx,ax
+[ 	]*442[ 	]+xacquire adc WORD PTR \[rcx\],ax
+[ 	]*443[ 	]+xrelease adc WORD PTR \[rcx\],ax
+[ 	]*444[ 	]+xacquire adc ax,cx
+[ 	]*445[ 	]+xacquire lock adc ax,cx
+[ 	]*446[ 	]+lock xacquire adc ax,cx
+[ 	]*447[ 	]+xrelease adc ax,cx
+[ 	]*448[ 	]+xrelease lock adc ax,cx
+[ 	]*449[ 	]+lock xrelease adc ax,cx
+[ 	]*450[ 	]+xacquire adc ax,WORD PTR \[rcx\]
+[ 	]*451[ 	]+xacquire lock adc ax,WORD PTR \[rcx\]
+[ 	]*452[ 	]+lock xacquire adc ax,WORD PTR \[rcx\]
+[ 	]*453[ 	]+xrelease adc ax,WORD PTR \[rcx\]
+[ 	]*454[ 	]+xrelease lock adc ax,WORD PTR \[rcx\]
+[ 	]*455[ 	]+lock xrelease adc ax,WORD PTR \[rcx\]
+[ 	]*456[ 	]+
+GAS LISTING .*
+
+
+[ 	]*457[ 	]+\# Tests for op regl regl/m32
+[ 	]*458[ 	]+\# Tests for op regl/m32 regl
+[ 	]*459[ 	]+xacquire adc ecx,eax
+[ 	]*460[ 	]+xacquire lock adc ecx,eax
+[ 	]*461[ 	]+lock xacquire adc ecx,eax
+[ 	]*462[ 	]+xrelease adc ecx,eax
+[ 	]*463[ 	]+xrelease lock adc ecx,eax
+[ 	]*464[ 	]+lock xrelease adc ecx,eax
+[ 	]*465[ 	]+xacquire adc DWORD PTR \[rcx\],eax
+[ 	]*466[ 	]+xrelease adc DWORD PTR \[rcx\],eax
+[ 	]*467[ 	]+xacquire adc eax,ecx
+[ 	]*468[ 	]+xacquire lock adc eax,ecx
+[ 	]*469[ 	]+lock xacquire adc eax,ecx
+[ 	]*470[ 	]+xrelease adc eax,ecx
+[ 	]*471[ 	]+xrelease lock adc eax,ecx
+[ 	]*472[ 	]+lock xrelease adc eax,ecx
+[ 	]*473[ 	]+xacquire adc eax,DWORD PTR \[rcx\]
+[ 	]*474[ 	]+xacquire lock adc eax,DWORD PTR \[rcx\]
+[ 	]*475[ 	]+lock xacquire adc eax,DWORD PTR \[rcx\]
+[ 	]*476[ 	]+xrelease adc eax,DWORD PTR \[rcx\]
+[ 	]*477[ 	]+xrelease lock adc eax,DWORD PTR \[rcx\]
+[ 	]*478[ 	]+lock xrelease adc eax,DWORD PTR \[rcx\]
+[ 	]*479[ 	]+
+[ 	]*480[ 	]+\# Tests for op regq regq/m64
+[ 	]*481[ 	]+\# Tests for op regq/m64 regq
+[ 	]*482[ 	]+xacquire adc rcx,rax
+[ 	]*483[ 	]+xacquire lock adc rcx,rax
+[ 	]*484[ 	]+lock xacquire adc rcx,rax
+[ 	]*485[ 	]+xrelease adc rcx,rax
+[ 	]*486[ 	]+xrelease lock adc rcx,rax
+[ 	]*487[ 	]+lock xrelease adc rcx,rax
+[ 	]*488[ 	]+xacquire adc QWORD PTR \[rcx\],rax
+[ 	]*489[ 	]+xrelease adc QWORD PTR \[rcx\],rax
+[ 	]*490[ 	]+xacquire adc rax,rcx
+[ 	]*491[ 	]+xacquire lock adc rax,rcx
+[ 	]*492[ 	]+lock xacquire adc rax,rcx
+[ 	]*493[ 	]+xrelease adc rax,rcx
+[ 	]*494[ 	]+xrelease lock adc rax,rcx
+[ 	]*495[ 	]+lock xrelease adc rax,rcx
+[ 	]*496[ 	]+xacquire adc rax,QWORD PTR \[rcx\]
+[ 	]*497[ 	]+xacquire lock adc rax,QWORD PTR \[rcx\]
+[ 	]*498[ 	]+lock xacquire adc rax,QWORD PTR \[rcx\]
+[ 	]*499[ 	]+xrelease adc rax,QWORD PTR \[rcx\]
+[ 	]*500[ 	]+xrelease lock adc rax,QWORD PTR \[rcx\]
+[ 	]*501[ 	]+lock xrelease adc rax,QWORD PTR \[rcx\]
+[ 	]*502[ 	]+
+[ 	]*503[ 	]+\# Tests for op regs, regs/m16
+[ 	]*504[ 	]+xacquire btc cx,ax
+[ 	]*505[ 	]+xacquire lock btc cx,ax
+[ 	]*506[ 	]+lock xacquire btc cx,ax
+[ 	]*507[ 	]+xrelease btc cx,ax
+[ 	]*508[ 	]+xrelease lock btc cx,ax
+[ 	]*509[ 	]+lock xrelease btc cx,ax
+[ 	]*510[ 	]+xacquire btc WORD PTR \[rcx\],ax
+[ 	]*511[ 	]+xrelease btc WORD PTR \[rcx\],ax
+[ 	]*512[ 	]+
+[ 	]*513[ 	]+\# Tests for op regl regl/m32
+GAS LISTING .*
+
+
+[ 	]*514[ 	]+xacquire btc ecx,eax
+[ 	]*515[ 	]+xacquire lock btc ecx,eax
+[ 	]*516[ 	]+lock xacquire btc ecx,eax
+[ 	]*517[ 	]+xrelease btc ecx,eax
+[ 	]*518[ 	]+xrelease lock btc ecx,eax
+[ 	]*519[ 	]+lock xrelease btc ecx,eax
+[ 	]*520[ 	]+xacquire btc DWORD PTR \[rcx\],eax
+[ 	]*521[ 	]+xrelease btc DWORD PTR \[rcx\],eax
+[ 	]*522[ 	]+
+[ 	]*523[ 	]+\# Tests for op regq regq/m64
+[ 	]*524[ 	]+xacquire btc rcx,rax
+[ 	]*525[ 	]+xacquire lock btc rcx,rax
+[ 	]*526[ 	]+lock xacquire btc rcx,rax
+[ 	]*527[ 	]+xrelease btc rcx,rax
+[ 	]*528[ 	]+xrelease lock btc rcx,rax
+[ 	]*529[ 	]+lock xrelease btc rcx,rax
+[ 	]*530[ 	]+xacquire btc QWORD PTR \[rcx\],rax
+[ 	]*531[ 	]+xrelease btc QWORD PTR \[rcx\],rax
+[ 	]*532[ 	]+
+[ 	]*533[ 	]+\# Tests for op regb/m8
+[ 	]*534[ 	]+xacquire dec cl
+[ 	]*535[ 	]+xacquire lock dec cl
+[ 	]*536[ 	]+lock xacquire dec cl
+[ 	]*537[ 	]+xrelease dec cl
+[ 	]*538[ 	]+xrelease lock dec cl
+[ 	]*539[ 	]+lock xrelease dec cl
+[ 	]*540[ 	]+xacquire dec BYTE PTR \[rcx\]
+[ 	]*541[ 	]+xrelease dec BYTE PTR \[rcx\]
+[ 	]*542[ 	]+
+[ 	]*543[ 	]+\# Tests for op regs/m16
+[ 	]*544[ 	]+xacquire dec cx
+[ 	]*545[ 	]+xacquire lock dec cx
+[ 	]*546[ 	]+lock xacquire dec cx
+[ 	]*547[ 	]+xrelease dec cx
+[ 	]*548[ 	]+xrelease lock dec cx
+[ 	]*549[ 	]+lock xrelease dec cx
+[ 	]*550[ 	]+xacquire dec WORD PTR \[rcx\]
+[ 	]*551[ 	]+xrelease dec WORD PTR \[rcx\]
+[ 	]*552[ 	]+
+[ 	]*553[ 	]+\# Tests for op regl/m32
+[ 	]*554[ 	]+xacquire dec ecx
+[ 	]*555[ 	]+xacquire lock dec ecx
+[ 	]*556[ 	]+lock xacquire dec ecx
+[ 	]*557[ 	]+xrelease dec ecx
+[ 	]*558[ 	]+xrelease lock dec ecx
+[ 	]*559[ 	]+lock xrelease dec ecx
+[ 	]*560[ 	]+xacquire dec DWORD PTR \[rcx\]
+[ 	]*561[ 	]+xrelease dec DWORD PTR \[rcx\]
+[ 	]*562[ 	]+
+[ 	]*563[ 	]+\# Tests for op regq/m64
+[ 	]*564[ 	]+xacquire dec rcx
+[ 	]*565[ 	]+xacquire lock dec rcx
+[ 	]*566[ 	]+lock xacquire dec rcx
+[ 	]*567[ 	]+xrelease dec rcx
+[ 	]*568[ 	]+xrelease lock dec rcx
+[ 	]*569[ 	]+lock xrelease dec rcx
+[ 	]*570[ 	]+xacquire dec QWORD PTR \[rcx\]
+GAS LISTING .*
+
+
+[ 	]*571[ 	]+xrelease dec QWORD PTR \[rcx\]
+[ 	]*572[ 	]+
+[ 	]*573[ 	]+\# Tests for op m64
+[ 	]*574[ 	]+xacquire cmpxchg8b QWORD PTR \[rcx\]
+[ 	]*575[ 	]+xrelease cmpxchg8b QWORD PTR \[rcx\]
+[ 	]*576[ 	]+
+[ 	]*577[ 	]+\# Tests for op regb, regb/m8
+[ 	]*578[ 	]+xacquire cmpxchg al,cl
+[ 	]*579[ 	]+xacquire lock cmpxchg al,cl
+[ 	]*580[ 	]+lock xacquire cmpxchg al,cl
+[ 	]*581[ 	]+xrelease cmpxchg al,cl
+[ 	]*582[ 	]+xrelease lock cmpxchg al,cl
+[ 	]*583[ 	]+lock xrelease cmpxchg al,cl
+[ 	]*584[ 	]+xacquire cmpxchg BYTE PTR \[rcx\],cl
+[ 	]*585[ 	]+xrelease cmpxchg BYTE PTR \[rcx\],cl
diff --git a/gas/testsuite/gas/i386/x86-64-hlebad.s b/gas/testsuite/gas/i386/x86-64-hlebad.s
new file mode 100644
index 0000000..f79633c
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-hlebad.s
@@ -0,0 +1,585 @@
+# Check 64bit unsupported HLE instructions
+
+	.allow_index_reg
+	.text
+_start:
+
+# Tests for op imm8 al
+	xacquire adc $100,%al
+	xacquire lock adc $100,%al
+	lock xacquire adc $100,%al
+	xrelease adc $100,%al
+	xrelease lock adc $100,%al
+	lock xrelease adc $100,%al
+
+# Tests for op imm16 ax
+	xacquire adc $1000,%ax
+	xacquire lock adc $1000,%ax
+	lock xacquire adc $1000,%ax
+	xrelease adc $1000,%ax
+	xrelease lock adc $1000,%ax
+	lock xrelease adc $1000,%ax
+
+# Tests for op imm32 eax
+	xacquire adc $10000000,%eax
+	xacquire lock adc $10000000,%eax
+	lock xacquire adc $10000000,%eax
+	xrelease adc $10000000,%eax
+	xrelease lock adc $10000000,%eax
+	lock xrelease adc $10000000,%eax
+
+
+# Tests for op imm32 rax
+	xacquire adc $10000000,%rax
+	xacquire lock adc $10000000,%rax
+	lock xacquire adc $10000000,%rax
+	xrelease adc $10000000,%rax
+	xrelease lock adc $10000000,%rax
+	lock xrelease adc $10000000,%rax
+
+# Tests for op imm8 regb/m8
+	xacquire adcb $100,%cl
+	xacquire lock adcb $100,%cl
+	lock xacquire adcb $100,%cl
+	xrelease adcb $100,%cl
+	xrelease lock adcb $100,%cl
+	lock xrelease adcb $100,%cl
+	xacquire adcb $100,(%rcx)
+	xrelease adcb $100,(%rcx)
+
+# Tests for op imm16 regs/m16
+	xacquire adcw $1000,%cx
+	xacquire lock adcw $1000,%cx
+	lock xacquire adcw $1000,%cx
+	xrelease adcw $1000,%cx
+	xrelease lock adcw $1000,%cx
+	lock xrelease adcw $1000,%cx
+	xacquire adcw $1000,(%rcx)
+	xrelease adcw $1000,(%rcx)
+
+# Tests for op imm32 regl/m32
+	xacquire adcl $10000000,%ecx
+	xacquire lock adcl $10000000,%ecx
+	lock xacquire adcl $10000000,%ecx
+	xrelease adcl $10000000,%ecx
+	xrelease lock adcl $10000000,%ecx
+	lock xrelease adcl $10000000,%ecx
+	xacquire adcl $10000000,(%rcx)
+	xrelease adcl $10000000,(%rcx)
+
+# Tests for op imm32 regq/m64
+	xacquire adcq $10000000,%rcx
+	xacquire lock adcq $10000000,%rcx
+	lock xacquire adcq $10000000,%rcx
+	xrelease adcq $10000000,%rcx
+	xrelease lock adcq $10000000,%rcx
+	lock xrelease adcq $10000000,%rcx
+	xacquire adcq $10000000,(%rcx)
+	xrelease adcq $10000000,(%rcx)
+
+# Tests for op imm8 regs/m16
+	xacquire adcw $100,%cx
+	xacquire lock adcw $100,%cx
+	lock xacquire adcw $100,%cx
+	xrelease adcw $100,%cx
+	xrelease lock adcw $100,%cx
+	lock xrelease adcw $100,%cx
+	xacquire adcw $100,(%rcx)
+	xrelease adcw $100,(%rcx)
+
+# Tests for op imm8 regl/m32
+	xacquire adcl $100,%ecx
+	xacquire lock adcl $100,%ecx
+	lock xacquire adcl $100,%ecx
+	xrelease adcl $100,%ecx
+	xrelease lock adcl $100,%ecx
+	lock xrelease adcl $100,%ecx
+	xacquire adcl $100,(%rcx)
+	xrelease adcl $100,(%rcx)
+
+# Tests for op imm8 regq/m64
+	xacquire adcq $100,%rcx
+	xacquire lock adcq $100,%rcx
+	lock xacquire adcq $100,%rcx
+	xrelease adcq $100,%rcx
+	xrelease lock adcq $100,%rcx
+	lock xrelease adcq $100,%rcx
+	xacquire adcq $100,(%rcx)
+	xrelease adcq $100,(%rcx)
+
+# Tests for op imm8 regb/m8
+	xacquire adcb $100,%cl
+	xacquire lock adcb $100,%cl
+	lock xacquire adcb $100,%cl
+	xrelease adcb $100,%cl
+	xrelease lock adcb $100,%cl
+	lock xrelease adcb $100,%cl
+	xacquire adcb $100,(%rcx)
+	xrelease adcb $100,(%rcx)
+
+# Tests for op regb regb/m8
+# Tests for op regb/m8 regb
+	xacquire adcb %al,%cl
+	xacquire lock adcb %al,%cl
+	lock xacquire adcb %al,%cl
+	xrelease adcb %al,%cl
+	xrelease lock adcb %al,%cl
+	lock xrelease adcb %al,%cl
+	xacquire adcb %al,(%rcx)
+	xrelease adcb %al,(%rcx)
+	xacquire adcb %cl,%al
+	xacquire lock adcb %cl,%al
+	lock xacquire adcb %cl,%al
+	xrelease adcb %cl,%al
+	xrelease lock adcb %cl,%al
+	lock xrelease adcb %cl,%al
+	xacquire adcb (%rcx),%al
+	xacquire lock adcb (%rcx),%al
+	lock xacquire adcb (%rcx),%al
+	xrelease adcb (%rcx),%al
+	xrelease lock adcb (%rcx),%al
+	lock xrelease adcb (%rcx),%al
+
+# Tests for op regs regs/m16
+# Tests for op regs/m16 regs
+	xacquire adcw %ax,%cx
+	xacquire lock adcw %ax,%cx
+	lock xacquire adcw %ax,%cx
+	xrelease adcw %ax,%cx
+	xrelease lock adcw %ax,%cx
+	lock xrelease adcw %ax,%cx
+	xacquire adcw %ax,(%rcx)
+	xrelease adcw %ax,(%rcx)
+	xacquire adcw %cx,%ax
+	xacquire lock adcw %cx,%ax
+	lock xacquire adcw %cx,%ax
+	xrelease adcw %cx,%ax
+	xrelease lock adcw %cx,%ax
+	lock xrelease adcw %cx,%ax
+	xacquire adcw (%rcx),%ax
+	xacquire lock adcw (%rcx),%ax
+	lock xacquire adcw (%rcx),%ax
+	xrelease adcw (%rcx),%ax
+	xrelease lock adcw (%rcx),%ax
+	lock xrelease adcw (%rcx),%ax
+
+# Tests for op regl regl/m32
+# Tests for op regl/m32 regl
+	xacquire adcl %eax,%ecx
+	xacquire lock adcl %eax,%ecx
+	lock xacquire adcl %eax,%ecx
+	xrelease adcl %eax,%ecx
+	xrelease lock adcl %eax,%ecx
+	lock xrelease adcl %eax,%ecx
+	xacquire adcl %eax,(%rcx)
+	xrelease adcl %eax,(%rcx)
+	xacquire adcl %ecx,%eax
+	xacquire lock adcl %ecx,%eax
+	lock xacquire adcl %ecx,%eax
+	xrelease adcl %ecx,%eax
+	xrelease lock adcl %ecx,%eax
+	lock xrelease adcl %ecx,%eax
+	xacquire adcl (%rcx),%eax
+	xacquire lock adcl (%rcx),%eax
+	lock xacquire adcl (%rcx),%eax
+	xrelease adcl (%rcx),%eax
+	xrelease lock adcl (%rcx),%eax
+	lock xrelease adcl (%rcx),%eax
+
+# Tests for op regq regq/m64
+# Tests for op regq/m64 regq
+	xacquire adcq %rax,%rcx
+	xacquire lock adcq %rax,%rcx
+	lock xacquire adcq %rax,%rcx
+	xrelease adcq %rax,%rcx
+	xrelease lock adcq %rax,%rcx
+	lock xrelease adcq %rax,%rcx
+	xacquire adcq %rax,(%rcx)
+	xrelease adcq %rax,(%rcx)
+	xacquire adcq %rcx,%rax
+	xacquire lock adcq %rcx,%rax
+	lock xacquire adcq %rcx,%rax
+	xrelease adcq %rcx,%rax
+	xrelease lock adcq %rcx,%rax
+	lock xrelease adcq %rcx,%rax
+	xacquire adcq (%rcx),%rax
+	xacquire lock adcq (%rcx),%rax
+	lock xacquire adcq (%rcx),%rax
+	xrelease adcq (%rcx),%rax
+	xrelease lock adcq (%rcx),%rax
+	lock xrelease adcq (%rcx),%rax
+
+# Tests for op regs, regs/m16
+	xacquire btcw %ax,%cx
+	xacquire lock btcw %ax,%cx
+	lock xacquire btcw %ax,%cx
+	xrelease btcw %ax,%cx
+	xrelease lock btcw %ax,%cx
+	lock xrelease btcw %ax,%cx
+	xacquire btcw %ax,(%rcx)
+	xrelease btcw %ax,(%rcx)
+
+# Tests for op regl regl/m32
+	xacquire btcl %eax,%ecx
+	xacquire lock btcl %eax,%ecx
+	lock xacquire btcl %eax,%ecx
+	xrelease btcl %eax,%ecx
+	xrelease lock btcl %eax,%ecx
+	lock xrelease btcl %eax,%ecx
+	xacquire btcl %eax,(%rcx)
+	xrelease btcl %eax,(%rcx)
+
+# Tests for op regq regq/m64
+	xacquire btcq %rax,%rcx
+	xacquire lock btcq %rax,%rcx
+	lock xacquire btcq %rax,%rcx
+	xrelease btcq %rax,%rcx
+	xrelease lock btcq %rax,%rcx
+	lock xrelease btcq %rax,%rcx
+	xacquire btcq %rax,(%rcx)
+	xrelease btcq %rax,(%rcx)
+
+# Tests for op regb/m8
+	xacquire decb %cl
+	xacquire lock decb %cl
+	lock xacquire decb %cl
+	xrelease decb %cl
+	xrelease lock decb %cl
+	lock xrelease decb %cl
+	xacquire decb (%rcx)
+	xrelease decb (%rcx)
+
+# Tests for op regs/m16
+	xacquire decw %cx
+	xacquire lock decw %cx
+	lock xacquire decw %cx
+	xrelease decw %cx
+	xrelease lock decw %cx
+	lock xrelease decw %cx
+	xacquire decw (%rcx)
+	xrelease decw (%rcx)
+
+# Tests for op regl/m32
+	xacquire decl %ecx
+	xacquire lock decl %ecx
+	lock xacquire decl %ecx
+	xrelease decl %ecx
+	xrelease lock decl %ecx
+	lock xrelease decl %ecx
+	xacquire decl (%rcx)
+	xrelease decl (%rcx)
+
+# Tests for op regq/m64
+	xacquire decq %rcx
+	xacquire lock decq %rcx
+	lock xacquire decq %rcx
+	xrelease decq %rcx
+	xrelease lock decq %rcx
+	lock xrelease decq %rcx
+	xacquire decq (%rcx)
+	xrelease decq (%rcx)
+
+# Tests for op m64
+	xacquire cmpxchg8bq (%rcx)
+	xrelease cmpxchg8bq (%rcx)
+
+# Tests for op regb, regb/m8
+	xacquire cmpxchgb %cl,%al
+	xacquire lock cmpxchgb %cl,%al
+	lock xacquire cmpxchgb %cl,%al
+	xrelease cmpxchgb %cl,%al
+	xrelease lock cmpxchgb %cl,%al
+	lock xrelease cmpxchgb %cl,%al
+	xacquire cmpxchgb %cl,(%rcx)
+	xrelease cmpxchgb %cl,(%rcx)
+
+	.intel_syntax noprefix
+
+# Tests for op imm8 al
+	xacquire adc al,100
+	xacquire lock adc al,100
+	lock xacquire adc al,100
+	xrelease adc al,100
+	xrelease lock adc al,100
+	lock xrelease adc al,100
+
+# Tests for op imm16 ax
+	xacquire adc ax,1000
+	xacquire lock adc ax,1000
+	lock xacquire adc ax,1000
+	xrelease adc ax,1000
+	xrelease lock adc ax,1000
+	lock xrelease adc ax,1000
+
+# Tests for op imm32 eax
+	xacquire adc eax,10000000
+	xacquire lock adc eax,10000000
+	lock xacquire adc eax,10000000
+	xrelease adc eax,10000000
+	xrelease lock adc eax,10000000
+	lock xrelease adc eax,10000000
+
+
+# Tests for op imm32 rax
+	xacquire adc rax,10000000
+	xacquire lock adc rax,10000000
+	lock xacquire adc rax,10000000
+	xrelease adc rax,10000000
+	xrelease lock adc rax,10000000
+	lock xrelease adc rax,10000000
+
+# Tests for op imm8 regb/m8
+	xacquire adc cl,100
+	xacquire lock adc cl,100
+	lock xacquire adc cl,100
+	xrelease adc cl,100
+	xrelease lock adc cl,100
+	lock xrelease adc cl,100
+	xacquire adc BYTE PTR [rcx],100
+	xrelease adc BYTE PTR [rcx],100
+
+# Tests for op imm16 regs/m16
+	xacquire adc cx,1000
+	xacquire lock adc cx,1000
+	lock xacquire adc cx,1000
+	xrelease adc cx,1000
+	xrelease lock adc cx,1000
+	lock xrelease adc cx,1000
+	xacquire adc WORD PTR [rcx],1000
+	xrelease adc WORD PTR [rcx],1000
+
+# Tests for op imm32 regl/m32
+	xacquire adc ecx,10000000
+	xacquire lock adc ecx,10000000
+	lock xacquire adc ecx,10000000
+	xrelease adc ecx,10000000
+	xrelease lock adc ecx,10000000
+	lock xrelease adc ecx,10000000
+	xacquire adc DWORD PTR [rcx],10000000
+	xrelease adc DWORD PTR [rcx],10000000
+
+# Tests for op imm32 regq/m64
+	xacquire adc rcx,10000000
+	xacquire lock adc rcx,10000000
+	lock xacquire adc rcx,10000000
+	xrelease adc rcx,10000000
+	xrelease lock adc rcx,10000000
+	lock xrelease adc rcx,10000000
+	xacquire adc QWORD PTR [rcx],10000000
+	xrelease adc QWORD PTR [rcx],10000000
+
+# Tests for op imm8 regs/m16
+	xacquire adc cx,100
+	xacquire lock adc cx,100
+	lock xacquire adc cx,100
+	xrelease adc cx,100
+	xrelease lock adc cx,100
+	lock xrelease adc cx,100
+	xacquire adc WORD PTR [rcx],100
+	xrelease adc WORD PTR [rcx],100
+
+# Tests for op imm8 regl/m32
+	xacquire adc ecx,100
+	xacquire lock adc ecx,100
+	lock xacquire adc ecx,100
+	xrelease adc ecx,100
+	xrelease lock adc ecx,100
+	lock xrelease adc ecx,100
+	xacquire adc DWORD PTR [rcx],100
+	xrelease adc DWORD PTR [rcx],100
+
+# Tests for op imm8 regq/m64
+	xacquire adc rcx,100
+	xacquire lock adc rcx,100
+	lock xacquire adc rcx,100
+	xrelease adc rcx,100
+	xrelease lock adc rcx,100
+	lock xrelease adc rcx,100
+	xacquire adc QWORD PTR [rcx],100
+	xrelease adc QWORD PTR [rcx],100
+
+# Tests for op imm8 regb/m8
+	xacquire adc cl,100
+	xacquire lock adc cl,100
+	lock xacquire adc cl,100
+	xrelease adc cl,100
+	xrelease lock adc cl,100
+	lock xrelease adc cl,100
+	xacquire adc BYTE PTR [rcx],100
+	xrelease adc BYTE PTR [rcx],100
+
+# Tests for op regb regb/m8
+# Tests for op regb/m8 regb
+	xacquire adc cl,al
+	xacquire lock adc cl,al
+	lock xacquire adc cl,al
+	xrelease adc cl,al
+	xrelease lock adc cl,al
+	lock xrelease adc cl,al
+	xacquire adc BYTE PTR [rcx],al
+	xrelease adc BYTE PTR [rcx],al
+	xacquire adc al,cl
+	xacquire lock adc al,cl
+	lock xacquire adc al,cl
+	xrelease adc al,cl
+	xrelease lock adc al,cl
+	lock xrelease adc al,cl
+	xacquire adc al,BYTE PTR [rcx]
+	xacquire lock adc al,BYTE PTR [rcx]
+	lock xacquire adc al,BYTE PTR [rcx]
+	xrelease adc al,BYTE PTR [rcx]
+	xrelease lock adc al,BYTE PTR [rcx]
+	lock xrelease adc al,BYTE PTR [rcx]
+
+# Tests for op regs regs/m16
+# Tests for op regs/m16 regs
+	xacquire adc cx,ax
+	xacquire lock adc cx,ax
+	lock xacquire adc cx,ax
+	xrelease adc cx,ax
+	xrelease lock adc cx,ax
+	lock xrelease adc cx,ax
+	xacquire adc WORD PTR [rcx],ax
+	xrelease adc WORD PTR [rcx],ax
+	xacquire adc ax,cx
+	xacquire lock adc ax,cx
+	lock xacquire adc ax,cx
+	xrelease adc ax,cx
+	xrelease lock adc ax,cx
+	lock xrelease adc ax,cx
+	xacquire adc ax,WORD PTR [rcx]
+	xacquire lock adc ax,WORD PTR [rcx]
+	lock xacquire adc ax,WORD PTR [rcx]
+	xrelease adc ax,WORD PTR [rcx]
+	xrelease lock adc ax,WORD PTR [rcx]
+	lock xrelease adc ax,WORD PTR [rcx]
+
+# Tests for op regl regl/m32
+# Tests for op regl/m32 regl
+	xacquire adc ecx,eax
+	xacquire lock adc ecx,eax
+	lock xacquire adc ecx,eax
+	xrelease adc ecx,eax
+	xrelease lock adc ecx,eax
+	lock xrelease adc ecx,eax
+	xacquire adc DWORD PTR [rcx],eax
+	xrelease adc DWORD PTR [rcx],eax
+	xacquire adc eax,ecx
+	xacquire lock adc eax,ecx
+	lock xacquire adc eax,ecx
+	xrelease adc eax,ecx
+	xrelease lock adc eax,ecx
+	lock xrelease adc eax,ecx
+	xacquire adc eax,DWORD PTR [rcx]
+	xacquire lock adc eax,DWORD PTR [rcx]
+	lock xacquire adc eax,DWORD PTR [rcx]
+	xrelease adc eax,DWORD PTR [rcx]
+	xrelease lock adc eax,DWORD PTR [rcx]
+	lock xrelease adc eax,DWORD PTR [rcx]
+
+# Tests for op regq regq/m64
+# Tests for op regq/m64 regq
+	xacquire adc rcx,rax
+	xacquire lock adc rcx,rax
+	lock xacquire adc rcx,rax
+	xrelease adc rcx,rax
+	xrelease lock adc rcx,rax
+	lock xrelease adc rcx,rax
+	xacquire adc QWORD PTR [rcx],rax
+	xrelease adc QWORD PTR [rcx],rax
+	xacquire adc rax,rcx
+	xacquire lock adc rax,rcx
+	lock xacquire adc rax,rcx
+	xrelease adc rax,rcx
+	xrelease lock adc rax,rcx
+	lock xrelease adc rax,rcx
+	xacquire adc rax,QWORD PTR [rcx]
+	xacquire lock adc rax,QWORD PTR [rcx]
+	lock xacquire adc rax,QWORD PTR [rcx]
+	xrelease adc rax,QWORD PTR [rcx]
+	xrelease lock adc rax,QWORD PTR [rcx]
+	lock xrelease adc rax,QWORD PTR [rcx]
+
+# Tests for op regs, regs/m16
+	xacquire btc cx,ax
+	xacquire lock btc cx,ax
+	lock xacquire btc cx,ax
+	xrelease btc cx,ax
+	xrelease lock btc cx,ax
+	lock xrelease btc cx,ax
+	xacquire btc WORD PTR [rcx],ax
+	xrelease btc WORD PTR [rcx],ax
+
+# Tests for op regl regl/m32
+	xacquire btc ecx,eax
+	xacquire lock btc ecx,eax
+	lock xacquire btc ecx,eax
+	xrelease btc ecx,eax
+	xrelease lock btc ecx,eax
+	lock xrelease btc ecx,eax
+	xacquire btc DWORD PTR [rcx],eax
+	xrelease btc DWORD PTR [rcx],eax
+
+# Tests for op regq regq/m64
+	xacquire btc rcx,rax
+	xacquire lock btc rcx,rax
+	lock xacquire btc rcx,rax
+	xrelease btc rcx,rax
+	xrelease lock btc rcx,rax
+	lock xrelease btc rcx,rax
+	xacquire btc QWORD PTR [rcx],rax
+	xrelease btc QWORD PTR [rcx],rax
+
+# Tests for op regb/m8
+	xacquire dec cl
+	xacquire lock dec cl
+	lock xacquire dec cl
+	xrelease dec cl
+	xrelease lock dec cl
+	lock xrelease dec cl
+	xacquire dec BYTE PTR [rcx]
+	xrelease dec BYTE PTR [rcx]
+
+# Tests for op regs/m16
+	xacquire dec cx
+	xacquire lock dec cx
+	lock xacquire dec cx
+	xrelease dec cx
+	xrelease lock dec cx
+	lock xrelease dec cx
+	xacquire dec WORD PTR [rcx]
+	xrelease dec WORD PTR [rcx]
+
+# Tests for op regl/m32
+	xacquire dec ecx
+	xacquire lock dec ecx
+	lock xacquire dec ecx
+	xrelease dec ecx
+	xrelease lock dec ecx
+	lock xrelease dec ecx
+	xacquire dec DWORD PTR [rcx]
+	xrelease dec DWORD PTR [rcx]
+
+# Tests for op regq/m64
+	xacquire dec rcx
+	xacquire lock dec rcx
+	lock xacquire dec rcx
+	xrelease dec rcx
+	xrelease lock dec rcx
+	lock xrelease dec rcx
+	xacquire dec QWORD PTR [rcx]
+	xrelease dec QWORD PTR [rcx]
+
+# Tests for op m64
+	xacquire cmpxchg8b QWORD PTR [rcx]
+	xrelease cmpxchg8b QWORD PTR [rcx]
+
+# Tests for op regb, regb/m8
+	xacquire cmpxchg al,cl
+	xacquire lock cmpxchg al,cl
+	lock xacquire cmpxchg al,cl
+	xrelease cmpxchg al,cl
+	xrelease lock cmpxchg al,cl
+	lock xrelease cmpxchg al,cl
+	xacquire cmpxchg BYTE PTR [rcx],cl
+	xrelease cmpxchg BYTE PTR [rcx],cl
diff --git a/gas/testsuite/gas/i386/x86-64-rtm-intel.d b/gas/testsuite/gas/i386/x86-64-rtm-intel.d
new file mode 100644
index 0000000..e79c4cb
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-rtm-intel.d
@@ -0,0 +1,20 @@
+#objdump: -dwMintel
+#name: x86-64 RTM insns (Intel disassembly)
+#source: x86-64-rtm.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ 	]*[a-f0-9]+:	c6 f8 08             	xabort 0x8
+[ 	]*[a-f0-9]+:	c7 f8 fa ff ff ff    	xbegin 3 <foo\+0x3>
+[ 	]*[a-f0-9]+:	c7 f8 00 00 00 00    	xbegin f <foo\+0xf>
+[ 	]*[a-f0-9]+:	0f 01 d5             	xend   
+[ 	]*[a-f0-9]+:	c6 f8 08             	xabort 0x8
+[ 	]*[a-f0-9]+:	c7 f8 fa ff ff ff    	xbegin 15 <foo\+0x15>
+[ 	]*[a-f0-9]+:	c7 f8 00 00 00 00    	xbegin 21 <foo\+0x21>
+[ 	]*[a-f0-9]+:	0f 01 d5             	xend   
+[ 	]*[a-f0-9]+:	0f 01 d6             	xtest  
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-rtm.d b/gas/testsuite/gas/i386/x86-64-rtm.d
new file mode 100644
index 0000000..6cb8a72
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-rtm.d
@@ -0,0 +1,19 @@
+#objdump: -dw
+#name: x86-64 RTM insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <foo>:
+[ 	]*[a-f0-9]+:	c6 f8 08             	xabort \$0x8
+[ 	]*[a-f0-9]+:	c7 f8 fa ff ff ff    	xbeginq 3 <foo\+0x3>
+[ 	]*[a-f0-9]+:	c7 f8 00 00 00 00    	xbeginq f <foo\+0xf>
+[ 	]*[a-f0-9]+:	0f 01 d5             	xend   
+[ 	]*[a-f0-9]+:	c6 f8 08             	xabort \$0x8
+[ 	]*[a-f0-9]+:	c7 f8 fa ff ff ff    	xbeginq 15 <foo\+0x15>
+[ 	]*[a-f0-9]+:	c7 f8 00 00 00 00    	xbeginq 21 <foo\+0x21>
+[ 	]*[a-f0-9]+:	0f 01 d5             	xend   
+[ 	]*[a-f0-9]+:	0f 01 d6             	xtest  
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-rtm.s b/gas/testsuite/gas/i386/x86-64-rtm.s
new file mode 100644
index 0000000..17a1402
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-rtm.s
@@ -0,0 +1,19 @@
+# Check 64bit RTM new instructions.
+
+	.text
+foo:
+	xabort $0x8
+1:
+	xbegin 1b
+	xbegin 2f
+2:
+	xend
+
+	.intel_syntax noprefix
+	xabort 0x8
+1:
+	xbegin 1b
+	xbegin 2f
+2:
+	xend
+	xtest